SYSRST_CTRL Simulation Results

Wednesday October 25 2023 19:02:24 UTC

GitHub Revision: `36fe17501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 73206971735528051817380869634782189547246915888580460230181224241798087620702

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	3.910s	2.117ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	4.970s	2.470ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.310s	2.399ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.470s	2.535ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	10.130s	6.031ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.180s	2.075ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.898m	41.048ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.750s	2.891ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.360s	2.142ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.180s	2.075ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.750s	2.891ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.067m	118.289ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.290m	49.085ms	0	100	0.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	5.620s	3.139ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.560s	4.089ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	4.730s	2.515ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.970s	2.075ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	7.580s	4.425ms	50	50	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	4.760s	2.620ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.830s	5.189ms	50	50	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	59.730s	38.606ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	2.284m	87.229ms	50	50	100.00
V2	alert_test	sysrst_ctrl_alert_test	3.770s	2.015ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.850s	2.023ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	5.820s	2.187ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	5.820s	2.187ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	10.130s	6.031ms	5	5	100.00
		sysrst_ctrl_csr_rw	4.180s	2.075ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.750s	2.891ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	25.580s	9.477ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	10.130s	6.031ms	5	5	100.00
		sysrst_ctrl_csr_rw	4.180s	2.075ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	8.750s	2.891ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	25.580s	9.477ms	20	20	100.00
V2		TOTAL			592	692	85.55
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.082m	42.019ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.161m	42.511ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.161m	42.511ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	7.310s	6.010ms	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			782	932	83.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.95	97.93	94.86	100.00	79.49	97.01	94.01	66.35

Failure Buckets

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-*

has 100 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 100 failures.

0.sysrst_ctrl_combo_detect_with_pre_cond.79541301975866138764314731370005274048032721466499008382803772140106944082000
Line 544, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 49085268838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
  UVM_ERROR @ 49085268838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4
  UVM_INFO @ 49085268838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sysrst_ctrl_combo_detect_with_pre_cond.20915513656860623666993388562627177595476417612171573022010266467037366430230
Line 544, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 49085268838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
  UVM_ERROR @ 49085268838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(9) vs exp(5) +/-4
  UVM_INFO @ 49085268838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 98 more failures.

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 50 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 50 failures.

0.sysrst_ctrl_stress_all_with_rand_reset.5365876010103389694535004659583040360759419997967736689066674976564219337678
Line 516, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5367768838 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 6010268838 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6010268838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sysrst_ctrl_stress_all_with_rand_reset.115556283430235603085156960133903516599760034343640927546088334213253172080055
Line 516, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5367768838 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 6010268838 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:214) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6010268838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.