Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1898

1

T14

8

T18

7

T19

2

auto[1]

601

1

T14

6

T18

1

T19

2

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T14

8

T18

6

T59

13

auto[1]

583

1

T14

6

T18

2

T19

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1907

1

T14

8

T18

7

T59

13

auto[1]

592

1

T14

6

T18

1

T19

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1864

1

T14

6

T18

8

T19

2

auto[1]

635

1

T14

8

T19

2

T59

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T14

14

T18

8

T19

4

auto[1]

153

1

T41

2

T58

2

T60

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2226

1

T14

14

T18

7

T19

4

auto[1]

273

1

T18

1

T38

4

T58

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2281

1

T14

14

T18

8

T19

4

auto[1]

218

1

T38

2

T41

8

T60

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2294

1

T14

14

T18

6

T19

4

auto[1]

205

1

T18

2

T38

2

T41

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2280

1

T14

14

T18

7

T19

4

auto[1]

219

1

T18

1

T38

2

T58

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1925

1

T14

13

T18

8

T59

13

auto[1]

574

1

T14

1

T19

4

T59

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	761	1			T14	6		T19	4		T59	16
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	50	1			T44	5		T356	7		T253	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	82	1			T250	2		T352	3		T357	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	19	1			T58	1		T360	4		T361	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	76	1			T18	2		T270	4		T362	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	13	1			T44	3		T269	2		T363	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	38	1			T60	1		T362	3		T253	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	3	1			T44	3		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	80	1			T41	5		T60	1		T105	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T42	4		T287	1		T354	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	12	1			T269	2		T270	1		T363	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T358	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	28	1			T270	2		T272	10		T364	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T41	1		T365	2		T366	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T367	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	115	1			T58	2		T61	3		T270	7
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	22	1			T60	1		T340	16		T345	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	36	1			T18	1		T363	3		T368	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T287	6		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	13	1			T38	2		T60	1		T90	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	17	1			T269	4		T369	4		T370	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	12	1			T272	8		T371	1		T372	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	7	1			T38	2		T345	5		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	4	1			T373	4		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

127

1

T59

13

T81

10

T339

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

122

1

T60

1

T282

11

T270

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

69

1

T38

2

T128

6

T273

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

76

1

T40

12

T374

8

T340

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T38

2

T58

1

T235

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

64

1

T158

4

T60

1

T269

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T39

4

T43

1

T178

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

74

1

T60

1

T362

3

T357

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

32

1

T18

1

T178

1

T363

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

37

1

T81

4

T44

5

T269

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T61

3

T93

3

T108

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

71

1

T128

4

T287

6

T93

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

47

1

T287

20

T168

1

T343

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T128

2

T58

1

T342

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T375

1

T376

2

T346

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

104

1

T18

2

T41

1

T58

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

48

1

T105

4

T90

3

T369

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

37

1

T42

4

T81

4

T272

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T40

2

T60

1

T235

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T41

5

T39

1

T288

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T269

2

T250

3

T168

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T341

2

T377

3

T378

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T67

1

T76

1

T93

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T339

1

T186

4

T338

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T14

5

T67

2

T339

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T59

1

T66

2

T235

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T14

1

T19

2

T59

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T273

3

T250

2

T379

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T40

2

T339

1

T93

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T19

2

T59

1

T180

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T93

1

T380

1

T381

3

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded