Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1113

1

T12

9

T25

6

T172

6

auto[1]

1145

1

T12

11

T25

14

T172

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T12

6

T25

6

T172

5

from_0to1

551

1

T12

6

T25

6

T172

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T12

10

T25

9

T172

13

auto[1]

1180

1

T12

10

T25

11

T172

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T12

9

T25

11

T172

9

auto[1]

1115

1

T12

11

T25

9

T172

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T12

1

T25

1

T21

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T45

2

T394

1

T166

4

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T25

1

T16

3

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T16

1

T21

2

T395

2

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T12

3

T45

1

T147

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T25

1

T172

1

T16

3

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T16

3

T21

1

T395

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T12

2

T25

1

T172

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T12

2

T172

1

T16

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T12

1

T25

1

T172

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T12

1

T25

2

T172

2

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T12

1

T25

1

T172

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T25

1

T172

1

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

59

1

T25

1

T172

1

T16

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T25

1

T16

1

T21

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T12

1

T25

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T12

9

T25

10

T172

12

auto[1]

1096

1

T12

11

T25

10

T172

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

538

1

T12

5

T25

5

T172

4

from_0to1

527

1

T12

5

T25

5

T172

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T12

9

T25

7

T172

9

auto[1]

1093

1

T12

11

T25

13

T172

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1094

1

T12

13

T25

10

T172

10

auto[1]

1164

1

T12

7

T25

10

T172

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T12

1

T25

1

T16

2

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T25

1

T16

1

T147

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T12

1

T172

1

T21

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T16

1

T21

2

T176

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T12

1

T172

1

T16

2

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T25

1

T172

2

T21

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T25

1

T172

1

T16

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T172

1

T16

1

T21

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T16

4

T21

1

T396

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T172

2

T16

1

T21

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T12

1

T25

1

T172

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T12

2

T25

2

T395

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T12

2

T16

1

T21

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T25

1

T16

1

T21

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T12

2

T25

2

T16

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T16

2

T176

1

T395

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T12

8

T25

11

T172

9

auto[1]

1104

1

T12

12

T25

9

T172

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T12

5

T25

6

T172

4

from_0to1

559

1

T12

5

T25

5

T172

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T12

11

T25

10

T172

7

auto[1]

1151

1

T12

9

T25

10

T172

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T12

12

T25

6

T172

14

auto[1]

1118

1

T12

8

T25

14

T172

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T12

2

T25

3

T172

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T25

1

T172

1

T176

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T16

1

T176

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T16

3

T21

1

T395

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T16

1

T176

1

T395

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T25

2

T16

1

T147

1

auto[0]

from_0to1

auto[1]

auto[0]

80

1

T12

2

T16

2

T176

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T25

1

T16

2

T76

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T12

2

T172

1

T395

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T395

1

T45

1

T147

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T25

2

T16

2

T395

2

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T12

1

T172

1

T16

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T12

2

T147

1

T285

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T12

1

T25

1

T172

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T172

2

T21

1

T176

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T25

1

T16

1

T176

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1148

1

T12

6

T25

10

T172

8

auto[1]

1110

1

T12

14

T25

10

T172

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

549

1

T12

5

T25

5

T172

6

from_0to1

546

1

T12

6

T25

4

T172

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T12

5

T25

11

T172

11

auto[1]

1143

1

T12

15

T25

9

T172

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T12

5

T25

15

T172

8

auto[1]

1127

1

T12

15

T25

5

T172

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T25

1

T16

2

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T172

2

T16

2

T45

2

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T25

1

T172

1

T16

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T12

2

T25

1

T21

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T172

1

T21

1

T395

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T172

2

T16

2

T176

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T25

1

T172

1

T21

2

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T16

1

T395

2

T45

4

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T25

1

T172

1

T16

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T12

1

T25

1

T172

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T12

1

T16

1

T21

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T12

1

T172

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T25

2

T16

1

T21

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T12

3

T172

1

T21

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T12

1

T25

1

T172

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T12

2

T16

1

T21

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T12

8

T25

11

T172

13

auto[1]

1105

1

T12

12

T25

9

T172

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

565

1

T12

7

T25

4

T172

4

from_0to1

558

1

T12

7

T25

5

T172

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T12

10

T25

10

T172

15

auto[1]

1126

1

T12

10

T25

10

T172

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T12

9

T25

11

T172

12

auto[1]

1158

1

T12

11

T25

9

T172

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T25

2

T16

1

T21

1

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T12

1

T172

2

T16

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T12

2

T16

1

T176

2

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T12

1

T16

1

T52

2

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T12

1

T172

1

T16

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T25

2

T172

1

T16

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T12

1

T25

1

T172

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T12

1

T25

1

T172

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T12

1

T172

1

T16

2

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T12

2

T25

1

T172

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T25

1

T395

1

T45

3

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T16

2

T395

1

T45

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T12

1

T25

1

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T12

1

T16

2

T176

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T12

1

T16

2

T21

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T12

1

T16

2

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T12

11

T25

9

T172

10

auto[1]

1149

1

T12

9

T25

11

T172

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

537

1

T12

4

T25

3

T172

5

from_0to1

541

1

T12

5

T25

4

T172

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T12

12

T25

13

T172

9

auto[1]

1138

1

T12

8

T25

7

T172

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T12

10

T25

7

T172

7

auto[1]

1169

1

T12

10

T25

13

T172

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T172

1

T16

1

T52

1

auto[0]

from_1to0

auto[0]

auto[1]

77

1

T12

1

T16

1

T21

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T12

1

T25

1

T16

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T172

1

T395

2

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T12

1

T176

1

T45

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T16

1

T21

1

T176

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T172

1

T16

1

T21

1

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T25

2

T172

2

T16

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T25

1

T172

1

T16

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T12

2

T16

2

T176

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T25

1

T45

1

T52

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T172

2

T21

1

T176

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T12

1

T16

1

T176

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T12

1

T25

2

T172

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T12

2

T172

1

T395

1

auto[1]

from_0to1

auto[1]

auto[1]

77

1

T16

1

T21

2

T395

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T12

13

T25

9

T172

10

auto[1]

1086

1

T12

7

T25

11

T172

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

551

1

T12

5

T25

5

T172

5

from_0to1

539

1

T12

4

T25

4

T172

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T12

9

T25

14

T172

8

auto[1]

1146

1

T12

11

T25

6

T172

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1154

1

T12

8

T25

10

T172

10

auto[1]

1104

1

T12

12

T25

10

T172

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T16

1

T21

1

T395

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T12

2

T25

3

T16

2

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T12

1

T172

1

T16

1

auto[0]

from_1to0

auto[1]

auto[1]

82

1

T172

1

T21

2

T176

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T12

1

T25

1

T16

3

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T172

1

T21

1

T395

3

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T12

1

T25

1

T172

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T16

1

T176

1

T395

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T25

1

T16

3

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T25

1

T172

2

T176

1

auto[1]

from_1to0

auto[1]

auto[0]

93

1

T12

2

T16

1

T21

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T172

1

T16

1

T21

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T25

1

T172

1

T52

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T12

2

T25

1

T172

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T21

1

T176

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T172

1

T16

2

T176

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T12

5

T25

10

T172

9

auto[1]

1155

1

T12

15

T25

10

T172

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T12

5

T25

4

T172

3

from_0to1

546

1

T12

5

T25

4

T172

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T12

9

T25

7

T172

10

auto[1]

1126

1

T12

11

T25

13

T172

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T12

13

T25

13

T172

11

auto[1]

1142

1

T12

7

T25

7

T172

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T25

1

T45

2

T147

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T25

1

T395

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T12

1

T25

1

T172

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T176

2

T395

2

T45

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T12

1

T25

1

T172

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T16

2

T21

1

T176

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T25

2

T172

1

T16

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T176

3

T395

1

T45

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T12

1

T16

1

T21

1

auto[1]

from_1to0

auto[0]

auto[1]

81

1

T16

4

T21

1

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T12

1

T25

1

T16

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T12

2

T172

2

T16

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T12

1

T25

1

T147

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T12

2

T172

1

T16

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T16

2

T395

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T12

1

T16

2

T176

1