Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118290

1

T1

407

T2

19

T5

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139344	1			T1	193		T2	35		T5	51
values[0x0]	66341	1			T1	97		T2	15		T5	70
values[0x1]	67051	1			T1	117		T2	23		T5	100

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125457	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147279

1

T1

407

T2

33

T5

210

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1021	1			T4	5		T6	4		T8	8
valid_sources[0x01]	1823	1			T5	1		T4	2		T6	3
valid_sources[0x02]	885	1			T1	2		T2	1		T5	2
valid_sources[0x03]	1059	1			T5	1		T3	2		T4	5
valid_sources[0x04]	985	1			T1	4		T5	1		T3	2
valid_sources[0x05]	816	1			T5	1		T22	1		T4	7
valid_sources[0x06]	949	1			T3	3		T4	8		T6	13
valid_sources[0x07]	856	1			T1	8		T4	1		T6	10
valid_sources[0x08]	859	1			T1	1		T5	1		T3	1
valid_sources[0x09]	935	1			T5	2		T22	1		T3	2
valid_sources[0x0a]	966	1			T1	1		T4	1		T6	7
valid_sources[0x0b]	878	1			T1	1		T3	4		T4	4
valid_sources[0x0c]	782	1			T5	1		T3	4		T4	3
valid_sources[0x0d]	932	1			T1	2		T5	1		T3	3
valid_sources[0x0e]	868	1			T2	1		T3	2		T23	6
valid_sources[0x0f]	1834	1			T3	6		T4	6		T6	10
valid_sources[0x10]	1242	1			T4	12		T6	7		T7	4
valid_sources[0x11]	1004	1			T1	3		T3	2		T4	2
valid_sources[0x12]	1220	1			T1	5		T5	2		T3	1
valid_sources[0x13]	724	1			T5	1		T4	3		T6	7
valid_sources[0x14]	917	1			T3	4		T4	1		T6	5
valid_sources[0x15]	955	1			T4	3		T6	4		T7	3
valid_sources[0x16]	892	1			T1	12		T2	3		T3	10
valid_sources[0x17]	887	1			T1	1		T3	4		T4	3
valid_sources[0x18]	1218	1			T1	2		T3	2		T4	3
valid_sources[0x19]	874	1			T1	2		T3	6		T4	6
valid_sources[0x1a]	948	1			T1	6		T5	1		T22	1
valid_sources[0x1b]	921	1			T1	2		T3	7		T4	3
valid_sources[0x1c]	797	1			T1	1		T4	5		T6	4
valid_sources[0x1d]	869	1			T2	2		T3	1		T23	6
valid_sources[0x1e]	927	1			T3	2		T4	6		T6	8
valid_sources[0x1f]	853	1			T23	6		T4	3		T6	4
valid_sources[0x20]	873	1			T1	5		T3	9		T4	3
valid_sources[0x21]	783	1			T1	1		T3	3		T4	4
valid_sources[0x22]	1014	1			T1	1		T5	1		T3	4
valid_sources[0x23]	1001	1			T1	6		T3	7		T23	4
valid_sources[0x24]	868	1			T1	3		T5	1		T3	4
valid_sources[0x25]	803	1			T1	7		T3	3		T4	5
valid_sources[0x26]	1160	1			T1	1		T5	1		T3	1
valid_sources[0x27]	1900	1			T1	5		T3	3		T4	1
valid_sources[0x28]	772	1			T5	2		T3	2		T4	5
valid_sources[0x29]	976	1			T2	2		T5	1		T4	3
valid_sources[0x2a]	839	1			T1	5		T2	1		T5	2
valid_sources[0x2b]	858	1			T1	4		T5	2		T3	2
valid_sources[0x2c]	1098	1			T1	4		T2	1		T5	2
valid_sources[0x2d]	870	1			T1	7		T5	1		T3	5
valid_sources[0x2e]	877	1			T1	2		T4	2		T6	6
valid_sources[0x2f]	2005	1			T3	12		T4	3		T6	7
valid_sources[0x30]	806	1			T1	2		T4	3		T7	6
valid_sources[0x31]	871	1			T3	6		T23	1		T4	4
valid_sources[0x32]	901	1			T1	1		T3	8		T4	4
valid_sources[0x33]	924	1			T5	2		T3	3		T4	4
valid_sources[0x34]	2146	1			T5	2		T4	3		T6	8
valid_sources[0x35]	989	1			T5	2		T3	6		T4	4
valid_sources[0x36]	849	1			T5	2		T4	2		T6	5
valid_sources[0x37]	1123	1			T1	1		T2	1		T5	1
valid_sources[0x38]	794	1			T1	1		T5	2		T4	5
valid_sources[0x39]	1037	1			T1	1		T3	6		T4	3
valid_sources[0x3a]	909	1			T1	1		T5	3		T3	1
valid_sources[0x3b]	999	1			T2	2		T5	1		T3	2
valid_sources[0x3c]	1142	1			T2	2		T5	2		T4	3
valid_sources[0x3d]	867	1			T2	3		T3	1		T4	3
valid_sources[0x3e]	910	1			T1	3		T3	3		T4	3
valid_sources[0x3f]	1285	1			T5	1		T3	4		T6	12
valid_sources[0x40]	948	1			T1	5		T5	1		T3	5
valid_sources[0x41]	976	1			T1	3		T5	1		T22	2
valid_sources[0x42]	814	1			T1	3		T5	2		T3	1
valid_sources[0x43]	897	1			T1	1		T4	3		T6	5
valid_sources[0x44]	1021	1			T1	5		T5	2		T4	7
valid_sources[0x45]	955	1			T22	1		T3	4		T4	5
valid_sources[0x46]	835	1			T3	14		T4	7		T6	1
valid_sources[0x47]	1001	1			T5	2		T3	2		T4	6
valid_sources[0x48]	974	1			T5	1		T3	4		T4	3
valid_sources[0x49]	1267	1			T2	1		T5	1		T3	1
valid_sources[0x4a]	835	1			T1	1		T5	1		T22	1
valid_sources[0x4b]	886	1			T1	7		T5	3		T22	1
valid_sources[0x4c]	878	1			T1	1		T5	1		T4	2
valid_sources[0x4d]	965	1			T1	2		T3	3		T4	2
valid_sources[0x4e]	1024	1			T1	3		T5	1		T3	4
valid_sources[0x4f]	1325	1			T5	1		T3	3		T4	3
valid_sources[0x50]	1821	1			T4	4		T6	4		T7	1
valid_sources[0x51]	810	1			T3	4		T7	1		T8	14
valid_sources[0x52]	1041	1			T1	1		T5	2		T3	5
valid_sources[0x53]	1874	1			T4	2		T6	8		T7	1
valid_sources[0x54]	870	1			T3	6		T4	1		T6	2
valid_sources[0x55]	799	1			T3	6		T23	4		T4	7
valid_sources[0x56]	829	1			T5	2		T3	4		T4	5
valid_sources[0x57]	968	1			T1	3		T4	1		T6	6
valid_sources[0x58]	819	1			T5	2		T3	2		T4	3
valid_sources[0x59]	3388	1			T1	1		T5	3		T3	3
valid_sources[0x5a]	1689	1			T1	4		T2	1		T22	2
valid_sources[0x5b]	925	1			T1	1		T2	3		T5	1
valid_sources[0x5c]	1691	1			T2	2		T5	1		T3	1
valid_sources[0x5d]	1017	1			T1	1		T5	1		T22	1
valid_sources[0x5e]	855	1			T1	3		T5	2		T3	1
valid_sources[0x5f]	900	1			T2	1		T5	2		T3	4
valid_sources[0x60]	989	1			T1	6		T5	1		T3	9
valid_sources[0x61]	1003	1			T1	2		T3	7		T4	7
valid_sources[0x62]	1977	1			T3	3		T4	4		T6	16
valid_sources[0x63]	1048	1			T1	1		T2	1		T5	2
valid_sources[0x64]	1168	1			T1	1		T5	1		T3	9
valid_sources[0x65]	1089	1			T5	1		T3	3		T4	1
valid_sources[0x66]	1579	1			T5	1		T4	4		T6	5
valid_sources[0x67]	753	1			T1	1		T5	1		T3	6
valid_sources[0x68]	798	1			T4	7		T6	1		T7	5
valid_sources[0x69]	952	1			T1	4		T5	1		T22	1
valid_sources[0x6a]	1079	1			T1	3		T5	1		T22	1
valid_sources[0x6b]	974	1			T5	2		T22	1		T3	4
valid_sources[0x6c]	919	1			T1	4		T5	1		T3	3
valid_sources[0x6d]	1792	1			T1	4		T5	1		T3	1
valid_sources[0x6e]	2439	1			T5	1		T4	4		T6	12
valid_sources[0x6f]	838	1			T1	4		T3	6		T4	1
valid_sources[0x70]	885	1			T1	1		T5	1		T3	2
valid_sources[0x71]	916	1			T3	7		T4	3		T6	5
valid_sources[0x72]	764	1			T1	1		T5	2		T3	1
valid_sources[0x73]	828	1			T1	2		T3	5		T6	4
valid_sources[0x74]	898	1			T1	1		T5	1		T3	1
valid_sources[0x75]	972	1			T1	3		T22	1		T3	3
valid_sources[0x76]	753	1			T3	2		T4	4		T6	8
valid_sources[0x77]	1046	1			T1	1		T4	4		T7	2
valid_sources[0x78]	1552	1			T1	2		T2	1		T22	1
valid_sources[0x79]	1225	1			T1	1		T3	1		T23	4
valid_sources[0x7a]	909	1			T1	9		T5	1		T4	1
valid_sources[0x7b]	1019	1			T5	2		T3	15		T4	4
valid_sources[0x7c]	1207	1			T1	6		T5	1		T3	5
valid_sources[0x7d]	919	1			T1	2		T4	7		T6	8
valid_sources[0x7e]	970	1			T5	2		T3	3		T4	3
valid_sources[0x7f]	1329	1			T3	1		T4	4		T7	5
valid_sources[0x80]	1107	1			T1	8		T5	1		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63603

1

T1

193

T2

6

T5

47

values[0x0]

all_enables

biggest_size

32071

1

T1

97

T2

7

T5

68

values[0x1]

all_enables

biggest_size

22616

1

T1

117

T2

6

T5

79