Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T55,T18,T56
1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T57,T55,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T57,T55,T18

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T57,T55,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T55,T18,T56
1	0	Covered	T18,T38,T41
1	1	Covered	T57,T55,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T57,T55,T18
0	1	Covered	T55,T18,T56
1	0	Covered	T18,T41,T42

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T57,T38,T58
0	1	Covered	T38,T58,T60
1	0	Covered	T85,T90,T264

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T57,T38,T58
1	-	Covered	T38,T58,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T57,T55,T18
0	1	Covered	T57,T55,T18
0	0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T57,T55,T18
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T57,T55,T18
IdleSt	0	-	-	-	-	-	-	Covered	T55,T18,T56
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T57,T55,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T265,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T57,T55,T18
DetectSt	-	-	-	-	1	-	-	Covered	T55,T18,T56
DetectSt	-	-	-	-	0	1	-	Covered	T57,T38,T58
DetectSt	-	-	-	-	0	0	-	Covered	T57,T55,T18
StableSt	-	-	-	-	-	-	1	Covered	T38,T58,T60
StableSt	-	-	-	-	-	-	0	Covered	T57,T38,T58
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	3145	0	0
CntIncr_A	8819542	103261	0	0
CntNoWrap_A	8819542	8155697	0	0
DetectStDropOut_A	8819542	262	0	0
DetectedOut_A	8819542	82902	0	0
DetectedPulseOut_A	8819542	1079	0	0
DisabledIdleSt_A	8819542	7697276	0	0
DisabledNoDetection_A	8819542	7699362	0	0
EnterDebounceSt_A	8819542	1586	0	0
EnterDetectSt_A	8819542	1559	0	0
EnterStableSt_A	8819542	1079	0	0
PulseIsPulse_A	8819542	1079	0	0
StayInStableSt	8819542	81720	0	0
gen_high_event_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	958	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3145	0	0
T18	8858	40	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	12	0	0
T41	0	60	0	0
T42	0	36	0	0
T55	5266	56	0	0
T56	0	50	0	0
T57	450	2	0	0
T58	0	54	0	0
T60	0	18	0	0
T61	0	2	0	0
T69	486	0	0	0
T99	724	0	0	0
T117	426	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	103261	0	0
T18	8858	1071	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	300	0	0
T41	0	2295	0	0
T42	0	976	0	0
T55	5266	1481	0	0
T56	0	1301	0	0
T57	450	21	0	0
T58	0	1242	0	0
T60	0	414	0	0
T61	0	59	0	0
T69	486	0	0	0
T99	724	0	0	0
T117	426	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8155697	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	262	0	0
T18	8858	6	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	0	14	0	0
T42	0	6	0	0
T55	5266	28	0	0
T56	5216	25	0	0
T99	724	0	0	0
T105	0	8	0	0
T106	0	4	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0
T247	0	27	0	0
T266	0	14	0	0
T267	0	23	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	82902	0	0
T38	11375	821	0	0
T44	0	934	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T57	450	25	0	0
T58	0	1108	0	0
T60	0	231	0	0
T61	0	6	0	0
T69	486	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T181	0	91	0	0
T221	0	2713	0	0
T268	0	1578	0	0
T269	0	192	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1079	0	0
T38	11375	6	0	0
T44	0	15	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T57	450	1	0	0
T58	0	27	0	0
T60	0	9	0	0
T61	0	1	0	0
T69	486	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T181	0	1	0	0
T221	0	27	0	0
T268	0	26	0	0
T269	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7697276	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7699362	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1586	0	0
T18	8858	20	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	6	0	0
T41	0	30	0	0
T42	0	18	0	0
T55	5266	28	0	0
T56	0	25	0	0
T57	450	1	0	0
T58	0	27	0	0
T60	0	9	0	0
T61	0	1	0	0
T69	486	0	0	0
T99	724	0	0	0
T117	426	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1559	0	0
T18	8858	20	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	6	0	0
T41	0	30	0	0
T42	0	18	0	0
T55	5266	28	0	0
T56	0	25	0	0
T57	450	1	0	0
T58	0	27	0	0
T60	0	9	0	0
T61	0	1	0	0
T69	486	0	0	0
T99	724	0	0	0
T117	426	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1079	0	0
T38	11375	6	0	0
T44	0	15	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T57	450	1	0	0
T58	0	27	0	0
T60	0	9	0	0
T61	0	1	0	0
T69	486	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T181	0	1	0	0
T221	0	27	0	0
T268	0	26	0	0
T269	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1079	0	0
T38	11375	6	0	0
T44	0	15	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T57	450	1	0	0
T58	0	27	0	0
T60	0	9	0	0
T61	0	1	0	0
T69	486	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T181	0	1	0	0
T221	0	27	0	0
T268	0	26	0	0
T269	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	81720	0	0
T38	11375	815	0	0
T44	0	918	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T57	450	23	0	0
T58	0	1080	0	0
T60	0	221	0	0
T61	0	5	0	0
T69	486	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T181	0	89	0	0
T221	0	2686	0	0
T268	0	1552	0	0
T269	0	186	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	958	0	0
T38	11375	6	0	0
T44	0	14	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	26	0	0
T60	0	8	0	0
T61	0	1	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	27	0	0
T250	0	21	0	0
T268	0	26	0	0
T269	0	6	0	0
T270	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T12,T14,T57
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T57
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T12,T14,T57

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T12,T14,T57

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T14,T16,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T57
1	0	Covered	T12,T14,T15
1	1	Covered	T12,T14,T57

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T19
0	1	Covered	T19,T39,T93
1	0	Covered	T85,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T59
0	1	Covered	T14,T16,T59
1	0	Covered	T85,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T16,T59
1	-	Covered	T14,T16,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T14,T57
0	1	Covered	T12,T14,T57
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T19
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T14,T57
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T57,T15
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T14,T57
DetectSt	-	-	-	-	1	-	-	Covered	T19,T39,T93
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T59
DetectSt	-	-	-	-	0	0	-	Covered	T14,T16,T19
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T59
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	1000	0	0
CntIncr_A	8819542	52202	0	0
CntNoWrap_A	8819542	8157842	0	0
DetectStDropOut_A	8819542	78	0	0
DetectedOut_A	8819542	14956	0	0
DetectedPulseOut_A	8819542	381	0	0
DisabledIdleSt_A	8819542	7795826	0	0
DisabledNoDetection_A	8819542	7797427	0	0
EnterDebounceSt_A	8819542	540	0	0
EnterDetectSt_A	8819542	462	0	0
EnterStableSt_A	8819542	381	0	0
PulseIsPulse_A	8819542	381	0	0
StayInStableSt	8819542	14538	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1000	0	0
T12	185966	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	2	0	0
T19	0	14	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T38	0	4	0	0
T45	0	4	0	0
T57	0	1	0	0
T59	0	2	0	0
T66	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	52202	0	0
T12	185966	20	0	0
T14	0	84	0	0
T15	0	20	0	0
T16	0	25	0	0
T19	0	1698	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T38	0	144	0	0
T45	0	50	0	0
T57	0	20	0	0
T59	0	87	0	0
T66	0	276	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8157842	0	0
T12	185966	181123	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	78	0	0
T19	12606	7	0	0
T20	649	0	0	0
T39	15581	9	0	0
T40	29528	0	0	0
T56	5216	0	0	0
T85	0	1	0	0
T93	45283	1	0	0
T107	25318	4	0	0
T108	0	5	0	0
T110	0	2	0	0
T112	0	7	0	0
T113	0	3	0	0
T115	0	2	0	0
T117	426	0	0	0
T118	527	0	0	0
T119	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14956	0	0
T14	16320	55	0	0
T16	10070	3	0	0
T17	2061	0	0	0
T38	0	151	0	0
T40	0	240	0	0
T45	0	6	0	0
T57	450	0	0	0
T58	0	47	0	0
T59	0	30	0	0
T66	0	26	0	0
T67	0	8	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T128	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	381	0	0
T14	16320	1	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T38	0	2	0	0
T40	0	12	0	0
T45	0	2	0	0
T57	450	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T128	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7795826	0	0
T12	185966	181085	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7797427	0	0
T12	185966	181098	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	540	0	0
T12	185966	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	0	7	0	0
T25	502	0	0	0
T26	701	0	0	0
T27	522	0	0	0
T28	999	0	0	0
T29	449	0	0	0
T30	452	0	0	0
T31	521	0	0	0
T32	630	0	0	0
T33	739	0	0	0
T38	0	2	0	0
T45	0	2	0	0
T57	0	1	0	0
T59	0	1	0	0
T66	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	462	0	0
T14	16320	1	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T19	0	7	0	0
T38	0	2	0	0
T39	0	9	0	0
T40	0	12	0	0
T45	0	2	0	0
T57	450	0	0	0
T59	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	381	0	0
T14	16320	1	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T38	0	2	0	0
T40	0	12	0	0
T45	0	2	0	0
T57	450	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T128	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	381	0	0
T14	16320	1	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T38	0	2	0	0
T40	0	12	0	0
T45	0	2	0	0
T57	450	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T128	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14538	0	0
T14	16320	54	0	0
T16	10070	2	0	0
T17	2061	0	0	0
T38	0	149	0	0
T40	0	228	0	0
T45	0	4	0	0
T57	450	0	0	0
T58	0	45	0	0
T59	0	29	0	0
T66	0	24	0	0
T67	0	6	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T128	0	56	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	341	0	0
T14	16320	1	0	0
T16	10070	1	0	0
T17	2061	0	0	0
T38	0	2	0	0
T40	0	12	0	0
T45	0	2	0	0
T46	0	1	0	0
T57	450	0	0	0
T59	0	1	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	522	0	0	0
T69	486	0	0	0
T70	662	0	0	0
T71	696	0	0	0
T72	416	0	0	0
T73	794	0	0	0
T128	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T55,T18,T56
1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T55,T18,T56
1	0	Covered	T18,T38,T41
1	1	Covered	T55,T18,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T55,T18,T56
0	1	Covered	T55,T56,T38
1	0	Covered	T38,T42,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T41,T58
0	1	Covered	T18,T41,T58
1	0	Covered	T89,T85,T123

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T41,T58
1	-	Covered	T18,T41,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T55,T18,T56
0	1	Covered	T55,T18,T56
0	0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T55,T18,T56
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T55,T18,T56
IdleSt	0	-	-	-	-	-	-	Covered	T55,T18,T56
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T55,T18,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T265,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T55,T18,T56
DetectSt	-	-	-	-	1	-	-	Covered	T55,T56,T38
DetectSt	-	-	-	-	0	1	-	Covered	T18,T41,T58
DetectSt	-	-	-	-	0	0	-	Covered	T55,T18,T56
StableSt	-	-	-	-	-	-	1	Covered	T18,T41,T58
StableSt	-	-	-	-	-	-	0	Covered	T18,T41,T58
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	3365	0	0
CntIncr_A	8819542	113739	0	0
CntNoWrap_A	8819542	8155477	0	0
DetectStDropOut_A	8819542	293	0	0
DetectedOut_A	8819542	83275	0	0
DetectedPulseOut_A	8819542	1109	0	0
DisabledIdleSt_A	8819542	7698059	0	0
DisabledNoDetection_A	8819542	7700145	0	0
EnterDebounceSt_A	8819542	1697	0	0
EnterDetectSt_A	8819542	1668	0	0
EnterStableSt_A	8819542	1109	0	0
PulseIsPulse_A	8819542	1109	0	0
StayInStableSt	8819542	82061	0	0
gen_high_event_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	978	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3365	0	0
T18	8858	52	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	52	0	0
T41	0	12	0	0
T42	0	20	0	0
T55	5266	14	0	0
T56	5216	50	0	0
T58	0	20	0	0
T60	0	22	0	0
T61	0	26	0	0
T99	724	0	0	0
T105	0	50	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	113739	0	0
T18	8858	1326	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	1462	0	0
T41	0	348	0	0
T42	0	544	0	0
T55	5266	364	0	0
T56	5216	1306	0	0
T58	0	490	0	0
T60	0	528	0	0
T61	0	481	0	0
T99	724	0	0	0
T105	0	1525	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8155477	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	293	0	0
T18	8858	0	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	15	0	0
T42	0	3	0	0
T55	5266	7	0	0
T56	5216	25	0	0
T99	724	0	0	0
T106	0	9	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0
T247	0	8	0	0
T266	0	18	0	0
T267	0	23	0	0
T268	0	9	0	0
T271	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	83275	0	0
T18	8858	1590	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	19055	447	0	0
T56	5216	0	0	0
T58	0	204	0	0
T60	0	243	0	0
T61	0	373	0	0
T99	724	0	0	0
T105	0	2354	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	2325	0	0
T228	688	0	0	0
T269	0	933	0	0
T270	0	4034	0	0
T272	0	1414	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1109	0	0
T18	8858	26	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	19055	6	0	0
T56	5216	0	0	0
T58	0	10	0	0
T60	0	11	0	0
T61	0	13	0	0
T99	724	0	0	0
T105	0	25	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T269	0	13	0	0
T270	0	33	0	0
T272	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7698059	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7700145	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1697	0	0
T18	8858	26	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	26	0	0
T41	0	6	0	0
T42	0	10	0	0
T55	5266	7	0	0
T56	5216	25	0	0
T58	0	10	0	0
T60	0	11	0	0
T61	0	13	0	0
T99	724	0	0	0
T105	0	25	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1668	0	0
T18	8858	26	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	26	0	0
T41	0	6	0	0
T42	0	10	0	0
T55	5266	7	0	0
T56	5216	25	0	0
T58	0	10	0	0
T60	0	11	0	0
T61	0	13	0	0
T99	724	0	0	0
T105	0	25	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1109	0	0
T18	8858	26	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	19055	6	0	0
T56	5216	0	0	0
T58	0	10	0	0
T60	0	11	0	0
T61	0	13	0	0
T99	724	0	0	0
T105	0	25	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T269	0	13	0	0
T270	0	33	0	0
T272	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1109	0	0
T18	8858	26	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	19055	6	0	0
T56	5216	0	0	0
T58	0	10	0	0
T60	0	11	0	0
T61	0	13	0	0
T99	724	0	0	0
T105	0	25	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T269	0	13	0	0
T270	0	33	0	0
T272	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	82061	0	0
T18	8858	1563	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	19055	440	0	0
T56	5216	0	0	0
T58	0	193	0	0
T60	0	231	0	0
T61	0	360	0	0
T99	724	0	0	0
T105	0	2325	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	2298	0	0
T228	688	0	0	0
T269	0	917	0	0
T270	0	3996	0	0
T272	0	1398	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	978	0	0
T18	8858	25	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	19055	5	0	0
T56	5216	0	0	0
T58	0	9	0	0
T60	0	10	0	0
T61	0	13	0	0
T99	724	0	0	0
T105	0	21	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T269	0	10	0	0
T270	0	28	0	0
T272	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T55,T18
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T55,T18
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T18,T19,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T18,T19,T59

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T18,T19,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T19
1	0	Covered	T12,T14,T15
1	1	Covered	T18,T19,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T59
0	1	Covered	T67,T180,T122
1	0	Covered	T85,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T59
0	1	Covered	T18,T19,T59
1	0	Covered	T85,T86

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T19,T59
1	-	Covered	T18,T19,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T19,T59
0	1	Covered	T18,T19,T59
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T59
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T19,T59
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T19,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T39,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T19,T59
DetectSt	-	-	-	-	1	-	-	Covered	T67,T180,T85
DetectSt	-	-	-	-	0	1	-	Covered	T18,T19,T59
DetectSt	-	-	-	-	0	0	-	Covered	T18,T19,T59
StableSt	-	-	-	-	-	-	1	Covered	T18,T19,T59
StableSt	-	-	-	-	-	-	0	Covered	T18,T19,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	731	0	0
CntIncr_A	8819542	36809	0	0
CntNoWrap_A	8819542	8158111	0	0
DetectStDropOut_A	8819542	37	0	0
DetectedOut_A	8819542	14588	0	0
DetectedPulseOut_A	8819542	296	0	0
DisabledIdleSt_A	8819542	7810135	0	0
DisabledNoDetection_A	8819542	7811826	0	0
EnterDebounceSt_A	8819542	394	0	0
EnterDetectSt_A	8819542	337	0	0
EnterStableSt_A	8819542	296	0	0
PulseIsPulse_A	8819542	296	0	0
StayInStableSt	8819542	14257	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	259	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	731	0	0
T18	8858	2	0	0
T19	12606	4	0	0
T20	649	0	0	0
T39	0	3	0	0
T40	0	5	0	0
T41	0	2	0	0
T56	5216	0	0	0
T59	31937	26	0	0
T66	0	2	0	0
T67	0	17	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	5	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	36809	0	0
T18	8858	61	0	0
T19	12606	446	0	0
T20	649	0	0	0
T39	0	138	0	0
T40	0	181	0	0
T41	0	61	0	0
T56	5216	0	0	0
T59	31937	1014	0	0
T66	0	122	0	0
T67	0	803	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	362	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	148	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158111	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	37	0	0
T39	15581	0	0	0
T40	29528	0	0	0
T67	11520	8	0	0
T112	0	2	0	0
T122	0	1	0	0
T150	496	0	0	0
T178	12353	0	0	0
T180	16640	4	0	0
T181	516	0	0	0
T182	1415	0	0	0
T183	433	0	0	0
T274	0	1	0	0
T275	0	1	0	0
T276	0	5	0	0
T277	0	3	0	0
T278	0	12	0	0
T279	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14588	0	0
T18	8858	68	0	0
T19	12606	39	0	0
T20	649	0	0	0
T39	0	19	0	0
T40	0	12	0	0
T41	0	97	0	0
T56	5216	0	0	0
T59	31937	510	0	0
T66	0	7	0	0
T76	0	8	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	118	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	52	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	296	0	0
T18	8858	1	0	0
T19	12606	2	0	0
T20	649	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T56	5216	0	0	0
T59	31937	13	0	0
T66	0	1	0	0
T76	0	1	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	2	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7810135	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7811826	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	394	0	0
T18	8858	1	0	0
T19	12606	2	0	0
T20	649	0	0	0
T39	0	2	0	0
T40	0	3	0	0
T41	0	1	0	0
T56	5216	0	0	0
T59	31937	13	0	0
T66	0	1	0	0
T67	0	9	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	337	0	0
T18	8858	1	0	0
T19	12606	2	0	0
T20	649	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T56	5216	0	0	0
T59	31937	13	0	0
T66	0	1	0	0
T67	0	8	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	2	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	296	0	0
T18	8858	1	0	0
T19	12606	2	0	0
T20	649	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T56	5216	0	0	0
T59	31937	13	0	0
T66	0	1	0	0
T76	0	1	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	2	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	296	0	0
T18	8858	1	0	0
T19	12606	2	0	0
T20	649	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T56	5216	0	0	0
T59	31937	13	0	0
T66	0	1	0	0
T76	0	1	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	2	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14257	0	0
T18	8858	67	0	0
T19	12606	37	0	0
T20	649	0	0	0
T39	0	18	0	0
T40	0	10	0	0
T41	0	96	0	0
T56	5216	0	0	0
T59	31937	497	0	0
T66	0	6	0	0
T76	0	7	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	116	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	259	0	0
T18	8858	1	0	0
T19	12606	2	0	0
T20	649	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T56	5216	0	0	0
T59	31937	13	0	0
T66	0	1	0	0
T76	0	1	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	2	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T55,T18,T56
1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T55,T18,T56
1	0	Covered	T18,T38,T41
1	1	Covered	T55,T18,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T55,T18,T56
0	1	Covered	T55,T18,T56
1	0	Covered	T18,T42,T105

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T41,T58
0	1	Covered	T38,T41,T58
1	0	Covered	T85,T280

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T41,T58
1	-	Covered	T38,T41,T58

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T55,T18,T56
0	1	Covered	T55,T18,T56
0	0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T55,T18,T56
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T55,T18,T56
IdleSt	0	-	-	-	-	-	-	Covered	T55,T18,T56
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T55,T18,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T265,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T55,T18,T56
DetectSt	-	-	-	-	1	-	-	Covered	T55,T18,T56
DetectSt	-	-	-	-	0	1	-	Covered	T38,T41,T58
DetectSt	-	-	-	-	0	0	-	Covered	T55,T18,T56
StableSt	-	-	-	-	-	-	1	Covered	T38,T41,T58
StableSt	-	-	-	-	-	-	0	Covered	T38,T41,T58
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	3004	0	0
CntIncr_A	8819542	98817	0	0
CntNoWrap_A	8819542	8155838	0	0
DetectStDropOut_A	8819542	235	0	0
DetectedOut_A	8819542	87783	0	0
DetectedPulseOut_A	8819542	1093	0	0
DisabledIdleSt_A	8819542	7689366	0	0
DisabledNoDetection_A	8819542	7691451	0	0
EnterDebounceSt_A	8819542	1515	0	0
EnterDetectSt_A	8819542	1489	0	0
EnterStableSt_A	8819542	1093	0	0
PulseIsPulse_A	8819542	1093	0	0
StayInStableSt	8819542	86585	0	0
gen_high_event_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	985	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3004	0	0
T18	8858	20	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	32	0	0
T41	0	54	0	0
T42	0	30	0	0
T55	5266	24	0	0
T56	5216	50	0	0
T58	0	54	0	0
T60	0	44	0	0
T61	0	52	0	0
T99	724	0	0	0
T105	0	40	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	98817	0	0
T18	8858	531	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	864	0	0
T41	0	1890	0	0
T42	0	813	0	0
T55	5266	626	0	0
T56	5216	1306	0	0
T58	0	891	0	0
T60	0	990	0	0
T61	0	1560	0	0
T99	724	0	0	0
T105	0	1366	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8155838	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	235	0	0
T18	8858	4	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	7	0	0
T55	5266	12	0	0
T56	5216	25	0	0
T99	724	0	0	0
T105	0	12	0	0
T106	0	9	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0
T247	0	21	0	0
T267	0	13	0	0
T268	0	3	0	0
T271	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	87783	0	0
T38	11375	1144	0	0
T41	0	2672	0	0
T44	0	3230	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	1459	0	0
T60	0	1516	0	0
T61	0	3467	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	1353	0	0
T266	0	1697	0	0
T269	0	268	0	0
T281	0	1489	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1093	0	0
T38	11375	16	0	0
T41	0	27	0	0
T44	0	21	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	27	0	0
T60	0	22	0	0
T61	0	26	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	15	0	0
T266	0	13	0	0
T269	0	13	0	0
T281	0	21	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7689366	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7691451	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1515	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	16	0	0
T41	0	27	0	0
T42	0	15	0	0
T55	5266	12	0	0
T56	5216	25	0	0
T58	0	27	0	0
T60	0	22	0	0
T61	0	26	0	0
T99	724	0	0	0
T105	0	20	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1489	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	16	0	0
T41	0	27	0	0
T42	0	15	0	0
T55	5266	12	0	0
T56	5216	25	0	0
T58	0	27	0	0
T60	0	22	0	0
T61	0	26	0	0
T99	724	0	0	0
T105	0	20	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1093	0	0
T38	11375	16	0	0
T41	0	27	0	0
T44	0	21	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	27	0	0
T60	0	22	0	0
T61	0	26	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	15	0	0
T266	0	13	0	0
T269	0	13	0	0
T281	0	21	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1093	0	0
T38	11375	16	0	0
T41	0	27	0	0
T44	0	21	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	27	0	0
T60	0	22	0	0
T61	0	26	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	15	0	0
T266	0	13	0	0
T269	0	13	0	0
T281	0	21	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	86585	0	0
T38	11375	1126	0	0
T41	0	2640	0	0
T44	0	3206	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	1431	0	0
T60	0	1493	0	0
T61	0	3438	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	1338	0	0
T266	0	1684	0	0
T269	0	253	0	0
T281	0	1468	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	985	0	0
T38	11375	14	0	0
T41	0	22	0	0
T44	0	18	0	0
T49	2512	0	0	0
T51	704	0	0	0
T53	882	0	0	0
T54	821	0	0	0
T58	0	26	0	0
T60	0	21	0	0
T61	0	23	0	0
T65	607	0	0	0
T129	424	0	0	0
T130	493	0	0	0
T175	426	0	0	0
T176	506	0	0	0
T221	0	15	0	0
T266	0	13	0	0
T269	0	11	0	0
T281	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T55,T18
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T55,T18
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T14,T19,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T14,T19,T59

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T14,T19,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T59
1	0	Covered	T12,T14,T15
1	1	Covered	T14,T19,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T59
0	1	Covered	T66,T273,T158
1	0	Covered	T85,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T59
0	1	Covered	T14,T19,T59
1	0	Covered	T85,T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T19,T59
1	-	Covered	T14,T19,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T19,T59
0	1	Covered	T14,T19,T59
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T19,T59
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T19,T59
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T19,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T38,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T19,T59
DetectSt	-	-	-	-	1	-	-	Covered	T66,T273,T158
DetectSt	-	-	-	-	0	1	-	Covered	T14,T19,T59
DetectSt	-	-	-	-	0	0	-	Covered	T14,T19,T59
StableSt	-	-	-	-	-	-	1	Covered	T14,T19,T59
StableSt	-	-	-	-	-	-	0	Covered	T14,T19,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	808	0	0
CntIncr_A	8819542	40763	0	0
CntNoWrap_A	8819542	8158034	0	0
DetectStDropOut_A	8819542	68	0	0
DetectedOut_A	8819542	14924	0	0
DetectedPulseOut_A	8819542	310	0	0
DisabledIdleSt_A	8819542	7800337	0	0
DisabledNoDetection_A	8819542	7802001	0	0
EnterDebounceSt_A	8819542	426	0	0
EnterDetectSt_A	8819542	382	0	0
EnterStableSt_A	8819542	310	0	0
PulseIsPulse_A	8819542	310	0	0
StayInStableSt	8819542	14577	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	269	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	808	0	0
T14	16320	16	0	0
T19	12606	5	0	0
T20	649	0	0	0
T38	0	5	0	0
T39	0	2	0	0
T40	0	5	0	0
T41	0	10	0	0
T56	5216	0	0	0
T57	450	0	0	0
T59	31937	2	0	0
T66	0	8	0	0
T67	0	2	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	40763	0	0
T14	16320	848	0	0
T19	12606	680	0	0
T20	649	0	0	0
T38	0	183	0	0
T39	0	76	0	0
T40	0	121	0	0
T41	0	520	0	0
T56	5216	0	0	0
T57	450	0	0	0
T59	31937	102	0	0
T66	0	518	0	0
T67	0	69	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	537	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158034	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	68	0	0
T39	15581	0	0	0
T40	29528	0	0	0
T52	106721	0	0	0
T66	7406	4	0	0
T67	11520	0	0	0
T108	0	9	0	0
T110	0	6	0	0
T112	0	2	0	0
T149	2200	0	0	0
T150	496	0	0	0
T158	0	11	0	0
T170	0	2	0	0
T273	17874	12	0	0
T279	422	0	0	0
T282	0	2	0	0
T283	0	2	0	0
T284	0	5	0	0
T285	507	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14924	0	0
T14	16320	274	0	0
T19	12606	16	0	0
T20	649	0	0	0
T38	0	145	0	0
T39	0	17	0	0
T40	0	72	0	0
T41	0	263	0	0
T56	5216	0	0	0
T57	450	0	0	0
T58	0	86	0	0
T59	31937	14	0	0
T67	0	26	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	53	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	310	0	0
T14	16320	8	0	0
T19	12606	2	0	0
T20	649	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T56	5216	0	0	0
T57	450	0	0	0
T58	0	2	0	0
T59	31937	1	0	0
T67	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7800337	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7802001	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	426	0	0
T14	16320	8	0	0
T19	12606	3	0	0
T20	649	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	3	0	0
T41	0	5	0	0
T56	5216	0	0	0
T57	450	0	0	0
T59	31937	1	0	0
T66	0	4	0	0
T67	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	382	0	0
T14	16320	8	0	0
T19	12606	2	0	0
T20	649	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T56	5216	0	0	0
T57	450	0	0	0
T59	31937	1	0	0
T66	0	4	0	0
T67	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	310	0	0
T14	16320	8	0	0
T19	12606	2	0	0
T20	649	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T56	5216	0	0	0
T57	450	0	0	0
T58	0	2	0	0
T59	31937	1	0	0
T67	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	310	0	0
T14	16320	8	0	0
T19	12606	2	0	0
T20	649	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T56	5216	0	0	0
T57	450	0	0	0
T58	0	2	0	0
T59	31937	1	0	0
T67	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	14577	0	0
T14	16320	266	0	0
T19	12606	14	0	0
T20	649	0	0	0
T38	0	143	0	0
T39	0	16	0	0
T40	0	70	0	0
T41	0	258	0	0
T56	5216	0	0	0
T57	450	0	0	0
T58	0	84	0	0
T59	31937	13	0	0
T67	0	25	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	50	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	269	0	0
T14	16320	8	0	0
T19	12606	2	0	0
T20	649	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	5	0	0
T56	5216	0	0	0
T57	450	0	0	0
T58	0	2	0	0
T59	31937	1	0	0
T67	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T128	0	3	0	0