Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T55,T18,T56
1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T55,T18,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T55,T18,T56
1	0	Covered	T18,T38,T41
1	1	Covered	T55,T18,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T55,T18,T56
0	1	Covered	T55,T56,T41
1	0	Covered	T38,T41,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T60,T61
0	1	Covered	T18,T60,T61
1	0	Covered	T85,T286

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T60,T61
1	-	Covered	T18,T60,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T55,T18,T56
0	1	Covered	T55,T18,T56
0	0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T55,T18,T56
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T55,T18,T56
IdleSt	0	-	-	-	-	-	-	Covered	T55,T18,T56
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T55,T18,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T85,T265,T86
DebounceSt	-	0	0	-	-	-	-	Covered	T55,T18,T56
DetectSt	-	-	-	-	1	-	-	Covered	T55,T56,T38
DetectSt	-	-	-	-	0	1	-	Covered	T18,T60,T61
DetectSt	-	-	-	-	0	0	-	Covered	T55,T18,T56
StableSt	-	-	-	-	-	-	1	Covered	T18,T60,T61
StableSt	-	-	-	-	-	-	0	Covered	T18,T60,T61
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	3107	0	0
CntIncr_A	8819542	105489	0	0
CntNoWrap_A	8819542	8155735	0	0
DetectStDropOut_A	8819542	279	0	0
DetectedOut_A	8819542	78910	0	0
DetectedPulseOut_A	8819542	985	0	0
DisabledIdleSt_A	8819542	7700873	0	0
DisabledNoDetection_A	8819542	7702963	0	0
EnterDebounceSt_A	8819542	1568	0	0
EnterDetectSt_A	8819542	1539	0	0
EnterStableSt_A	8819542	985	0	0
PulseIsPulse_A	8819542	985	0	0
StayInStableSt	8819542	77826	0	0
gen_high_event_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	883	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	3107	0	0
T18	8858	20	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	12	0	0
T41	0	38	0	0
T42	0	34	0	0
T55	5266	8	0	0
T56	5216	14	0	0
T58	0	54	0	0
T60	0	22	0	0
T61	0	24	0	0
T99	724	0	0	0
T105	0	34	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	105489	0	0
T18	8858	500	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	339	0	0
T41	0	1444	0	0
T42	0	782	0	0
T55	5266	208	0	0
T56	5216	358	0	0
T58	0	1399	0	0
T60	0	462	0	0
T61	0	384	0	0
T99	724	0	0	0
T105	0	1154	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8155735	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	279	0	0
T18	8858	0	0	0
T19	12606	0	0	0
T20	649	0	0	0
T41	0	10	0	0
T55	5266	4	0	0
T56	5216	7	0	0
T58	0	9	0	0
T99	724	0	0	0
T105	0	9	0	0
T106	0	13	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0
T247	0	21	0	0
T250	0	5	0	0
T266	0	14	0	0
T267	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	78910	0	0
T18	8858	978	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	1920	0	0
T44	0	780	0	0
T56	5216	0	0	0
T60	10958	305	0	0
T61	0	400	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	2433	0	0
T228	688	0	0	0
T268	0	313	0	0
T269	0	897	0	0
T270	0	1135	0	0
T287	0	1641	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	985	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	17	0	0
T44	0	7	0	0
T56	5216	0	0	0
T60	10958	11	0	0
T61	0	12	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T268	0	6	0	0
T269	0	10	0	0
T270	0	11	0	0
T287	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7700873	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7702963	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1568	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	6	0	0
T41	0	19	0	0
T42	0	17	0	0
T55	5266	4	0	0
T56	5216	7	0	0
T58	0	27	0	0
T60	0	11	0	0
T61	0	12	0	0
T99	724	0	0	0
T105	0	17	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	1539	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T38	0	6	0	0
T41	0	19	0	0
T42	0	17	0	0
T55	5266	4	0	0
T56	5216	7	0	0
T58	0	27	0	0
T60	0	11	0	0
T61	0	12	0	0
T99	724	0	0	0
T105	0	17	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T228	688	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	985	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	17	0	0
T44	0	7	0	0
T56	5216	0	0	0
T60	10958	11	0	0
T61	0	12	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T268	0	6	0	0
T269	0	10	0	0
T270	0	11	0	0
T287	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	985	0	0
T18	8858	10	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	17	0	0
T44	0	7	0	0
T56	5216	0	0	0
T60	10958	11	0	0
T61	0	12	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T268	0	6	0	0
T269	0	10	0	0
T270	0	11	0	0
T287	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	77826	0	0
T18	8858	967	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	1899	0	0
T44	0	772	0	0
T56	5216	0	0	0
T60	10958	293	0	0
T61	0	388	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	2406	0	0
T228	688	0	0	0
T268	0	307	0	0
T269	0	886	0	0
T270	0	1123	0	0
T287	0	1613	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	883	0	0
T18	8858	9	0	0
T19	12606	0	0	0
T20	649	0	0	0
T42	0	13	0	0
T44	0	6	0	0
T56	5216	0	0	0
T60	10958	10	0	0
T61	0	12	0	0
T99	724	0	0	0
T117	426	0	0	0
T118	527	0	0	0
T131	403	0	0	0
T221	0	27	0	0
T228	688	0	0	0
T268	0	6	0	0
T269	0	9	0	0
T270	0	10	0	0
T287	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T55,T18
1	Covered	T36,T12,T25

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T55,T18
1	0	Covered	T36,T12,T25
1	1	Covered	T36,T12,T25

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T14,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T36,T12,T25	VC_COV_UNR
1	Covered	T14,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T36,T12,T25
1	Covered	T14,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T18,T19
1	0	Covered	T12,T14,T15
1	1	Covered	T14,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T19
0	1	Covered	T19,T66,T40
1	0	Covered	T85,T86

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T18,T59
0	1	Covered	T14,T59,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T18,T59
1	-	Covered	T14,T59,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T18,T19
0	1	Covered	T14,T18,T19
0	0	Excluded	T36,T12,T25	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T18,T19
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T36,T12,T25
DebounceSt	-	1	-	-	-	-	-	Covered	T85,T86
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T40,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T19,T66,T40
DetectSt	-	-	-	-	0	1	-	Covered	T14,T18,T59
DetectSt	-	-	-	-	0	0	-	Covered	T14,T18,T19
StableSt	-	-	-	-	-	-	1	Covered	T14,T59,T39
StableSt	-	-	-	-	-	-	0	Covered	T14,T18,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T36,T12,T25
0	Covered	T36,T12,T25

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8819542	716	0	0
CntIncr_A	8819542	39303	0	0
CntNoWrap_A	8819542	8158126	0	0
DetectStDropOut_A	8819542	56	0	0
DetectedOut_A	8819542	12967	0	0
DetectedPulseOut_A	8819542	269	0	0
DisabledIdleSt_A	8819542	7812044	0	0
DisabledNoDetection_A	8819542	7813717	0	0
EnterDebounceSt_A	8819542	388	0	0
EnterDetectSt_A	8819542	329	0	0
EnterStableSt_A	8819542	269	0	0
PulseIsPulse_A	8819542	269	0	0
StayInStableSt	8819542	12654	0	0
gen_high_level_sva.HighLevelEvent_A	8819542	8161124	0	0
gen_not_sticky_sva.StableStDropOut_A	8819542	224	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	716	0	0
T14	16320	10	0	0
T18	8858	2	0	0
T19	12606	10	0	0
T20	649	0	0	0
T39	0	8	0	0
T40	0	21	0	0
T57	450	0	0	0
T59	0	2	0	0
T60	0	2	0	0
T66	0	6	0	0
T68	522	0	0	0
T69	486	0	0	0
T99	724	0	0	0
T128	0	6	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	39303	0	0
T14	16320	380	0	0
T18	8858	73	0	0
T19	12606	1396	0	0
T20	649	0	0	0
T39	0	352	0	0
T40	0	845	0	0
T57	450	0	0	0
T59	0	66	0	0
T60	0	54	0	0
T66	0	388	0	0
T68	522	0	0	0
T69	486	0	0	0
T99	724	0	0	0
T128	0	489	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	305	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8158126	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	56	0	0
T19	12606	4	0	0
T20	649	0	0	0
T40	0	9	0	0
T52	106721	0	0	0
T56	5216	0	0	0
T66	7406	3	0	0
T67	11520	0	0	0
T93	0	7	0	0
T109	0	1	0	0
T110	0	10	0	0
T117	426	0	0	0
T118	527	0	0	0
T140	0	1	0	0
T149	2200	0	0	0
T150	496	0	0	0
T186	0	4	0	0
T273	0	6	0	0
T288	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	12967	0	0
T14	16320	317	0	0
T18	8858	56	0	0
T19	12606	0	0	0
T20	649	0	0	0
T39	0	20	0	0
T42	0	271	0	0
T43	0	37	0	0
T44	0	95	0	0
T57	450	0	0	0
T59	0	51	0	0
T60	0	48	0	0
T68	522	0	0	0
T69	486	0	0	0
T81	0	304	0	0
T99	724	0	0	0
T128	0	101	0	0
T131	403	0	0	0
T228	688	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	269	0	0
T14	16320	5	0	0
T18	8858	1	0	0
T19	12606	0	0	0
T20	649	0	0	0
T39	0	4	0	0
T42	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T57	450	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T81	0	10	0	0
T99	724	0	0	0
T128	0	3	0	0
T131	403	0	0	0
T228	688	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7812044	0	0
T12	185966	181124	0	0
T25	502	101	0	0
T26	701	300	0	0
T27	522	121	0	0
T28	999	598	0	0
T29	449	48	0	0
T30	452	51	0	0
T31	521	120	0	0
T32	630	229	0	0
T36	402	1	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	7813717	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	388	0	0
T14	16320	5	0	0
T18	8858	1	0	0
T19	12606	6	0	0
T20	649	0	0	0
T39	0	4	0	0
T40	0	12	0	0
T57	450	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T66	0	3	0	0
T68	522	0	0	0
T69	486	0	0	0
T99	724	0	0	0
T128	0	3	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	329	0	0
T14	16320	5	0	0
T18	8858	1	0	0
T19	12606	4	0	0
T20	649	0	0	0
T39	0	4	0	0
T40	0	9	0	0
T57	450	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T66	0	3	0	0
T68	522	0	0	0
T69	486	0	0	0
T99	724	0	0	0
T128	0	3	0	0
T131	403	0	0	0
T228	688	0	0	0
T273	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	269	0	0
T14	16320	5	0	0
T18	8858	1	0	0
T19	12606	0	0	0
T20	649	0	0	0
T39	0	4	0	0
T42	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T57	450	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T81	0	10	0	0
T99	724	0	0	0
T128	0	3	0	0
T131	403	0	0	0
T228	688	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	269	0	0
T14	16320	5	0	0
T18	8858	1	0	0
T19	12606	0	0	0
T20	649	0	0	0
T39	0	4	0	0
T42	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T57	450	0	0	0
T59	0	1	0	0
T60	0	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T81	0	10	0	0
T99	724	0	0	0
T128	0	3	0	0
T131	403	0	0	0
T228	688	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	12654	0	0
T14	16320	312	0	0
T18	8858	54	0	0
T19	12606	0	0	0
T20	649	0	0	0
T39	0	16	0	0
T42	0	267	0	0
T43	0	36	0	0
T44	0	94	0	0
T57	450	0	0	0
T59	0	50	0	0
T60	0	46	0	0
T68	522	0	0	0
T69	486	0	0	0
T81	0	294	0	0
T99	724	0	0	0
T128	0	98	0	0
T131	403	0	0	0
T228	688	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	8161124	0	0
T12	185966	181138	0	0
T25	502	102	0	0
T26	701	301	0	0
T27	522	122	0	0
T28	999	599	0	0
T29	449	49	0	0
T30	452	52	0	0
T31	521	121	0	0
T32	630	230	0	0
T36	402	2	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8819542	224	0	0
T14	16320	5	0	0
T39	0	4	0	0
T42	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T57	450	0	0	0
T59	31937	1	0	0
T68	522	0	0	0
T69	486	0	0	0
T81	0	10	0	0
T128	0	3	0	0
T134	635	0	0	0
T135	422	0	0	0
T136	642	0	0	0
T137	422	0	0	0
T138	406	0	0	0
T180	0	3	0	0
T282	0	5	0	0