Cond split page
dashboard | hierarchy | modlist | groups | tests | asserts
Go back
 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT5,T6,T8
11CoveredT1,T2,T5

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT289,T290,T291
10CoveredT6,T8,T292

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T5
001CoveredT289,T290,T291
010CoveredT6,T8,T292
100CoveredT6,T8,T292

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T5
001CoveredT6,T8,T292
010CoveredT5,T293,T294
100CoveredT5,T293,T294

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T5
11CoveredT5,T6,T8

 LINE       2118
 EXPRESSION (aon_ec_rst_ctl_we & aon_ec_rst_ctl_regwen)
             --------1--------   ----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT1,T2,T3

 LINE       2149
 EXPRESSION (aon_ulp_ac_debounce_ctl_we & aon_ulp_ac_debounce_ctl_regwen)
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT2,T3,T4

 LINE       2181
 EXPRESSION (aon_ulp_lid_debounce_ctl_we & aon_ulp_lid_debounce_ctl_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT1,T4,T6

 LINE       2213
 EXPRESSION (aon_ulp_pwrb_debounce_ctl_we & aon_ulp_pwrb_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T7
11CoveredT1,T2,T3

 LINE       2333
 EXPRESSION (aon_key_invert_ctl_we & aon_key_invert_ctl_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T6
11CoveredT2,T3,T4

 LINE       2662
 EXPRESSION (aon_pin_allowed_ctl_we & aon_pin_allowed_ctl_regwen)
             -----------1----------   -------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT1,T2,T4

 LINE       3753
 EXPRESSION (aon_key_intr_ctl_we & aon_key_intr_ctl_regwen)
             ---------1---------   -----------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT2,T4,T6

 LINE       4136
 EXPRESSION (aon_key_intr_debounce_ctl_we & aon_key_intr_debounce_ctl_regwen)
             --------------1-------------   ----------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T6

 LINE       4168
 EXPRESSION (aon_auto_block_debounce_ctl_we & aon_auto_block_debounce_ctl_regwen)
             ---------------1--------------   -----------------2----------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT1,T2,T3

 LINE       4228
 EXPRESSION (aon_auto_block_out_ctl_we & aon_auto_block_out_ctl_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT3,T4,T6

 LINE       4397
 EXPRESSION (aon_com_pre_sel_ctl_0_we & aon_com_pre_sel_ctl_0_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT2,T3,T4

 LINE       4538
 EXPRESSION (aon_com_pre_sel_ctl_1_we & aon_com_pre_sel_ctl_1_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T6
11CoveredT1,T3,T4

 LINE       4679
 EXPRESSION (aon_com_pre_sel_ctl_2_we & aon_com_pre_sel_ctl_2_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T3,T4

 LINE       4820
 EXPRESSION (aon_com_pre_sel_ctl_3_we & aon_com_pre_sel_ctl_3_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T6,T7

 LINE       4961
 EXPRESSION (aon_com_pre_det_ctl_0_we & aon_com_pre_det_ctl_0_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T4
11CoveredT2,T3,T4

 LINE       4993
 EXPRESSION (aon_com_pre_det_ctl_1_we & aon_com_pre_det_ctl_1_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T7
11CoveredT1,T2,T3

 LINE       5025
 EXPRESSION (aon_com_pre_det_ctl_2_we & aon_com_pre_det_ctl_2_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T3,T4

 LINE       5057
 EXPRESSION (aon_com_pre_det_ctl_3_we & aon_com_pre_det_ctl_3_regwen)
             ------------1-----------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T7
11CoveredT1,T3,T4

 LINE       5089
 EXPRESSION (aon_com_sel_ctl_0_we & aon_com_sel_ctl_0_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T4,T6

 LINE       5230
 EXPRESSION (aon_com_sel_ctl_1_we & aon_com_sel_ctl_1_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T3,T4

 LINE       5371
 EXPRESSION (aon_com_sel_ctl_2_we & aon_com_sel_ctl_2_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T4,T6

 LINE       5512
 EXPRESSION (aon_com_sel_ctl_3_we & aon_com_sel_ctl_3_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT3,T4,T6

 LINE       5653
 EXPRESSION (aon_com_det_ctl_0_we & aon_com_det_ctl_0_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T3,T4

 LINE       5685
 EXPRESSION (aon_com_det_ctl_1_we & aon_com_det_ctl_1_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T4
11CoveredT1,T3,T4

 LINE       5717
 EXPRESSION (aon_com_det_ctl_2_we & aon_com_det_ctl_2_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T6

 LINE       5749
 EXPRESSION (aon_com_det_ctl_3_we & aon_com_det_ctl_3_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT4,T6,T7
11CoveredT1,T2,T3

 LINE       5781
 EXPRESSION (aon_com_out_ctl_0_we & aon_com_out_ctl_0_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT1,T2,T3

 LINE       5895
 EXPRESSION (aon_com_out_ctl_1_we & aon_com_out_ctl_1_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT3,T4,T6
11CoveredT1,T3,T4

 LINE       6009
 EXPRESSION (aon_com_out_ctl_2_we & aon_com_out_ctl_2_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T6
11CoveredT2,T4,T6

 LINE       6123
 EXPRESSION (aon_com_out_ctl_3_we & aon_com_out_ctl_3_regwen)
             ----------1---------   ------------2-----------
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T6
11CoveredT1,T3,T4

 LINE       6731
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_STATE_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6732
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_ENABLE_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6733
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_INTR_TEST_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T5,T22

 LINE       6734
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ALERT_TEST_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6735
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_REGWEN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6736
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_EC_RST_CTL_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6737
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_OFFSET)
            ------------------------------------1------------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6738
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1------------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6739
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6740
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_CTL_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6741
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_ULP_STATUS_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6742
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_WKUP_STATUS_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6743
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INVERT_CTL_OFFSET)
            ----------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6744
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_ALLOWED_CTL_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6745
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_CTL_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6746
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_OUT_VALUE_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6747
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_PIN_IN_VALUE_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6748
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_CTL_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6749
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_OFFSET)
            -------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6750
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET)
            --------------------------------------1--------------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6751
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_OFFSET)
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6752
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6753
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6754
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6755
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_SEL_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6756
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_0_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6757
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_1_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6758
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_2_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6759
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_PRE_DET_CTL_3_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6760
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_0_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6761
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_1_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6762
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_2_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6763
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_SEL_CTL_3_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6764
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_0_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6765
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_1_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6766
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_2_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6767
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_DET_CTL_3_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6768
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_0_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6769
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_1_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6770
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_2_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6771
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COM_OUT_CTL_3_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6772
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_COMBO_INTR_STATUS_OFFSET)
            -----------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6773
 EXPRESSION (reg_addr == sysrst_ctrl_reg_pkg::SYSRST_CTRL_KEY_INTR_STATUS_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6776
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T5

 LINE       6776
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T5
10CoveredT1,T2,T5

 LINE       6780
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT5,T6,T8

 LINE       6780
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b0011 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0011 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b0011 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b0011 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1111 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1111 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1111 & (~reg_be))))) | 
     29  (addr_hit[28] & ((|(4'b1111 & (~reg_be))))) | 
     30  (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | 
     31  (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | 
     32  (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | 
     33  (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | 
     34  (addr_hit[33] & ((|(4'b1111 & (~reg_be))))) | 
     35  (addr_hit[34] & ((|(4'b1111 & (~reg_be))))) | 
     36  (addr_hit[35] & ((|(4'b1111 & (~reg_be))))) | 
     37  (addr_hit[36] & ((|(4'b1111 & (~reg_be))))) | 
     38  (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | 
     39  (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | 
     40  (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | 
     41  (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | 
     42  (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | 
     43  (addr_hit[42] & ((|(4'b0011 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T5
43 (addr_hit[42] & ((|(4'...CoveredT1,T5,T23
42 (addr_hit[41] & ((|(4'...CoveredT1,T5,T23
41 (addr_hit[40] & ((|(4'...CoveredT1,T2,T5
40 (addr_hit[39] & ((|(4'...CoveredT1,T5,T23
39 (addr_hit[38] & ((|(4'...CoveredT1,T5,T23
38 (addr_hit[37] & ((|(4'...CoveredT1,T5,T23
37 (addr_hit[36] & ((|(4'...CoveredT1,T5,T23
36 (addr_hit[35] & ((|(4'...CoveredT1,T5,T23
35 (addr_hit[34] & ((|(4'...CoveredT1,T2,T5
34 (addr_hit[33] & ((|(4'...CoveredT1,T5,T23
33 (addr_hit[32] & ((|(4'...CoveredT1,T5,T23
32 (addr_hit[31] & ((|(4'...CoveredT1,T2,T5
31 (addr_hit[30] & ((|(4'...CoveredT1,T5,T23
30 (addr_hit[29] & ((|(4'...CoveredT1,T2,T5
29 (addr_hit[28] & ((|(4'...CoveredT1,T5,T23
28 (addr_hit[27] & ((|(4'...CoveredT1,T5,T23
27 (addr_hit[26] & ((|(4'...CoveredT1,T2,T5
26 (addr_hit[25] & ((|(4'...CoveredT1,T2,T5
25 (addr_hit[24] & ((|(4'...CoveredT1,T2,T5
24 (addr_hit[23] & ((|(4'...CoveredT1,T5,T23
23 (addr_hit[22] & ((|(4'...CoveredT1,T2,T5
22 (addr_hit[21] & ((|(4'...CoveredT1,T5,T23
21 (addr_hit[20] & ((|(4'...CoveredT1,T2,T5
20 (addr_hit[19] & ((|(4'...CoveredT1,T2,T5
19 (addr_hit[18] & ((|(4'...CoveredT1,T5,T23
18 (addr_hit[17] & ((|(4'...CoveredT1,T2,T5
17 (addr_hit[16] & ((|(4'...CoveredT1,T5,T23
16 (addr_hit[15] & ((|(4'...CoveredT1,T5,T23
15 (addr_hit[14] & ((|(4'...CoveredT1,T5,T23
14 (addr_hit[13] & ((|(4'...CoveredT1,T2,T5
13 (addr_hit[12] & ((|(4'...CoveredT1,T5,T23
12 (addr_hit[11] & ((|(4'...CoveredT1,T5,T23
11 (addr_hit[10] & ((|(4'...CoveredT1,T5,T7
10 (addr_hit[9] & ((|(4'b...CoveredT1,T2,T5
9 (addr_hit[8] & ((|(4'b...CoveredT1,T5,T23
8 (addr_hit[7] & ((|(4'b...CoveredT1,T5,T23
7 (addr_hit[6] & ((|(4'b...CoveredT1,T2,T5
6 (addr_hit[5] & ((|(4'b...CoveredT1,T5,T23
5 (addr_hit[4] & ((|(4'b...CoveredT1,T5,T23
4 (addr_hit[3] & ((|(4'b...CoveredT1,T2,T5
3 (addr_hit[2] & ((|(4'b...CoveredT1,T5,T22
2 (addr_hit[1] & ((|(4'b...CoveredT1,T5,T22
1 (addr_hit[0] & ((|(4'b...CoveredT1,T5,T22

 LINE       6780
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T22

 LINE       6780
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T22

 LINE       6780
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T5,T22
11CoveredT1,T5,T22

 LINE       6780
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T7

 LINE       6780
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T2,T5

 LINE       6780
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6780
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T5
11CoveredT1,T5,T23

 LINE       6827
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT5,T294,T295
111CoveredT22,T24,T37

 LINE       6830
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT293,T294,T295
111CoveredT1,T2,T22

 LINE       6833
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T5,T22
110CoveredT293,T296,T297
111CoveredT22,T24,T37

 LINE       6836
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT6,T293,T294
111CoveredT1,T2,T3

 LINE       6839
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT8,T293,T294
111CoveredT1,T2,T3

 LINE       6842
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT293,T294,T295
111CoveredT1,T2,T3

 LINE       6844
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT292,T294,T295
111CoveredT1,T2,T3

 LINE       6846
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T22
101CoveredT1,T2,T5
110CoveredT5,T293,T294
111CoveredT1,T3,T4
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%