Unified Coverage Report :: Module :: sysrst_ctrl_reg_top

Module : sysrst_ctrl_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.62	100.00	94.48			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	98.62	100.00	94.46			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.62	100.00	94.46			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.93	99.40	96.43	100.00		98.84	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_auto_block_debounce_ctl_auto_block_enable	100.00	100.00	100.00			100.00
u_auto_block_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_auto_block_debounce_ctl_debounce_timer	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_auto_block_out_ctl_key0_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key0_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key1_out_value	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_sel	100.00	100.00	100.00			100.00
u_auto_block_out_ctl_key2_out_value	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_com_det_ctl_0	100.00	100.00	100.00			100.00
u_com_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_1	100.00	100.00	100.00			100.00
u_com_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_2	100.00	100.00	100.00			100.00
u_com_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_det_ctl_3	100.00	100.00	100.00			100.00
u_com_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_bat_disable_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_0_ec_rst_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_interrupt_0	100.00	100.00	100.00			100.00
u_com_out_ctl_0_rst_req_0	100.00	100.00	100.00			100.00
u_com_out_ctl_1_bat_disable_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_1_ec_rst_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_interrupt_1	100.00	100.00	100.00			100.00
u_com_out_ctl_1_rst_req_1	100.00	100.00	100.00			100.00
u_com_out_ctl_2_bat_disable_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_2_ec_rst_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_interrupt_2	100.00	100.00	100.00			100.00
u_com_out_ctl_2_rst_req_2	100.00	100.00	100.00			100.00
u_com_out_ctl_3_bat_disable_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_out_ctl_3_ec_rst_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_interrupt_3	100.00	100.00	100.00			100.00
u_com_out_ctl_3_rst_req_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_1	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_2	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_det_ctl_3	100.00	100.00	100.00			100.00
u_com_pre_det_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_pre_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_pre_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_ac_present_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_0_key0_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key1_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_key2_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_0_pwrb_in_sel_0	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_ac_present_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_1_key0_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key1_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_key2_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_1_pwrb_in_sel_1	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_ac_present_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_2_key0_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key1_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_key2_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_2_pwrb_in_sel_2	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_ac_present_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_cdc	99.17	100.00	96.67			100.00	100.00
u_com_sel_ctl_3_key0_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key1_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_key2_in_sel_3	100.00	100.00	100.00			100.00
u_com_sel_ctl_3_pwrb_in_sel_3	100.00	100.00	100.00			100.00
u_combo_intr_status_cdc	96.76	100.00	88.73			98.31	100.00
u_combo_intr_status_combo0_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo1_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo2_h2l	100.00	100.00	100.00			100.00
u_combo_intr_status_combo3_h2l	100.00	100.00	100.00			100.00
u_ec_rst_ctl	100.00	100.00	100.00			100.00
u_ec_rst_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_intr_enable	100.00	100.00	100.00			100.00
u_intr_state	100.00	100.00	100.00			100.00
u_intr_test	100.00	100.00
u_key_intr_ctl_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_intr_ctl_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_ctl_pwrb_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl	100.00	100.00	100.00			100.00
u_key_intr_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_key_intr_status_ac_present_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ac_present_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_cdc	96.76	100.00	88.73			98.31	100.00
u_key_intr_status_ec_rst_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_ec_rst_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_flash_wp_l_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key0_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key1_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_key2_in_l2h	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_h2l	100.00	100.00	100.00			100.00
u_key_intr_status_pwrb_l2h	100.00	100.00	100.00			100.00
u_key_invert_ctl_ac_present	100.00	100.00	100.00			100.00
u_key_invert_ctl_bat_disable	100.00	100.00	100.00			100.00
u_key_invert_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_key_invert_ctl_key0_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key0_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key1_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_key2_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_lid_open	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_in	100.00	100.00	100.00			100.00
u_key_invert_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_key_invert_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_bat_disable_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_allowed_ctl_ec_rst_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_ec_rst_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_flash_wp_l_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key0_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key1_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_key2_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_pwrb_out_1	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_0	100.00	100.00	100.00			100.00
u_pin_allowed_ctl_z3_wakeup_1	100.00	100.00	100.00			100.00
u_pin_in_value_ac_present	62.59	77.78	50.00			60.00
u_pin_in_value_ec_rst_l	62.59	77.78	50.00			60.00
u_pin_in_value_flash_wp_l	62.59	77.78	50.00			60.00
u_pin_in_value_key0_in	62.59	77.78	50.00			60.00
u_pin_in_value_key1_in	62.59	77.78	50.00			60.00
u_pin_in_value_key2_in	62.59	77.78	50.00			60.00
u_pin_in_value_lid_open	62.59	77.78	50.00			60.00
u_pin_in_value_pwrb_in	62.59	77.78	50.00			60.00
u_pin_out_ctl_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_ctl_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_ctl_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_ctl_key0_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key1_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_key2_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_ctl_z3_wakeup	100.00	100.00	100.00			100.00
u_pin_out_value_bat_disable	100.00	100.00	100.00			100.00
u_pin_out_value_cdc	99.17	100.00	96.67			100.00	100.00
u_pin_out_value_ec_rst_l	100.00	100.00	100.00			100.00
u_pin_out_value_flash_wp_l	100.00	100.00	100.00			100.00
u_pin_out_value_key0_out	100.00	100.00	100.00			100.00
u_pin_out_value_key1_out	100.00	100.00	100.00			100.00
u_pin_out_value_key2_out	100.00	100.00	100.00			100.00
u_pin_out_value_pwrb_out	100.00	100.00	100.00			100.00
u_pin_out_value_z3_wakeup	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.69	97.14	97.62			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_ulp_ac_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_ac_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_ctl	100.00	100.00	100.00			100.00
u_ulp_ctl_cdc	99.22	100.00	96.88			100.00	100.00
u_ulp_lid_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_lid_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_pwrb_debounce_ctl	100.00	100.00	100.00			100.00
u_ulp_pwrb_debounce_ctl_cdc	98.33	100.00	93.33			100.00	100.00
u_ulp_status	100.00	100.00	100.00			100.00
u_ulp_status_cdc	93.79	96.99	84.93			93.22	100.00
u_wkup_status	100.00	100.00	100.00			100.00
u_wkup_status_cdc	93.79	96.99	84.93			93.22	100.00

Line Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
TOTAL		532	532	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	272	2	2	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	311	2	2	100.00
CONT_ASSIGN	339	1	1	100.00
ALWAYS	350	2	2	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	389	2	2	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	427	2	2	100.00
CONT_ASSIGN	455	1	1	100.00
ALWAYS	468	4	4	100.00
CONT_ASSIGN	498	1	1	100.00
ALWAYS	511	4	4	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	563	13	13	100.00
CONT_ASSIGN	602	1	1	100.00
ALWAYS	628	17	17	100.00
CONT_ASSIGN	671	1	1	100.00
ALWAYS	688	9	9	100.00
CONT_ASSIGN	723	1	1	100.00
ALWAYS	740	9	9	100.00
CONT_ASSIGN	775	1	1	100.00
ALWAYS	799	15	15	100.00
CONT_ASSIGN	840	1	1	100.00
ALWAYS	851	2	2	100.00
CONT_ASSIGN	879	1	1	100.00
ALWAYS	891	3	3	100.00
CONT_ASSIGN	920	1	1	100.00
ALWAYS	936	7	7	100.00
CONT_ASSIGN	969	1	1	100.00
ALWAYS	984	6	6	100.00
CONT_ASSIGN	1016	1	1	100.00
ALWAYS	1031	6	6	100.00
CONT_ASSIGN	1063	1	1	100.00
ALWAYS	1078	6	6	100.00
CONT_ASSIGN	1110	1	1	100.00
ALWAYS	1125	6	6	100.00
CONT_ASSIGN	1157	1	1	100.00
ALWAYS	1168	2	2	100.00
CONT_ASSIGN	1196	1	1	100.00
ALWAYS	1207	2	2	100.00
CONT_ASSIGN	1235	1	1	100.00
ALWAYS	1246	2	2	100.00
CONT_ASSIGN	1274	1	1	100.00
ALWAYS	1285	2	2	100.00
CONT_ASSIGN	1313	1	1	100.00
ALWAYS	1328	6	6	100.00
CONT_ASSIGN	1360	1	1	100.00
ALWAYS	1375	6	6	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1422	6	6	100.00
CONT_ASSIGN	1454	1	1	100.00
ALWAYS	1469	6	6	100.00
CONT_ASSIGN	1501	1	1	100.00
ALWAYS	1512	2	2	100.00
CONT_ASSIGN	1540	1	1	100.00
ALWAYS	1551	2	2	100.00
CONT_ASSIGN	1579	1	1	100.00
ALWAYS	1590	2	2	100.00
CONT_ASSIGN	1618	1	1	100.00
ALWAYS	1629	2	2	100.00
CONT_ASSIGN	1657	1	1	100.00
ALWAYS	1671	5	5	100.00
CONT_ASSIGN	1702	1	1	100.00
ALWAYS	1716	5	5	100.00
CONT_ASSIGN	1747	1	1	100.00
ALWAYS	1761	5	5	100.00
CONT_ASSIGN	1792	1	1	100.00
ALWAYS	1806	5	5	100.00
CONT_ASSIGN	1837	1	1	100.00
ALWAYS	1856	10	10	100.00
CONT_ASSIGN	1892	1	1	100.00
ALWAYS	1931	30	30	100.00
CONT_ASSIGN	1987	1	1	100.00
CONT_ASSIGN	2050	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2070	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2213	1	1	100.00
CONT_ASSIGN	2272	1	1	100.00
CONT_ASSIGN	2302	1	1	100.00
CONT_ASSIGN	2333	1	1	100.00
CONT_ASSIGN	2662	1	1	100.00
CONT_ASSIGN	3753	1	1	100.00
CONT_ASSIGN	4136	1	1	100.00
CONT_ASSIGN	4168	1	1	100.00
CONT_ASSIGN	4228	1	1	100.00
CONT_ASSIGN	4397	1	1	100.00
CONT_ASSIGN	4538	1	1	100.00
CONT_ASSIGN	4679	1	1	100.00
CONT_ASSIGN	4820	1	1	100.00
CONT_ASSIGN	4961	1	1	100.00
CONT_ASSIGN	4993	1	1	100.00
CONT_ASSIGN	5025	1	1	100.00
CONT_ASSIGN	5057	1	1	100.00
CONT_ASSIGN	5089	1	1	100.00
CONT_ASSIGN	5230	1	1	100.00
CONT_ASSIGN	5371	1	1	100.00
CONT_ASSIGN	5512	1	1	100.00
CONT_ASSIGN	5653	1	1	100.00
CONT_ASSIGN	5685	1	1	100.00
CONT_ASSIGN	5717	1	1	100.00
CONT_ASSIGN	5749	1	1	100.00
CONT_ASSIGN	5781	1	1	100.00
CONT_ASSIGN	5895	1	1	100.00
CONT_ASSIGN	6009	1	1	100.00
CONT_ASSIGN	6123	1	1	100.00
CONT_ASSIGN	6235	1	1	100.00
CONT_ASSIGN	6347	1	1	100.00
ALWAYS	6730	44	44	100.00
CONT_ASSIGN	6776	1	1	100.00
ALWAYS	6780	1	1	100.00
CONT_ASSIGN	6827	1	1	100.00
CONT_ASSIGN	6829	1	1	100.00
CONT_ASSIGN	6830	1	1	100.00
CONT_ASSIGN	6832	1	1	100.00
CONT_ASSIGN	6833	1	1	100.00
CONT_ASSIGN	6835	1	1	100.00
CONT_ASSIGN	6836	1	1	100.00
CONT_ASSIGN	6838	1	1	100.00
CONT_ASSIGN	6839	1	1	100.00
CONT_ASSIGN	6841	1	1	100.00
CONT_ASSIGN	6842	1	1	100.00
CONT_ASSIGN	6844	1	1	100.00
CONT_ASSIGN	6846	1	1	100.00
CONT_ASSIGN	6848	1	1	100.00
CONT_ASSIGN	6850	1	1	100.00
CONT_ASSIGN	6852	1	1	100.00
CONT_ASSIGN	6854	1	1	100.00
CONT_ASSIGN	6856	1	1	100.00
CONT_ASSIGN	6869	1	1	100.00
CONT_ASSIGN	6886	1	1	100.00
CONT_ASSIGN	6895	1	1	100.00
CONT_ASSIGN	6904	1	1	100.00
CONT_ASSIGN	6919	1	1	100.00
CONT_ASSIGN	6921	1	1	100.00
CONT_ASSIGN	6924	1	1	100.00
CONT_ASSIGN	6931	1	1	100.00
CONT_ASSIGN	6937	1	1	100.00
CONT_ASSIGN	6943	1	1	100.00
CONT_ASSIGN	6949	1	1	100.00
CONT_ASSIGN	6955	1	1	100.00
CONT_ASSIGN	6957	1	1	100.00
CONT_ASSIGN	6959	1	1	100.00
CONT_ASSIGN	6961	1	1	100.00
CONT_ASSIGN	6963	1	1	100.00
CONT_ASSIGN	6969	1	1	100.00
CONT_ASSIGN	6975	1	1	100.00
CONT_ASSIGN	6981	1	1	100.00
CONT_ASSIGN	6987	1	1	100.00
CONT_ASSIGN	6989	1	1	100.00
CONT_ASSIGN	6991	1	1	100.00
CONT_ASSIGN	6993	1	1	100.00
CONT_ASSIGN	6995	1	1	100.00
CONT_ASSIGN	7000	1	1	100.00
CONT_ASSIGN	7005	1	1	100.00
CONT_ASSIGN	7010	1	1	100.00
CONT_ASSIGN	7015	1	1	100.00
CONT_ASSIGN	7020	1	1	100.00
ALWAYS	7038	44	44	100.00
ALWAYS	7086	52	52	100.00
CONT_ASSIGN	7242	1	1	100.00
ALWAYS	7244	39	39	100.00
CONT_ASSIGN	7370	1	1	100.00
CONT_ASSIGN	7371	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
272	1	1
273	1	1
300	1	1
311	1	1
312	1	1
339	1	1
350	1	1
351	1	1
378	1	1
389	1	1
390	1	1
417	1	1
427	1	1
428	1	1
455	1	1
468	1	1
469	1	1
470	1	1
471	1	1
498	1	1
511	1	1
512	1	1
513	1	1
514	1	1
541	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	1	1
602	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
671	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
723	1	1
740	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
775	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
810	1	1
811	1	1
812	1	1
813	1	1
840	1	1
851	1	1
852	1	1
879	1	1
891	1	1
892	1	1
893	1	1
920	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
942	1	1
969	1	1
984	1	1
985	1	1
986	1	1
987	1	1
988	1	1
989	1	1
1016	1	1
1031	1	1
1032	1	1
1033	1	1
1034	1	1
1035	1	1
1036	1	1
1063	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1083	1	1
1110	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
1129	1	1
1130	1	1
1157	1	1
1168	1	1
1169	1	1
1196	1	1
1207	1	1
1208	1	1
1235	1	1
1246	1	1
1247	1	1
1274	1	1
1285	1	1
1286	1	1
1313	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1360	1	1
1375	1	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1380	1	1
1407	1	1
1422	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1427	1	1
1454	1	1
1469	1	1
1470	1	1
1471	1	1
1472	1	1
1473	1	1
1474	1	1
1501	1	1
1512	1	1
1513	1	1
1540	1	1
1551	1	1
1552	1	1
1579	1	1
1590	1	1
1591	1	1
1618	1	1
1629	1	1
1630	1	1
1657	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1702	1	1
1716	1	1
1717	1	1
1718	1	1
1719	1	1
1720	1	1
1747	1	1
1761	1	1
1762	1	1
1763	1	1
1764	1	1
1765	1	1
1792	1	1
1806	1	1
1807	1	1
1808	1	1
1809	1	1
1810	1	1
1837	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1892	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1958	1	1
1959	1	1
1960	1	1
1987	1	1
2050	1	1
2064	1	1
2070	1	1
2084	1	1
2118	1	1
2149	1	1
2181	1	1
2213	1	1
2272	1	1
2302	1	1
2333	1	1
2662	1	1
3753	1	1
4136	1	1
4168	1	1
4228	1	1
4397	1	1
4538	1	1
4679	1	1
4820	1	1
4961	1	1
4993	1	1
5025	1	1
5057	1	1
5089	1	1
5230	1	1
5371	1	1
5512	1	1
5653	1	1
5685	1	1
5717	1	1
5749	1	1
5781	1	1
5895	1	1
6009	1	1
6123	1	1
6235	1	1
6347	1	1
6730	1	1
6731	1	1
6732	1	1
6733	1	1
6734	1	1
6735	1	1
6736	1	1
6737	1	1
6738	1	1
6739	1	1
6740	1	1
6741	1	1
6742	1	1
6743	1	1
6744	1	1
6745	1	1
6746	1	1
6747	1	1
6748	1	1
6749	1	1
6750	1	1
6751	1	1
6752	1	1
6753	1	1
6754	1	1
6755	1	1
6756	1	1
6757	1	1
6758	1	1
6759	1	1
6760	1	1
6761	1	1
6762	1	1
6763	1	1
6764	1	1
6765	1	1
6766	1	1
6767	1	1
6768	1	1
6769	1	1
6770	1	1
6771	1	1
6772	1	1
6773	1	1
6776	1	1
6780	1	1
6827	1	1
6829	1	1
6830	1	1
6832	1	1
6833	1	1
6835	1	1
6836	1	1
6838	1	1
6839	1	1
6841	1	1
6842	1	1
6844	1	1
6846	1	1
6848	1	1
6850	1	1
6852	1	1
6854	1	1
6856	1	1
6869	1	1
6886	1	1
6895	1	1
6904	1	1
6919	1	1
6921	1	1
6924	1	1
6931	1	1
6937	1	1
6943	1	1
6949	1	1
6955	1	1
6957	1	1
6959	1	1
6961	1	1
6963	1	1
6969	1	1
6975	1	1
6981	1	1
6987	1	1
6989	1	1
6991	1	1
6993	1	1
6995	1	1
7000	1	1
7005	1	1
7010	1	1
7015	1	1
7020	1	1
7038	1	1
7039	1	1
7040	1	1
7041	1	1
7042	1	1
7043	1	1
7044	1	1
7045	1	1
7046	1	1
7047	1	1
7048	1	1
7049	1	1
7050	1	1
7051	1	1
7052	1	1
7053	1	1
7054	1	1
7055	1	1
7056	1	1
7057	1	1
7058	1	1
7059	1	1
7060	1	1
7061	1	1
7062	1	1
7063	1	1
7064	1	1
7065	1	1
7066	1	1
7067	1	1
7068	1	1
7069	1	1
7070	1	1
7071	1	1
7072	1	1
7073	1	1
7074	1	1
7075	1	1
7076	1	1
7077	1	1
7078	1	1
7079	1	1
7080	1	1
7081	1	1
7086	1	1
7087	1	1
7089	1	1
7093	1	1
7097	1	1
7101	1	1
7105	1	1
7109	1	1
7112	1	1
7115	1	1
7118	1	1
7121	1	1
7124	1	1
7127	1	1
7130	1	1
7133	1	1
7136	1	1
7139	1	1
7142	1	1
7143	1	1
7144	1	1
7145	1	1
7146	1	1
7147	1	1
7148	1	1
7149	1	1
7153	1	1
7156	1	1
7159	1	1
7162	1	1
7165	1	1
7168	1	1
7171	1	1
7174	1	1
7177	1	1
7180	1	1
7183	1	1
7186	1	1
7189	1	1
7192	1	1
7195	1	1
7198	1	1
7201	1	1
7204	1	1
7207	1	1
7210	1	1
7213	1	1
7216	1	1
7219	1	1
7222	1	1
7225	1	1
7228	1	1
7242	1	1
7244	1	1
7245	1	1
7247	1	1
7250	1	1
7253	1	1
7256	1	1
7259	1	1
7262	1	1
7265	1	1
7268	1	1
7271	1	1
7274	1	1
7277	1	1
7280	1	1
7283	1	1
7286	1	1
7289	1	1
7292	1	1
7295	1	1
7298	1	1
7301	1	1
7304	1	1
7307	1	1
7310	1	1
7313	1	1
7316	1	1
7319	1	1
7322	1	1
7325	1	1
7328	1	1
7331	1	1
7334	1	1
7337	1	1
7340	1	1
7343	1	1
7346	1	1
7349	1	1
7352	1	1
7355	1	1
7370	1	1
7371	1	1

---

Cond Coverage for Module : sysrst_ctrl_reg_top

	Total	Covered	Percent
Conditions	543	513	94.48
Logical	543	513	94.48
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-6846	92.59
6848-7242	100.00

---

Branch Coverage for Module : sysrst_ctrl_reg_top

	Line No.	Total	Covered	Percent
Branches		87	87	100.00
TERNARY	6776	2	2	100.00
IF	73	3	3	100.00
CASE	7087	44	44	100.00
CASE	7245	38	38	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	6776	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T6,T8,T292
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	7087	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T5
addr_hit[1]	Covered	T1,T2,T5
addr_hit[2]	Covered	T1,T2,T5
addr_hit[3]	Covered	T1,T2,T5
addr_hit[4]	Covered	T1,T2,T5
addr_hit[5]	Covered	T1,T2,T5
addr_hit[6]	Covered	T1,T2,T5
addr_hit[7]	Covered	T1,T2,T5
addr_hit[8]	Covered	T1,T2,T5
addr_hit[9]	Covered	T1,T2,T5
addr_hit[10]	Covered	T1,T2,T5
addr_hit[11]	Covered	T1,T2,T5
addr_hit[12]	Covered	T1,T2,T5
addr_hit[13]	Covered	T1,T2,T5
addr_hit[14]	Covered	T1,T2,T5
addr_hit[15]	Covered	T1,T2,T5
addr_hit[16]	Covered	T1,T2,T5
addr_hit[17]	Covered	T1,T2,T5
addr_hit[18]	Covered	T1,T2,T5
addr_hit[19]	Covered	T1,T2,T5
addr_hit[20]	Covered	T1,T2,T5
addr_hit[21]	Covered	T1,T2,T5
addr_hit[22]	Covered	T1,T2,T5
addr_hit[23]	Covered	T1,T2,T5
addr_hit[24]	Covered	T1,T2,T5
addr_hit[25]	Covered	T1,T2,T5
addr_hit[26]	Covered	T1,T2,T5
addr_hit[27]	Covered	T1,T2,T5
addr_hit[28]	Covered	T1,T2,T5
addr_hit[29]	Covered	T1,T2,T5
addr_hit[30]	Covered	T1,T2,T5
addr_hit[31]	Covered	T1,T2,T5
addr_hit[32]	Covered	T1,T2,T5
addr_hit[33]	Covered	T1,T2,T5
addr_hit[34]	Covered	T1,T2,T5
addr_hit[35]	Covered	T1,T2,T5
addr_hit[36]	Covered	T1,T2,T5
addr_hit[37]	Covered	T1,T2,T5
addr_hit[38]	Covered	T1,T2,T5
addr_hit[39]	Covered	T1,T2,T5
addr_hit[40]	Covered	T1,T2,T5
addr_hit[41]	Covered	T1,T2,T5
addr_hit[42]	Covered	T1,T2,T5
default	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	7245	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T1,T2,T5
addr_hit[6]	Covered	T1,T2,T5
addr_hit[7]	Covered	T1,T2,T5
addr_hit[8]	Covered	T1,T2,T5
addr_hit[9]	Covered	T1,T2,T5
addr_hit[10]	Covered	T1,T2,T5
addr_hit[11]	Covered	T1,T2,T5
addr_hit[12]	Covered	T1,T2,T5
addr_hit[13]	Covered	T1,T2,T5
addr_hit[14]	Covered	T1,T2,T5
addr_hit[15]	Covered	T1,T2,T5
addr_hit[17]	Covered	T1,T2,T5
addr_hit[18]	Covered	T1,T2,T5
addr_hit[19]	Covered	T1,T2,T5
addr_hit[20]	Covered	T1,T2,T5
addr_hit[21]	Covered	T1,T2,T5
addr_hit[22]	Covered	T1,T2,T5
addr_hit[23]	Covered	T1,T2,T5
addr_hit[24]	Covered	T1,T2,T5
addr_hit[25]	Covered	T1,T2,T5
addr_hit[26]	Covered	T1,T2,T5
addr_hit[27]	Covered	T1,T2,T5
addr_hit[28]	Covered	T1,T2,T5
addr_hit[29]	Covered	T1,T2,T5
addr_hit[30]	Covered	T1,T2,T5
addr_hit[31]	Covered	T1,T2,T5
addr_hit[32]	Covered	T1,T2,T5
addr_hit[33]	Covered	T1,T2,T5
addr_hit[34]	Covered	T1,T2,T5
addr_hit[35]	Covered	T1,T2,T5
addr_hit[36]	Covered	T1,T2,T5
addr_hit[37]	Covered	T1,T2,T5
addr_hit[38]	Covered	T1,T2,T5
addr_hit[39]	Covered	T1,T2,T5
addr_hit[40]	Covered	T1,T2,T5
addr_hit[41]	Covered	T1,T2,T5
addr_hit[42]	Covered	T1,T2,T5
default	Covered	T1,T2,T5

---

Assert Coverage for Module : sysrst_ctrl_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1352205319	263612	0	0
reAfterRv	1352205319	263608	0	0
rePulse	1352205319	137080	0	0
wePulse	1352205319	126528	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	263612	0	0
T1	500852	407	0	0
T2	100133	73	0	0
T3	967042	856	0	0
T4	507152	903	0	0
T5	194417	27	0	0
T6	109305	1236	0	0
T7	143114	401	0	0
T22	97139	39	0	0
T23	21412	59	0	0
T24	193176	21	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	263608	0	0
T1	500852	407	0	0
T2	100133	73	0	0
T3	967042	856	0	0
T4	507152	903	0	0
T5	194417	27	0	0
T6	109305	1236	0	0
T7	143114	401	0	0
T22	97139	39	0	0
T23	21412	59	0	0
T24	193176	21	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	137080	0	0
T1	500852	193	0	0
T2	100133	35	0	0
T3	967042	411	0	0
T4	507152	439	0	0
T5	194417	5	0	0
T6	109305	840	0	0
T7	143114	178	0	0
T22	97139	20	0	0
T23	21412	43	0	0
T24	193176	11	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	126528	0	0
T1	500852	214	0	0
T2	100133	38	0	0
T3	967042	445	0	0
T4	507152	464	0	0
T5	194417	22	0	0
T6	109305	396	0	0
T7	143114	223	0	0
T22	97139	19	0	0
T23	21412	16	0	0
T24	193176	10	0	0

Line Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
TOTAL		532	532	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
CONT_ASSIGN	95	1	1	100.00
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	272	2	2	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	311	2	2	100.00
CONT_ASSIGN	339	1	1	100.00
ALWAYS	350	2	2	100.00
CONT_ASSIGN	378	1	1	100.00
ALWAYS	389	2	2	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	427	2	2	100.00
CONT_ASSIGN	455	1	1	100.00
ALWAYS	468	4	4	100.00
CONT_ASSIGN	498	1	1	100.00
ALWAYS	511	4	4	100.00
CONT_ASSIGN	541	1	1	100.00
ALWAYS	563	13	13	100.00
CONT_ASSIGN	602	1	1	100.00
ALWAYS	628	17	17	100.00
CONT_ASSIGN	671	1	1	100.00
ALWAYS	688	9	9	100.00
CONT_ASSIGN	723	1	1	100.00
ALWAYS	740	9	9	100.00
CONT_ASSIGN	775	1	1	100.00
ALWAYS	799	15	15	100.00
CONT_ASSIGN	840	1	1	100.00
ALWAYS	851	2	2	100.00
CONT_ASSIGN	879	1	1	100.00
ALWAYS	891	3	3	100.00
CONT_ASSIGN	920	1	1	100.00
ALWAYS	936	7	7	100.00
CONT_ASSIGN	969	1	1	100.00
ALWAYS	984	6	6	100.00
CONT_ASSIGN	1016	1	1	100.00
ALWAYS	1031	6	6	100.00
CONT_ASSIGN	1063	1	1	100.00
ALWAYS	1078	6	6	100.00
CONT_ASSIGN	1110	1	1	100.00
ALWAYS	1125	6	6	100.00
CONT_ASSIGN	1157	1	1	100.00
ALWAYS	1168	2	2	100.00
CONT_ASSIGN	1196	1	1	100.00
ALWAYS	1207	2	2	100.00
CONT_ASSIGN	1235	1	1	100.00
ALWAYS	1246	2	2	100.00
CONT_ASSIGN	1274	1	1	100.00
ALWAYS	1285	2	2	100.00
CONT_ASSIGN	1313	1	1	100.00
ALWAYS	1328	6	6	100.00
CONT_ASSIGN	1360	1	1	100.00
ALWAYS	1375	6	6	100.00
CONT_ASSIGN	1407	1	1	100.00
ALWAYS	1422	6	6	100.00
CONT_ASSIGN	1454	1	1	100.00
ALWAYS	1469	6	6	100.00
CONT_ASSIGN	1501	1	1	100.00
ALWAYS	1512	2	2	100.00
CONT_ASSIGN	1540	1	1	100.00
ALWAYS	1551	2	2	100.00
CONT_ASSIGN	1579	1	1	100.00
ALWAYS	1590	2	2	100.00
CONT_ASSIGN	1618	1	1	100.00
ALWAYS	1629	2	2	100.00
CONT_ASSIGN	1657	1	1	100.00
ALWAYS	1671	5	5	100.00
CONT_ASSIGN	1702	1	1	100.00
ALWAYS	1716	5	5	100.00
CONT_ASSIGN	1747	1	1	100.00
ALWAYS	1761	5	5	100.00
CONT_ASSIGN	1792	1	1	100.00
ALWAYS	1806	5	5	100.00
CONT_ASSIGN	1837	1	1	100.00
ALWAYS	1856	10	10	100.00
CONT_ASSIGN	1892	1	1	100.00
ALWAYS	1931	30	30	100.00
CONT_ASSIGN	1987	1	1	100.00
CONT_ASSIGN	2050	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2070	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2213	1	1	100.00
CONT_ASSIGN	2272	1	1	100.00
CONT_ASSIGN	2302	1	1	100.00
CONT_ASSIGN	2333	1	1	100.00
CONT_ASSIGN	2662	1	1	100.00
CONT_ASSIGN	3753	1	1	100.00
CONT_ASSIGN	4136	1	1	100.00
CONT_ASSIGN	4168	1	1	100.00
CONT_ASSIGN	4228	1	1	100.00
CONT_ASSIGN	4397	1	1	100.00
CONT_ASSIGN	4538	1	1	100.00
CONT_ASSIGN	4679	1	1	100.00
CONT_ASSIGN	4820	1	1	100.00
CONT_ASSIGN	4961	1	1	100.00
CONT_ASSIGN	4993	1	1	100.00
CONT_ASSIGN	5025	1	1	100.00
CONT_ASSIGN	5057	1	1	100.00
CONT_ASSIGN	5089	1	1	100.00
CONT_ASSIGN	5230	1	1	100.00
CONT_ASSIGN	5371	1	1	100.00
CONT_ASSIGN	5512	1	1	100.00
CONT_ASSIGN	5653	1	1	100.00
CONT_ASSIGN	5685	1	1	100.00
CONT_ASSIGN	5717	1	1	100.00
CONT_ASSIGN	5749	1	1	100.00
CONT_ASSIGN	5781	1	1	100.00
CONT_ASSIGN	5895	1	1	100.00
CONT_ASSIGN	6009	1	1	100.00
CONT_ASSIGN	6123	1	1	100.00
CONT_ASSIGN	6235	1	1	100.00
CONT_ASSIGN	6347	1	1	100.00
ALWAYS	6730	44	44	100.00
CONT_ASSIGN	6776	1	1	100.00
ALWAYS	6780	1	1	100.00
CONT_ASSIGN	6827	1	1	100.00
CONT_ASSIGN	6829	1	1	100.00
CONT_ASSIGN	6830	1	1	100.00
CONT_ASSIGN	6832	1	1	100.00
CONT_ASSIGN	6833	1	1	100.00
CONT_ASSIGN	6835	1	1	100.00
CONT_ASSIGN	6836	1	1	100.00
CONT_ASSIGN	6838	1	1	100.00
CONT_ASSIGN	6839	1	1	100.00
CONT_ASSIGN	6841	1	1	100.00
CONT_ASSIGN	6842	1	1	100.00
CONT_ASSIGN	6844	1	1	100.00
CONT_ASSIGN	6846	1	1	100.00
CONT_ASSIGN	6848	1	1	100.00
CONT_ASSIGN	6850	1	1	100.00
CONT_ASSIGN	6852	1	1	100.00
CONT_ASSIGN	6854	1	1	100.00
CONT_ASSIGN	6856	1	1	100.00
CONT_ASSIGN	6869	1	1	100.00
CONT_ASSIGN	6886	1	1	100.00
CONT_ASSIGN	6895	1	1	100.00
CONT_ASSIGN	6904	1	1	100.00
CONT_ASSIGN	6919	1	1	100.00
CONT_ASSIGN	6921	1	1	100.00
CONT_ASSIGN	6924	1	1	100.00
CONT_ASSIGN	6931	1	1	100.00
CONT_ASSIGN	6937	1	1	100.00
CONT_ASSIGN	6943	1	1	100.00
CONT_ASSIGN	6949	1	1	100.00
CONT_ASSIGN	6955	1	1	100.00
CONT_ASSIGN	6957	1	1	100.00
CONT_ASSIGN	6959	1	1	100.00
CONT_ASSIGN	6961	1	1	100.00
CONT_ASSIGN	6963	1	1	100.00
CONT_ASSIGN	6969	1	1	100.00
CONT_ASSIGN	6975	1	1	100.00
CONT_ASSIGN	6981	1	1	100.00
CONT_ASSIGN	6987	1	1	100.00
CONT_ASSIGN	6989	1	1	100.00
CONT_ASSIGN	6991	1	1	100.00
CONT_ASSIGN	6993	1	1	100.00
CONT_ASSIGN	6995	1	1	100.00
CONT_ASSIGN	7000	1	1	100.00
CONT_ASSIGN	7005	1	1	100.00
CONT_ASSIGN	7010	1	1	100.00
CONT_ASSIGN	7015	1	1	100.00
CONT_ASSIGN	7020	1	1	100.00
ALWAYS	7038	44	44	100.00
ALWAYS	7086	52	52	100.00
CONT_ASSIGN	7242	1	1	100.00
ALWAYS	7244	39	39	100.00
CONT_ASSIGN	7370	1	1	100.00
CONT_ASSIGN	7371	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
94	1	1
95	1	1
123	1	1
124	1	1
272	1	1
273	1	1
300	1	1
311	1	1
312	1	1
339	1	1
350	1	1
351	1	1
378	1	1
389	1	1
390	1	1
417	1	1
427	1	1
428	1	1
455	1	1
468	1	1
469	1	1
470	1	1
471	1	1
498	1	1
511	1	1
512	1	1
513	1	1
514	1	1
541	1	1
563	1	1
564	1	1
565	1	1
566	1	1
567	1	1
568	1	1
569	1	1
570	1	1
571	1	1
572	1	1
573	1	1
574	1	1
575	1	1
602	1	1
628	1	1
629	1	1
630	1	1
631	1	1
632	1	1
633	1	1
634	1	1
635	1	1
636	1	1
637	1	1
638	1	1
639	1	1
640	1	1
641	1	1
642	1	1
643	1	1
644	1	1
671	1	1
688	1	1
689	1	1
690	1	1
691	1	1
692	1	1
693	1	1
694	1	1
695	1	1
696	1	1
723	1	1
740	1	1
741	1	1
742	1	1
743	1	1
744	1	1
745	1	1
746	1	1
747	1	1
748	1	1
775	1	1
799	1	1
800	1	1
801	1	1
802	1	1
803	1	1
804	1	1
805	1	1
806	1	1
807	1	1
808	1	1
809	1	1
810	1	1
811	1	1
812	1	1
813	1	1
840	1	1
851	1	1
852	1	1
879	1	1
891	1	1
892	1	1
893	1	1
920	1	1
936	1	1
937	1	1
938	1	1
939	1	1
940	1	1
941	1	1
942	1	1
969	1	1
984	1	1
985	1	1
986	1	1
987	1	1
988	1	1
989	1	1
1016	1	1
1031	1	1
1032	1	1
1033	1	1
1034	1	1
1035	1	1
1036	1	1
1063	1	1
1078	1	1
1079	1	1
1080	1	1
1081	1	1
1082	1	1
1083	1	1
1110	1	1
1125	1	1
1126	1	1
1127	1	1
1128	1	1
1129	1	1
1130	1	1
1157	1	1
1168	1	1
1169	1	1
1196	1	1
1207	1	1
1208	1	1
1235	1	1
1246	1	1
1247	1	1
1274	1	1
1285	1	1
1286	1	1
1313	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1360	1	1
1375	1	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1380	1	1
1407	1	1
1422	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1427	1	1
1454	1	1
1469	1	1
1470	1	1
1471	1	1
1472	1	1
1473	1	1
1474	1	1
1501	1	1
1512	1	1
1513	1	1
1540	1	1
1551	1	1
1552	1	1
1579	1	1
1590	1	1
1591	1	1
1618	1	1
1629	1	1
1630	1	1
1657	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1675	1	1
1702	1	1
1716	1	1
1717	1	1
1718	1	1
1719	1	1
1720	1	1
1747	1	1
1761	1	1
1762	1	1
1763	1	1
1764	1	1
1765	1	1
1792	1	1
1806	1	1
1807	1	1
1808	1	1
1809	1	1
1810	1	1
1837	1	1
1856	1	1
1857	1	1
1858	1	1
1859	1	1
1860	1	1
1861	1	1
1862	1	1
1863	1	1
1864	1	1
1865	1	1
1892	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1958	1	1
1959	1	1
1960	1	1
1987	1	1
2050	1	1
2064	1	1
2070	1	1
2084	1	1
2118	1	1
2149	1	1
2181	1	1
2213	1	1
2272	1	1
2302	1	1
2333	1	1
2662	1	1
3753	1	1
4136	1	1
4168	1	1
4228	1	1
4397	1	1
4538	1	1
4679	1	1
4820	1	1
4961	1	1
4993	1	1
5025	1	1
5057	1	1
5089	1	1
5230	1	1
5371	1	1
5512	1	1
5653	1	1
5685	1	1
5717	1	1
5749	1	1
5781	1	1
5895	1	1
6009	1	1
6123	1	1
6235	1	1
6347	1	1
6730	1	1
6731	1	1
6732	1	1
6733	1	1
6734	1	1
6735	1	1
6736	1	1
6737	1	1
6738	1	1
6739	1	1
6740	1	1
6741	1	1
6742	1	1
6743	1	1
6744	1	1
6745	1	1
6746	1	1
6747	1	1
6748	1	1
6749	1	1
6750	1	1
6751	1	1
6752	1	1
6753	1	1
6754	1	1
6755	1	1
6756	1	1
6757	1	1
6758	1	1
6759	1	1
6760	1	1
6761	1	1
6762	1	1
6763	1	1
6764	1	1
6765	1	1
6766	1	1
6767	1	1
6768	1	1
6769	1	1
6770	1	1
6771	1	1
6772	1	1
6773	1	1
6776	1	1
6780	1	1
6827	1	1
6829	1	1
6830	1	1
6832	1	1
6833	1	1
6835	1	1
6836	1	1
6838	1	1
6839	1	1
6841	1	1
6842	1	1
6844	1	1
6846	1	1
6848	1	1
6850	1	1
6852	1	1
6854	1	1
6856	1	1
6869	1	1
6886	1	1
6895	1	1
6904	1	1
6919	1	1
6921	1	1
6924	1	1
6931	1	1
6937	1	1
6943	1	1
6949	1	1
6955	1	1
6957	1	1
6959	1	1
6961	1	1
6963	1	1
6969	1	1
6975	1	1
6981	1	1
6987	1	1
6989	1	1
6991	1	1
6993	1	1
6995	1	1
7000	1	1
7005	1	1
7010	1	1
7015	1	1
7020	1	1
7038	1	1
7039	1	1
7040	1	1
7041	1	1
7042	1	1
7043	1	1
7044	1	1
7045	1	1
7046	1	1
7047	1	1
7048	1	1
7049	1	1
7050	1	1
7051	1	1
7052	1	1
7053	1	1
7054	1	1
7055	1	1
7056	1	1
7057	1	1
7058	1	1
7059	1	1
7060	1	1
7061	1	1
7062	1	1
7063	1	1
7064	1	1
7065	1	1
7066	1	1
7067	1	1
7068	1	1
7069	1	1
7070	1	1
7071	1	1
7072	1	1
7073	1	1
7074	1	1
7075	1	1
7076	1	1
7077	1	1
7078	1	1
7079	1	1
7080	1	1
7081	1	1
7086	1	1
7087	1	1
7089	1	1
7093	1	1
7097	1	1
7101	1	1
7105	1	1
7109	1	1
7112	1	1
7115	1	1
7118	1	1
7121	1	1
7124	1	1
7127	1	1
7130	1	1
7133	1	1
7136	1	1
7139	1	1
7142	1	1
7143	1	1
7144	1	1
7145	1	1
7146	1	1
7147	1	1
7148	1	1
7149	1	1
7153	1	1
7156	1	1
7159	1	1
7162	1	1
7165	1	1
7168	1	1
7171	1	1
7174	1	1
7177	1	1
7180	1	1
7183	1	1
7186	1	1
7189	1	1
7192	1	1
7195	1	1
7198	1	1
7201	1	1
7204	1	1
7207	1	1
7210	1	1
7213	1	1
7216	1	1
7219	1	1
7222	1	1
7225	1	1
7228	1	1
7242	1	1
7244	1	1
7245	1	1
7247	1	1
7250	1	1
7253	1	1
7256	1	1
7259	1	1
7262	1	1
7265	1	1
7268	1	1
7271	1	1
7274	1	1
7277	1	1
7280	1	1
7283	1	1
7286	1	1
7289	1	1
7292	1	1
7295	1	1
7298	1	1
7301	1	1
7304	1	1
7307	1	1
7310	1	1
7313	1	1
7316	1	1
7319	1	1
7322	1	1
7325	1	1
7328	1	1
7331	1	1
7334	1	1
7337	1	1
7340	1	1
7343	1	1
7346	1	1
7349	1	1
7352	1	1
7355	1	1
7370	1	1
7371	1	1

---

Cond Coverage for Instance : tb.dut.u_reg

	Total	Covered	Percent
Conditions	542	512	94.46
Logical	542	512	94.46
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-6846	92.57
6848-7242	100.00

---

Branch Coverage for Instance : tb.dut.u_reg

	Line No.	Total	Covered	Percent
Branches		87	87	100.00
TERNARY	6776	2	2	100.00
IF	73	3	3	100.00
CASE	7087	44	44	100.00
CASE	7245	38	38	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	6776	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T5
0	1	Covered	T6,T8,T292
0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	7087	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T5
addr_hit[1]	Covered	T1,T2,T5
addr_hit[2]	Covered	T1,T2,T5
addr_hit[3]	Covered	T1,T2,T5
addr_hit[4]	Covered	T1,T2,T5
addr_hit[5]	Covered	T1,T2,T5
addr_hit[6]	Covered	T1,T2,T5
addr_hit[7]	Covered	T1,T2,T5
addr_hit[8]	Covered	T1,T2,T5
addr_hit[9]	Covered	T1,T2,T5
addr_hit[10]	Covered	T1,T2,T5
addr_hit[11]	Covered	T1,T2,T5
addr_hit[12]	Covered	T1,T2,T5
addr_hit[13]	Covered	T1,T2,T5
addr_hit[14]	Covered	T1,T2,T5
addr_hit[15]	Covered	T1,T2,T5
addr_hit[16]	Covered	T1,T2,T5
addr_hit[17]	Covered	T1,T2,T5
addr_hit[18]	Covered	T1,T2,T5
addr_hit[19]	Covered	T1,T2,T5
addr_hit[20]	Covered	T1,T2,T5
addr_hit[21]	Covered	T1,T2,T5
addr_hit[22]	Covered	T1,T2,T5
addr_hit[23]	Covered	T1,T2,T5
addr_hit[24]	Covered	T1,T2,T5
addr_hit[25]	Covered	T1,T2,T5
addr_hit[26]	Covered	T1,T2,T5
addr_hit[27]	Covered	T1,T2,T5
addr_hit[28]	Covered	T1,T2,T5
addr_hit[29]	Covered	T1,T2,T5
addr_hit[30]	Covered	T1,T2,T5
addr_hit[31]	Covered	T1,T2,T5
addr_hit[32]	Covered	T1,T2,T5
addr_hit[33]	Covered	T1,T2,T5
addr_hit[34]	Covered	T1,T2,T5
addr_hit[35]	Covered	T1,T2,T5
addr_hit[36]	Covered	T1,T2,T5
addr_hit[37]	Covered	T1,T2,T5
addr_hit[38]	Covered	T1,T2,T5
addr_hit[39]	Covered	T1,T2,T5
addr_hit[40]	Covered	T1,T2,T5
addr_hit[41]	Covered	T1,T2,T5
addr_hit[42]	Covered	T1,T2,T5
default	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	7245	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[5]	Covered	T1,T2,T5
addr_hit[6]	Covered	T1,T2,T5
addr_hit[7]	Covered	T1,T2,T5
addr_hit[8]	Covered	T1,T2,T5
addr_hit[9]	Covered	T1,T2,T5
addr_hit[10]	Covered	T1,T2,T5
addr_hit[11]	Covered	T1,T2,T5
addr_hit[12]	Covered	T1,T2,T5
addr_hit[13]	Covered	T1,T2,T5
addr_hit[14]	Covered	T1,T2,T5
addr_hit[15]	Covered	T1,T2,T5
addr_hit[17]	Covered	T1,T2,T5
addr_hit[18]	Covered	T1,T2,T5
addr_hit[19]	Covered	T1,T2,T5
addr_hit[20]	Covered	T1,T2,T5
addr_hit[21]	Covered	T1,T2,T5
addr_hit[22]	Covered	T1,T2,T5
addr_hit[23]	Covered	T1,T2,T5
addr_hit[24]	Covered	T1,T2,T5
addr_hit[25]	Covered	T1,T2,T5
addr_hit[26]	Covered	T1,T2,T5
addr_hit[27]	Covered	T1,T2,T5
addr_hit[28]	Covered	T1,T2,T5
addr_hit[29]	Covered	T1,T2,T5
addr_hit[30]	Covered	T1,T2,T5
addr_hit[31]	Covered	T1,T2,T5
addr_hit[32]	Covered	T1,T2,T5
addr_hit[33]	Covered	T1,T2,T5
addr_hit[34]	Covered	T1,T2,T5
addr_hit[35]	Covered	T1,T2,T5
addr_hit[36]	Covered	T1,T2,T5
addr_hit[37]	Covered	T1,T2,T5
addr_hit[38]	Covered	T1,T2,T5
addr_hit[39]	Covered	T1,T2,T5
addr_hit[40]	Covered	T1,T2,T5
addr_hit[41]	Covered	T1,T2,T5
addr_hit[42]	Covered	T1,T2,T5
default	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_reg

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	1352205319	263612	0	0
reAfterRv	1352205319	263608	0	0
rePulse	1352205319	137080	0	0
wePulse	1352205319	126528	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	263612	0	0
T1	500852	407	0	0
T2	100133	73	0	0
T3	967042	856	0	0
T4	507152	903	0	0
T5	194417	27	0	0
T6	109305	1236	0	0
T7	143114	401	0	0
T22	97139	39	0	0
T23	21412	59	0	0
T24	193176	21	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	263608	0	0
T1	500852	407	0	0
T2	100133	73	0	0
T3	967042	856	0	0
T4	507152	903	0	0
T5	194417	27	0	0
T6	109305	1236	0	0
T7	143114	401	0	0
T22	97139	39	0	0
T23	21412	59	0	0
T24	193176	21	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	137080	0	0
T1	500852	193	0	0
T2	100133	35	0	0
T3	967042	411	0	0
T4	507152	439	0	0
T5	194417	5	0	0
T6	109305	840	0	0
T7	143114	178	0	0
T22	97139	20	0	0
T23	21412	43	0	0
T24	193176	11	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	1352205319	126528	0	0
T1	500852	214	0	0
T2	100133	38	0	0
T3	967042	445	0	0
T4	507152	464	0	0
T5	194417	22	0	0
T6	109305	396	0	0
T7	143114	223	0	0
T22	97139	19	0	0
T23	21412	16	0	0
T24	193176	10	0	0