Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
900 |
1 |
|
|
T22 |
13 |
|
T68 |
12 |
|
T69 |
10 |
| auto[1] |
880 |
1 |
|
|
T22 |
7 |
|
T68 |
8 |
|
T69 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T22 |
8 |
|
T68 |
11 |
|
T69 |
11 |
| auto[1] |
911 |
1 |
|
|
T22 |
12 |
|
T68 |
9 |
|
T69 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
886 |
1 |
|
|
T22 |
10 |
|
T68 |
8 |
|
T69 |
11 |
| auto[1] |
894 |
1 |
|
|
T22 |
10 |
|
T68 |
12 |
|
T69 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T22 |
7 |
|
T68 |
15 |
|
T69 |
11 |
| auto[1] |
893 |
1 |
|
|
T22 |
13 |
|
T68 |
5 |
|
T69 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T22 |
17 |
|
T68 |
13 |
|
T69 |
13 |
| auto[1] |
876 |
1 |
|
|
T22 |
3 |
|
T68 |
7 |
|
T69 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T22 |
11 |
|
T68 |
10 |
|
T69 |
7 |
| auto[1] |
891 |
1 |
|
|
T22 |
9 |
|
T68 |
10 |
|
T69 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T22 |
10 |
|
T68 |
12 |
|
T69 |
9 |
| auto[1] |
932 |
1 |
|
|
T22 |
10 |
|
T68 |
8 |
|
T69 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T22 |
9 |
|
T68 |
6 |
|
T69 |
10 |
| auto[1] |
897 |
1 |
|
|
T22 |
11 |
|
T68 |
14 |
|
T69 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T22 |
11 |
|
T68 |
11 |
|
T69 |
12 |
| auto[1] |
904 |
1 |
|
|
T22 |
9 |
|
T68 |
9 |
|
T69 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
896 |
1 |
|
|
T22 |
7 |
|
T68 |
10 |
|
T69 |
10 |
| auto[1] |
884 |
1 |
|
|
T22 |
13 |
|
T68 |
10 |
|
T69 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T22 |
8 |
|
T68 |
9 |
|
T69 |
12 |
| auto[1] |
881 |
1 |
|
|
T22 |
12 |
|
T68 |
11 |
|
T69 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T22 |
10 |
|
T68 |
11 |
|
T69 |
11 |
| auto[1] |
912 |
1 |
|
|
T22 |
10 |
|
T68 |
9 |
|
T69 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T22 |
11 |
|
T68 |
10 |
|
T69 |
11 |
| auto[1] |
874 |
1 |
|
|
T22 |
9 |
|
T68 |
10 |
|
T69 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
869 |
1 |
|
|
T22 |
8 |
|
T68 |
11 |
|
T69 |
11 |
| auto[1] |
911 |
1 |
|
|
T22 |
12 |
|
T68 |
9 |
|
T69 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T22 |
12 |
|
T68 |
9 |
|
T69 |
11 |
| auto[1] |
855 |
1 |
|
|
T22 |
8 |
|
T68 |
11 |
|
T69 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T22 |
13 |
|
T68 |
6 |
|
T69 |
11 |
| auto[1] |
898 |
1 |
|
|
T22 |
7 |
|
T68 |
14 |
|
T69 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T22 |
8 |
|
T68 |
17 |
|
T69 |
6 |
| auto[1] |
890 |
1 |
|
|
T22 |
12 |
|
T68 |
3 |
|
T69 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
921 |
1 |
|
|
T22 |
12 |
|
T68 |
12 |
|
T69 |
6 |
| auto[1] |
859 |
1 |
|
|
T22 |
8 |
|
T68 |
8 |
|
T69 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T22 |
16 |
|
T68 |
14 |
|
T69 |
9 |
| auto[1] |
881 |
1 |
|
|
T22 |
4 |
|
T68 |
6 |
|
T69 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T22 |
11 |
|
T68 |
10 |
|
T69 |
10 |
| auto[1] |
866 |
1 |
|
|
T22 |
9 |
|
T68 |
10 |
|
T69 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
900 |
1 |
|
|
T22 |
8 |
|
T68 |
15 |
|
T69 |
11 |
| auto[1] |
880 |
1 |
|
|
T22 |
12 |
|
T68 |
5 |
|
T69 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T22 |
8 |
|
T68 |
9 |
|
T69 |
11 |
| auto[1] |
870 |
1 |
|
|
T22 |
12 |
|
T68 |
11 |
|
T69 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T22 |
9 |
|
T68 |
6 |
|
T69 |
7 |
| auto[1] |
901 |
1 |
|
|
T22 |
11 |
|
T68 |
14 |
|
T69 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T22 |
10 |
|
T68 |
11 |
|
T69 |
11 |
| auto[1] |
912 |
1 |
|
|
T22 |
10 |
|
T68 |
9 |
|
T69 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
463 |
1 |
|
|
T22 |
4 |
|
T68 |
2 |
|
T69 |
6 |
| auto[0] |
auto[1] |
462 |
1 |
|
|
T22 |
8 |
|
T68 |
7 |
|
T69 |
5 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T22 |
6 |
|
T68 |
6 |
|
T69 |
5 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T22 |
2 |
|
T68 |
5 |
|
T69 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T22 |
3 |
|
T68 |
4 |
|
T69 |
6 |
| auto[0] |
auto[1] |
440 |
1 |
|
|
T22 |
10 |
|
T68 |
2 |
|
T69 |
5 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T22 |
4 |
|
T68 |
11 |
|
T69 |
5 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T22 |
3 |
|
T68 |
3 |
|
T69 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
452 |
1 |
|
|
T22 |
7 |
|
T68 |
10 |
|
T69 |
5 |
| auto[0] |
auto[1] |
438 |
1 |
|
|
T22 |
1 |
|
T68 |
7 |
|
T69 |
1 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T22 |
10 |
|
T68 |
3 |
|
T69 |
8 |
| auto[1] |
auto[1] |
438 |
1 |
|
|
T22 |
2 |
|
T69 |
6 |
|
T63 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
460 |
1 |
|
|
T22 |
6 |
|
T68 |
6 |
|
T69 |
2 |
| auto[0] |
auto[1] |
461 |
1 |
|
|
T22 |
6 |
|
T68 |
6 |
|
T69 |
4 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T22 |
5 |
|
T68 |
4 |
|
T69 |
5 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T22 |
3 |
|
T68 |
4 |
|
T69 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
414 |
1 |
|
|
T22 |
8 |
|
T68 |
8 |
|
T69 |
3 |
| auto[0] |
auto[1] |
485 |
1 |
|
|
T22 |
8 |
|
T68 |
6 |
|
T69 |
6 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T22 |
2 |
|
T68 |
4 |
|
T69 |
6 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T22 |
2 |
|
T68 |
2 |
|
T69 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T22 |
5 |
|
T68 |
3 |
|
T69 |
4 |
| auto[0] |
auto[1] |
475 |
1 |
|
|
T22 |
6 |
|
T68 |
7 |
|
T69 |
6 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T22 |
4 |
|
T68 |
3 |
|
T69 |
6 |
| auto[1] |
auto[1] |
422 |
1 |
|
|
T22 |
5 |
|
T68 |
7 |
|
T69 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
461 |
1 |
|
|
T22 |
4 |
|
T68 |
3 |
|
T69 |
7 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T22 |
4 |
|
T68 |
6 |
|
T69 |
4 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T22 |
3 |
|
T68 |
7 |
|
T69 |
3 |
| auto[1] |
auto[1] |
435 |
1 |
|
|
T22 |
9 |
|
T68 |
4 |
|
T69 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T22 |
5 |
|
T68 |
1 |
|
T69 |
6 |
| auto[0] |
auto[1] |
432 |
1 |
|
|
T22 |
4 |
|
T68 |
5 |
|
T69 |
1 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T22 |
3 |
|
T68 |
8 |
|
T69 |
6 |
| auto[1] |
auto[1] |
449 |
1 |
|
|
T22 |
8 |
|
T68 |
6 |
|
T69 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
455 |
1 |
|
|
T22 |
6 |
|
T68 |
5 |
|
T69 |
7 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T22 |
5 |
|
T68 |
5 |
|
T69 |
4 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T22 |
7 |
|
T68 |
7 |
|
T69 |
3 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T22 |
2 |
|
T68 |
3 |
|
T69 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
869 |
1 |
|
|
T22 |
8 |
|
T68 |
11 |
|
T69 |
11 |
| auto[1] |
auto[1] |
911 |
1 |
|
|
T22 |
12 |
|
T68 |
9 |
|
T69 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T22 |
3 |
|
T68 |
7 |
|
T69 |
7 |
| auto[0] |
auto[1] |
471 |
1 |
|
|
T22 |
5 |
|
T68 |
8 |
|
T69 |
4 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T22 |
8 |
|
T68 |
4 |
|
T69 |
5 |
| auto[1] |
auto[1] |
433 |
1 |
|
|
T22 |
4 |
|
T68 |
1 |
|
T69 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
868 |
1 |
|
|
T22 |
10 |
|
T68 |
11 |
|
T69 |
11 |
| auto[1] |
auto[1] |
912 |
1 |
|
|
T22 |
10 |
|
T68 |
9 |
|
T69 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T50 |
12 |
|
T212 |
12 |
|
T190 |
9 |
| auto[1] |
117 |
1 |
|
|
T50 |
8 |
|
T212 |
8 |
|
T190 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T50 |
9 |
|
T212 |
10 |
|
T190 |
7 |
| auto[1] |
121 |
1 |
|
|
T50 |
11 |
|
T212 |
10 |
|
T190 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
123 |
1 |
|
|
T50 |
10 |
|
T212 |
10 |
|
T190 |
10 |
| auto[1] |
117 |
1 |
|
|
T50 |
10 |
|
T212 |
10 |
|
T190 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T50 |
10 |
|
T212 |
14 |
|
T190 |
9 |
| auto[1] |
121 |
1 |
|
|
T50 |
10 |
|
T212 |
6 |
|
T190 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T50 |
7 |
|
T212 |
12 |
|
T190 |
8 |
| auto[1] |
129 |
1 |
|
|
T50 |
13 |
|
T212 |
8 |
|
T190 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
113 |
1 |
|
|
T50 |
11 |
|
T212 |
7 |
|
T190 |
8 |
| auto[1] |
127 |
1 |
|
|
T50 |
9 |
|
T212 |
13 |
|
T190 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T50 |
11 |
|
T212 |
8 |
|
T190 |
11 |
| auto[1] |
114 |
1 |
|
|
T50 |
9 |
|
T212 |
12 |
|
T190 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T50 |
13 |
|
T212 |
10 |
|
T190 |
7 |
| auto[1] |
122 |
1 |
|
|
T50 |
7 |
|
T212 |
10 |
|
T190 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T50 |
9 |
|
T212 |
12 |
|
T190 |
14 |
| auto[1] |
111 |
1 |
|
|
T50 |
11 |
|
T212 |
8 |
|
T190 |
6 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T50 |
7 |
|
T212 |
12 |
|
T190 |
6 |
| auto[1] |
129 |
1 |
|
|
T50 |
13 |
|
T212 |
8 |
|
T190 |
14 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
117 |
1 |
|
|
T50 |
10 |
|
T212 |
9 |
|
T190 |
10 |
| auto[1] |
123 |
1 |
|
|
T50 |
10 |
|
T212 |
11 |
|
T190 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T50 |
9 |
|
T212 |
9 |
|
T190 |
13 |
| auto[1] |
106 |
1 |
|
|
T50 |
11 |
|
T212 |
11 |
|
T190 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T50 |
6 |
|
T212 |
12 |
|
T190 |
6 |
| auto[1] |
124 |
1 |
|
|
T50 |
14 |
|
T212 |
8 |
|
T190 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
119 |
1 |
|
|
T50 |
9 |
|
T212 |
10 |
|
T190 |
7 |
| auto[1] |
121 |
1 |
|
|
T50 |
11 |
|
T212 |
10 |
|
T190 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T50 |
8 |
|
T212 |
13 |
|
T190 |
10 |
| auto[1] |
129 |
1 |
|
|
T50 |
12 |
|
T212 |
7 |
|
T190 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T50 |
12 |
|
T212 |
7 |
|
T190 |
11 |
| auto[1] |
125 |
1 |
|
|
T50 |
8 |
|
T212 |
13 |
|
T190 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T50 |
12 |
|
T212 |
8 |
|
T190 |
9 |
| auto[1] |
119 |
1 |
|
|
T50 |
8 |
|
T212 |
12 |
|
T190 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T50 |
12 |
|
T212 |
13 |
|
T190 |
11 |
| auto[1] |
113 |
1 |
|
|
T50 |
8 |
|
T212 |
7 |
|
T190 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T50 |
9 |
|
T212 |
14 |
|
T190 |
10 |
| auto[1] |
98 |
1 |
|
|
T50 |
11 |
|
T212 |
6 |
|
T190 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
112 |
1 |
|
|
T50 |
9 |
|
T212 |
8 |
|
T190 |
10 |
| auto[1] |
128 |
1 |
|
|
T50 |
11 |
|
T212 |
12 |
|
T190 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
115 |
1 |
|
|
T50 |
13 |
|
T212 |
12 |
|
T190 |
6 |
| auto[1] |
125 |
1 |
|
|
T50 |
7 |
|
T212 |
8 |
|
T190 |
14 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T50 |
12 |
|
T212 |
15 |
|
T190 |
12 |
| auto[1] |
114 |
1 |
|
|
T50 |
8 |
|
T212 |
5 |
|
T190 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T50 |
7 |
|
T212 |
8 |
|
T190 |
8 |
| auto[1] |
114 |
1 |
|
|
T50 |
13 |
|
T212 |
12 |
|
T190 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T50 |
9 |
|
T212 |
9 |
|
T190 |
13 |
| auto[1] |
106 |
1 |
|
|
T50 |
11 |
|
T212 |
11 |
|
T190 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T50 |
3 |
|
T212 |
7 |
|
T190 |
4 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T50 |
5 |
|
T212 |
6 |
|
T190 |
6 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T50 |
7 |
|
T212 |
3 |
|
T190 |
6 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T50 |
5 |
|
T212 |
4 |
|
T190 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
51 |
1 |
|
|
T50 |
5 |
|
T212 |
6 |
|
T190 |
4 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T50 |
7 |
|
T212 |
1 |
|
T190 |
7 |
| auto[1] |
auto[0] |
68 |
1 |
|
|
T50 |
5 |
|
T212 |
8 |
|
T190 |
5 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T50 |
3 |
|
T212 |
5 |
|
T190 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
52 |
1 |
|
|
T50 |
4 |
|
T212 |
4 |
|
T190 |
4 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T50 |
8 |
|
T212 |
4 |
|
T190 |
5 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T50 |
3 |
|
T212 |
8 |
|
T190 |
4 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T50 |
5 |
|
T212 |
4 |
|
T190 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T50 |
6 |
|
T212 |
4 |
|
T190 |
5 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T50 |
6 |
|
T212 |
9 |
|
T190 |
6 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T50 |
5 |
|
T212 |
3 |
|
T190 |
3 |
| auto[1] |
auto[1] |
56 |
1 |
|
|
T50 |
3 |
|
T212 |
4 |
|
T190 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T50 |
5 |
|
T212 |
6 |
|
T190 |
3 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T50 |
4 |
|
T212 |
8 |
|
T190 |
7 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T50 |
6 |
|
T212 |
2 |
|
T190 |
8 |
| auto[1] |
auto[1] |
38 |
1 |
|
|
T50 |
5 |
|
T212 |
4 |
|
T190 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
47 |
1 |
|
|
T50 |
6 |
|
T212 |
4 |
|
T190 |
1 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T50 |
3 |
|
T212 |
4 |
|
T190 |
9 |
| auto[1] |
auto[0] |
71 |
1 |
|
|
T50 |
7 |
|
T212 |
6 |
|
T190 |
6 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T50 |
4 |
|
T212 |
6 |
|
T190 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
54 |
1 |
|
|
T50 |
5 |
|
T212 |
10 |
|
T190 |
3 |
| auto[0] |
auto[1] |
72 |
1 |
|
|
T50 |
7 |
|
T212 |
5 |
|
T190 |
9 |
| auto[1] |
auto[0] |
57 |
1 |
|
|
T50 |
2 |
|
T212 |
2 |
|
T190 |
3 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T50 |
6 |
|
T212 |
3 |
|
T190 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
57 |
1 |
|
|
T50 |
4 |
|
T212 |
5 |
|
T190 |
3 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T50 |
3 |
|
T212 |
3 |
|
T190 |
5 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T50 |
6 |
|
T212 |
4 |
|
T190 |
7 |
| auto[1] |
auto[1] |
54 |
1 |
|
|
T50 |
7 |
|
T212 |
8 |
|
T190 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T50 |
3 |
|
T212 |
9 |
|
T190 |
2 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T50 |
3 |
|
T212 |
3 |
|
T190 |
4 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T50 |
9 |
|
T212 |
3 |
|
T190 |
7 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T50 |
5 |
|
T212 |
5 |
|
T190 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
119 |
1 |
|
|
T50 |
9 |
|
T212 |
10 |
|
T190 |
7 |
| auto[1] |
auto[1] |
121 |
1 |
|
|
T50 |
11 |
|
T212 |
10 |
|
T190 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T50 |
7 |
|
T212 |
7 |
|
T190 |
5 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T50 |
6 |
|
T212 |
5 |
|
T190 |
1 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T50 |
2 |
|
T212 |
5 |
|
T190 |
9 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T50 |
5 |
|
T212 |
3 |
|
T190 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
134 |
1 |
|
|
T50 |
9 |
|
T212 |
9 |
|
T190 |
13 |
| auto[1] |
auto[1] |
106 |
1 |
|
|
T50 |
11 |
|
T212 |
11 |
|
T190 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T50 |
8 |
|
T117 |
12 |
|
T229 |
10 |
| auto[1] |
30 |
1 |
|
|
T50 |
12 |
|
T117 |
8 |
|
T229 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
35 |
1 |
|
|
T50 |
14 |
|
T117 |
11 |
|
T229 |
10 |
| auto[1] |
25 |
1 |
|
|
T50 |
6 |
|
T117 |
9 |
|
T229 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T50 |
11 |
|
T117 |
11 |
|
T229 |
9 |
| auto[1] |
29 |
1 |
|
|
T50 |
9 |
|
T117 |
9 |
|
T229 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T50 |
9 |
|
T117 |
12 |
|
T229 |
8 |
| auto[1] |
31 |
1 |
|
|
T50 |
11 |
|
T117 |
8 |
|
T229 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
34 |
1 |
|
|
T50 |
10 |
|
T117 |
10 |
|
T229 |
14 |
| auto[1] |
26 |
1 |
|
|
T50 |
10 |
|
T117 |
10 |
|
T229 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
32 |
1 |
|
|
T50 |
8 |
|
T117 |
9 |
|
T229 |
15 |
| auto[1] |
28 |
1 |
|
|
T50 |
12 |
|
T117 |
11 |
|
T229 |
5 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
23 |
1 |
|
|
T50 |
8 |
|
T117 |
7 |
|
T229 |
8 |
| auto[1] |
37 |
1 |
|
|
T50 |
12 |
|
T117 |
13 |
|
T229 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T50 |
8 |
|
T117 |
11 |
|
T229 |
11 |
| auto[1] |
30 |
1 |
|
|
T50 |
12 |
|
T117 |
9 |
|
T229 |
9 |