Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 98.96 96.38 100.00 97.44 98.33 99.81 94.03


Total tests in report: 913
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.73 52.73 72.69 72.69 66.20 66.20 86.56 86.56 0.00 0.00 76.12 76.12 54.68 54.68 12.88 12.88 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3924138844
67.35 14.62 72.69 0.00 67.06 0.86 87.02 0.46 97.44 97.44 76.16 0.03 56.27 1.59 14.85 1.97 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2120710694
78.48 11.13 88.30 15.61 79.76 12.71 95.44 8.43 97.44 0.00 88.55 12.39 75.94 19.66 23.94 9.09 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.4127048591
84.28 5.80 91.77 3.47 83.46 3.69 95.67 0.23 97.44 0.00 91.16 2.61 82.96 7.02 47.51 23.57 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.162907321
87.81 3.53 95.12 3.35 86.67 3.22 95.67 0.00 97.44 0.00 94.15 2.99 91.01 8.05 54.62 7.11 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.1251393868
89.29 1.48 95.62 0.50 88.82 2.15 96.92 1.25 97.44 0.00 94.99 0.84 91.95 0.94 59.29 4.67 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1066214947
90.76 1.47 95.62 0.00 92.06 3.24 96.92 0.00 97.44 0.00 94.99 0.00 92.70 0.75 65.58 6.28 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1052350876
92.15 1.39 95.66 0.03 92.09 0.02 96.92 0.00 97.44 0.00 95.02 0.03 92.79 0.09 75.13 9.55 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3800863460
92.95 0.80 96.39 0.73 92.59 0.50 98.06 1.14 97.44 0.00 95.54 0.52 94.48 1.69 76.17 1.04 /workspace/coverage/default/47.sysrst_ctrl_stress_all.658823025
93.52 0.56 96.70 0.31 93.09 0.50 98.06 0.00 97.44 0.00 95.68 0.14 95.13 0.66 78.50 2.34 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3338401652
94.01 0.50 96.98 0.28 93.85 0.76 98.06 0.00 97.44 0.00 96.24 0.56 97.00 1.87 78.50 0.00 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.1226505704
94.36 0.35 97.05 0.07 94.06 0.21 98.29 0.23 97.44 0.00 96.31 0.07 97.00 0.00 80.37 1.87 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.4034608201
94.70 0.34 97.05 0.00 94.09 0.02 98.29 0.00 97.44 0.00 96.31 0.00 97.00 0.00 82.71 2.34 /workspace/coverage/default/5.sysrst_ctrl_stress_all.3552266029
95.02 0.33 97.48 0.43 94.42 0.33 98.29 0.00 97.44 0.00 96.69 0.38 98.03 1.03 82.81 0.10 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1030629314
95.29 0.26 97.55 0.07 94.59 0.17 98.29 0.00 97.44 0.00 96.80 0.10 98.03 0.00 84.32 1.51 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.185886089
95.53 0.25 98.09 0.54 95.11 0.52 98.29 0.00 97.44 0.00 97.46 0.66 98.03 0.00 84.32 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2126564543
95.77 0.24 98.32 0.23 95.23 0.12 98.86 0.57 97.44 0.00 97.49 0.03 98.22 0.19 84.84 0.52 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2337467753
95.99 0.22 98.32 0.00 95.33 0.10 98.86 0.00 97.44 0.00 97.49 0.00 98.22 0.00 86.29 1.45 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1906441588
96.20 0.21 98.33 0.02 95.33 0.00 98.86 0.00 97.44 0.00 97.53 0.03 98.22 0.00 87.69 1.40 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3971192561
96.40 0.20 98.33 0.00 95.35 0.02 100.00 1.14 97.44 0.00 97.56 0.03 98.31 0.09 87.80 0.10 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.3528522954
96.56 0.16 98.33 0.00 95.35 0.00 100.00 0.00 97.44 0.00 97.56 0.00 98.31 0.00 88.94 1.14 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3017110182
96.69 0.13 98.42 0.09 95.49 0.14 100.00 0.00 97.44 0.00 97.70 0.14 98.60 0.28 89.20 0.26 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.640764268
96.79 0.10 98.42 0.00 95.52 0.02 100.00 0.00 97.44 0.00 97.70 0.00 98.60 0.00 89.88 0.67 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.967710649
96.89 0.09 98.47 0.05 95.54 0.02 100.00 0.00 97.44 0.00 97.77 0.07 98.69 0.09 90.29 0.42 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1176478704
96.97 0.09 98.59 0.12 95.61 0.07 100.00 0.00 97.44 0.00 97.91 0.14 98.97 0.28 90.29 0.00 /workspace/coverage/default/42.sysrst_ctrl_stress_all.2124714916
97.04 0.07 98.59 0.00 95.61 0.00 100.00 0.00 97.44 0.00 97.91 0.00 98.97 0.00 90.76 0.47 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3890651507
97.10 0.06 98.63 0.03 95.69 0.07 100.00 0.00 97.44 0.00 97.91 0.00 98.97 0.00 91.07 0.31 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.756977829
97.16 0.06 98.70 0.07 95.76 0.07 100.00 0.00 97.44 0.00 97.98 0.07 99.16 0.19 91.07 0.00 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.4014384924
97.21 0.05 98.70 0.00 95.76 0.00 100.00 0.00 97.44 0.00 97.98 0.00 99.16 0.00 91.43 0.36 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1174196823
97.26 0.05 98.73 0.03 95.78 0.02 100.00 0.00 97.44 0.00 98.02 0.03 99.25 0.09 91.59 0.16 /workspace/coverage/default/19.sysrst_ctrl_stress_all.904230534
97.30 0.05 98.77 0.03 95.85 0.07 100.00 0.00 97.44 0.00 98.05 0.03 99.44 0.19 91.59 0.00 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2643477797
97.35 0.04 98.77 0.00 95.85 0.00 100.00 0.00 97.44 0.00 98.05 0.00 99.44 0.00 91.90 0.31 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.3724947570
97.38 0.03 98.80 0.03 95.88 0.02 100.00 0.00 97.44 0.00 98.09 0.03 99.53 0.09 91.95 0.05 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2287212132
97.42 0.03 98.80 0.00 96.11 0.24 100.00 0.00 97.44 0.00 98.09 0.00 99.53 0.00 91.95 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2243121948
97.45 0.03 98.80 0.00 96.11 0.00 100.00 0.00 97.44 0.00 98.09 0.00 99.53 0.00 92.16 0.21 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1018300954
97.48 0.03 98.80 0.00 96.11 0.00 100.00 0.00 97.44 0.00 98.09 0.00 99.53 0.00 92.37 0.21 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.4078623138
97.50 0.03 98.84 0.03 96.14 0.02 100.00 0.00 97.44 0.00 98.12 0.03 99.63 0.09 92.37 0.00 /workspace/coverage/default/22.sysrst_ctrl_edge_detect.1988085207
97.53 0.03 98.87 0.03 96.16 0.02 100.00 0.00 97.44 0.00 98.16 0.03 99.72 0.09 92.37 0.00 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.410322877
97.56 0.03 98.87 0.00 96.19 0.02 100.00 0.00 97.44 0.00 98.16 0.00 99.72 0.00 92.52 0.16 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.713209017
97.58 0.02 98.87 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.16 0.00 99.72 0.00 92.68 0.16 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3559584662
97.60 0.02 98.87 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.16 0.00 99.72 0.00 92.83 0.16 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3750838772
97.62 0.01 98.91 0.03 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.07 99.72 0.00 92.83 0.00 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1448327841
97.63 0.01 98.91 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 92.94 0.10 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1378441477
97.64 0.01 98.91 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 93.04 0.10 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.988151080
97.66 0.01 98.91 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 93.15 0.10 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.1122753324
97.67 0.01 98.91 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 93.25 0.10 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3830533630
97.69 0.01 98.91 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 93.35 0.10 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1838282007
97.70 0.01 98.91 0.00 96.19 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.81 0.09 93.35 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1781610369
97.71 0.01 98.91 0.00 96.21 0.02 100.00 0.00 97.44 0.00 98.22 0.00 99.81 0.00 93.41 0.05 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1112656866
97.72 0.01 98.92 0.02 96.21 0.00 100.00 0.00 97.44 0.00 98.26 0.03 99.81 0.00 93.41 0.00 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3998482609
97.73 0.01 98.94 0.02 96.21 0.00 100.00 0.00 97.44 0.00 98.29 0.03 99.81 0.00 93.41 0.00 /workspace/coverage/default/29.sysrst_ctrl_stress_all.858609920
97.74 0.01 98.96 0.02 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.03 99.81 0.00 93.41 0.00 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.2205527423
97.74 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.46 0.05 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2024468057
97.75 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.51 0.05 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.2284161403
97.76 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.56 0.05 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3676229150
97.77 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.61 0.05 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2383017035
97.77 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.67 0.05 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3957397102
97.78 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.72 0.05 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3666735601
97.79 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.77 0.05 /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.419570408
97.80 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.82 0.05 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.1327060801
97.80 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.87 0.05 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3601888111
97.81 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.93 0.05 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.744819368
97.82 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 93.98 0.05 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3857653812
97.82 0.01 98.96 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 94.03 0.05 /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1072790136
97.83 0.01 98.96 0.00 96.26 0.05 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 94.03 0.00 /workspace/coverage/default/0.sysrst_ctrl_alert_test.336255183
97.84 0.01 98.96 0.00 96.28 0.02 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 94.03 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2151820785
97.84 0.01 98.96 0.00 96.31 0.02 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 94.03 0.00 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2023366638
97.84 0.01 98.96 0.00 96.33 0.02 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 94.03 0.00 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.437743052
97.85 0.01 98.96 0.00 96.35 0.02 100.00 0.00 97.44 0.00 98.33 0.00 99.81 0.00 94.03 0.00 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1108549399

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2511924631
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3608337072
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.4254709568
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2095330020
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2087199591
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1876345393
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3898628259
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2782851432
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3694804211
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4221029459
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.705086007
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2812394866
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2100667077
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1748518703
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2810907870
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1295389888
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.4215001655
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3646414650
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3861425061
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1557354531
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2025955922
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.612510720
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2687089925
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3090661701
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.687195535
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3554299925
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.2355239143
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1247956461
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1898975050
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.4048602577
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.114742694
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.4110142434
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1722199555
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.654942657
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.427211131
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2390756890
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3205321400
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1769240916
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2177632622
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2461158877
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2610058790
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1706655571
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2293933786
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2200363381
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.504051928
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965742550
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3319516914
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.689006135
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3789924955
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3826555458
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1962114433
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2924696991
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2243035502
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2434940633
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.863660269
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3719247085
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3123516008
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.3538058514
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3121633282
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1176457551
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1372840379
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2812370536
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2218373601
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.140820222
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.945419578
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1569073315
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3976481013
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2343290688
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1137025015
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3527867549
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3996257324
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2253506822
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2989498817
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2133650607
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3629529193
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3361683896
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1719035935
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1352689860
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/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3602836727
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2428568211
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.782815284
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.1616364030
/workspace/coverage/default/41.sysrst_ctrl_smoke.4047695327
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2391650682
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1698777022
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2145578933
/workspace/coverage/default/42.sysrst_ctrl_alert_test.543796602
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1057559099
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2583216953
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3940707792
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.4267467601
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2105269766
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2778336591
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1177577017
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1181306716
/workspace/coverage/default/42.sysrst_ctrl_smoke.2982426402
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.371074228
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2303093715
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1437384216
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1418196683
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3788938192
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3806831524
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.2274455855
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3846687610
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3653917290
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1124873964
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2916861009
/workspace/coverage/default/43.sysrst_ctrl_smoke.1340286718
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3907662725
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2214239696
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3629167694
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3994826788
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2905686972
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1707953708
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.808351676
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1667016325
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3068671884
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.3063111546
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2319992168
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1142639185
/workspace/coverage/default/44.sysrst_ctrl_smoke.290959366
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3368454045
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2642653495
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3538394608
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2977519020
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.908559453
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3852821516
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.4156203066
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.4404849
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3634599147
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3885046186
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3746306864
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1193438686
/workspace/coverage/default/45.sysrst_ctrl_smoke.3941385390
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1742899575
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2197542108
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3698774569
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1457351751
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3709367435
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1133050556
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3201225913
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2284504906
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.285487814
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1299993816
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2074041838
/workspace/coverage/default/46.sysrst_ctrl_smoke.3232548829
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3226791223
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1550885585
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1941917507
/workspace/coverage/default/47.sysrst_ctrl_alert_test.1442333545
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.552560323
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.501126229
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.4138000981
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.4267139683
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1157480235
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2573120267
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1499332653
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4092287486
/workspace/coverage/default/47.sysrst_ctrl_smoke.834931238
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3504287620
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1248820331
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2522222876
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2209234750
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2307797544
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1867142528
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.365537829
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.976864856
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.1268897320
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1648087862
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3624977209
/workspace/coverage/default/48.sysrst_ctrl_smoke.1336176731
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2118608980
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2870820705
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1641295720
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2427360447
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3512450531
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3253483068
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3435241756
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2942701155
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1008875388
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.149264519
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.524184528
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3792558516
/workspace/coverage/default/49.sysrst_ctrl_smoke.3806215817
/workspace/coverage/default/49.sysrst_ctrl_stress_all.3216197778
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2987031317
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1131529546
/workspace/coverage/default/5.sysrst_ctrl_alert_test.640086760
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2555044580
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1376575012
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3083872429
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1270443298
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3901150501
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1321637698
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.735230045
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1809057008
/workspace/coverage/default/5.sysrst_ctrl_smoke.3817253869
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3228711568
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2815797263
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1596750391
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3980824265
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3505042327
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3150235840
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1117592377
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.298322347
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.4074646669
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3029548070
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3340719342
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2578962975
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1313612853
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2520533257
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3724049008
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.241027438
/workspace/coverage/default/6.sysrst_ctrl_smoke.2191793968
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1269373731
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.730954889
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.258657947
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1492855063
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2479213397
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.130587630
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2484695330
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1338706226
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3363618032
/workspace/coverage/default/7.sysrst_ctrl_alert_test.4264622982
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.764116106
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.615676920
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.54719113
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.656263798
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.3713070477
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.364994008
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3894066864
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2532309087
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2151722952
/workspace/coverage/default/7.sysrst_ctrl_smoke.3103899495
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2029909550
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3202732033
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2321658870
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.755000151
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3972756179
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2943883528
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1664230321
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.109475104
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3306144667
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2488954549
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2314519753
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.36080192
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3619742594
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1349006175
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3075596592
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3371495132
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1605103752
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2484646331
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3151802562
/workspace/coverage/default/8.sysrst_ctrl_smoke.2399374699
/workspace/coverage/default/8.sysrst_ctrl_stress_all.1770254123
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.2965304669
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3199210271
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1072234235
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2828199228
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.813965166
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3414131722
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2312452404
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1371479088
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.92986267
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.953491654
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4280205295
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2890207258
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.99821014
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3071438750
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3648802940
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3456339327
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1790438736
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.208896506
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1989718935
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1340889023
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.353100898
/workspace/coverage/default/9.sysrst_ctrl_smoke.3371570266
/workspace/coverage/default/9.sysrst_ctrl_stress_all.4172244836
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3007305858
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2672358742
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.579767463
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1577394378
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1215619172
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3089890594
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.476955696
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.611661192
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1100270814



Total test records in report: 913
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T5 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2120710694 Dec 24 01:01:48 PM PST 23 Dec 24 01:01:59 PM PST 23 2257957373 ps
T6 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.4114055645 Dec 24 01:01:48 PM PST 23 Dec 24 01:01:58 PM PST 23 2038421667 ps
T7 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.4243028527 Dec 24 01:01:58 PM PST 23 Dec 24 01:02:12 PM PST 23 2010113533 ps
T39 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1748518703 Dec 24 01:01:46 PM PST 23 Dec 24 01:01:53 PM PST 23 2057612738 ps
T1 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3924138844 Dec 24 01:01:44 PM PST 23 Dec 24 01:02:04 PM PST 23 22419226639 ps
T24 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2025955922 Dec 24 01:01:51 PM PST 23 Dec 24 01:02:03 PM PST 23 2146757183 ps
T2 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3205321400 Dec 24 01:01:48 PM PST 23 Dec 24 01:01:58 PM PST 23 5608541190 ps
T25 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2661826218 Dec 24 01:01:59 PM PST 23 Dec 24 01:02:12 PM PST 23 2014408146 ps
T3 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.330367943 Dec 24 01:01:44 PM PST 23 Dec 24 01:01:51 PM PST 23 2066878416 ps
T26 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1368667768 Dec 24 01:01:59 PM PST 23 Dec 24 01:02:10 PM PST 23 2018248690 ps
T4 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.863660269 Dec 24 01:01:58 PM PST 23 Dec 24 01:02:35 PM PST 23 10456482345 ps
T27 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2924696991 Dec 24 01:01:49 PM PST 23 Dec 24 01:01:59 PM PST 23 2080806925 ps
T8 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1623546057 Dec 24 01:01:37 PM PST 23 Dec 24 01:01:44 PM PST 23 2042526346 ps
T9 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.504051928 Dec 24 01:01:49 PM PST 23 Dec 24 01:02:31 PM PST 23 22301458824 ps
T10 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2486919392 Dec 24 01:01:46 PM PST 23 Dec 24 01:02:08 PM PST 23 22263718880 ps
T53 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1052350876 Dec 24 01:01:43 PM PST 23 Dec 24 01:02:52 PM PST 23 14048616344 ps
T316 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.4034608201 Dec 24 01:01:50 PM PST 23 Dec 24 01:01:59 PM PST 23 2147769512 ps
T11 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3123516008 Dec 24 01:01:48 PM PST 23 Dec 24 01:02:16 PM PST 23 42624564161 ps
T301 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.265463366 Dec 24 01:01:40 PM PST 23 Dec 24 01:01:45 PM PST 23 2286103457 ps
T12 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1295389888 Dec 24 01:01:39 PM PST 23 Dec 24 01:02:37 PM PST 23 22160364059 ps
T319 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1730311758 Dec 24 01:01:58 PM PST 23 Dec 24 01:02:08 PM PST 23 2040496099 ps
T13 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1446941680 Dec 24 01:01:47 PM PST 23 Dec 24 01:01:56 PM PST 23 2078660333 ps
T33 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1906441588 Dec 24 01:01:48 PM PST 23 Dec 24 01:02:11 PM PST 23 22417929811 ps
T34 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3789924955 Dec 24 01:01:48 PM PST 23 Dec 24 01:02:00 PM PST 23 4753813990 ps
T387 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.4180067495 Dec 24 01:01:46 PM PST 23 Dec 24 01:01:58 PM PST 23 2010090240 ps
T388 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3637028904 Dec 24 01:01:41 PM PST 23 Dec 24 01:01:46 PM PST 23 2031655562 ps
T35 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2177632622 Dec 24 01:01:45 PM PST 23 Dec 24 01:02:50 PM PST 23 42594956574 ps
T307 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1722199555 Dec 24 01:01:49 PM PST 23 Dec 24 01:03:52 PM PST 23 42444022347 ps
T317 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.2624411215 Dec 24 01:01:54 PM PST 23 Dec 24 01:02:10 PM PST 23 2015196452 ps
T322 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2483437694 Dec 24 01:02:05 PM PST 23 Dec 24 01:02:12 PM PST 23 6066680314 ps
T323 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3608337072 Dec 24 01:01:41 PM PST 23 Dec 24 01:02:18 PM PST 23 38749566766 ps
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