Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_key_intr_status_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_key_intr_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_key_intr_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present_h2l 2 0 2 100.00 100 1 1 2
cp_ac_present_l2h 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_h2l 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_l2h 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_h2l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_l2h 2 0 2 100.00 100 1 1 2
cp_key0_in_h2l 2 0 2 100.00 100 1 1 2
cp_key0_in_l2h 2 0 2 100.00 100 1 1 2
cp_key1_in_h2l 2 0 2 100.00 100 1 1 2
cp_key1_in_l2h 2 0 2 100.00 100 1 1 2
cp_key2_in_h2l 2 0 2 100.00 100 1 1 2
cp_key2_in_l2h 2 0 2 100.00 100 1 1 2
cp_pwrb_h2l 2 0 2 100.00 100 1 1 2
cp_pwrb_l2h 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1184 1 T6 1 T7 1 T25 1
auto[1] 105 1 T16 3 T17 2 T18 1



Summary for Variable cp_ac_present_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1127 1 T6 1 T7 1 T25 1
auto[1] 162 1 T16 1 T18 3 T45 5



Summary for Variable cp_ec_rst_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1129 1 T6 1 T7 1 T25 1
auto[1] 160 1 T16 4 T18 1 T44 4



Summary for Variable cp_ec_rst_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1172 1 T6 1 T7 1 T25 1
auto[1] 117 1 T16 2 T40 4 T45 4



Summary for Variable cp_flash_wp_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1140 1 T6 1 T7 1 T25 1
auto[1] 149 1 T16 3 T17 2 T46 3



Summary for Variable cp_flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1166 1 T6 1 T7 1 T25 1
auto[1] 123 1 T16 3 T18 1 T45 1



Summary for Variable cp_key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1181 1 T6 1 T7 1 T25 1
auto[1] 108 1 T16 3 T43 1 T42 3



Summary for Variable cp_key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1153 1 T6 1 T7 1 T25 1
auto[1] 136 1 T16 1 T18 3 T46 3



Summary for Variable cp_key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1157 1 T6 1 T7 1 T25 1
auto[1] 132 1 T16 1 T17 2 T18 1



Summary for Variable cp_key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1112 1 T6 1 T7 1 T25 1
auto[1] 177 1 T16 4 T17 2 T46 1



Summary for Variable cp_key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1177 1 T6 1 T7 1 T25 1
auto[1] 112 1 T16 3 T40 4 T45 4



Summary for Variable cp_key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1119 1 T6 1 T7 1 T25 1
auto[1] 170 1 T16 3 T18 3 T45 2



Summary for Variable cp_pwrb_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1163 1 T6 1 T7 1 T25 1
auto[1] 126 1 T16 2 T17 2 T18 1



Summary for Variable cp_pwrb_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1141 1 T6 1 T7 1 T25 1
auto[1] 148 1 T16 4 T17 3 T18 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%