Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1775

1

T15

17

T19

52

T20

10

auto[1]

511

1

T15

6

T20

2

T21

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1705

1

T15

23

T19

26

T20

11

auto[1]

581

1

T19

26

T20

1

T21

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1709

1

T15

10

T19

26

T20

12

auto[1]

577

1

T15

13

T19

26

T22

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1749

1

T15

19

T19

39

T20

10

auto[1]

537

1

T15

4

T19

13

T20

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2078

1

T15

23

T19

13

T20

11

auto[1]

208

1

T19

39

T20

1

T38

10

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2052

1

T15

23

T19

52

T20

10

auto[1]

234

1

T20

2

T38

5

T230

10

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2122

1

T15

23

T19

52

T20

11

auto[1]

164

1

T20

1

T21

1

T49

18

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2076

1

T15

23

T19

52

T20

11

auto[1]

210

1

T20

1

T38

5

T49

10

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2121

1

T15

23

T19

52

T20

12

auto[1]

165

1

T49

3

T230

20

T233

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1659

1

T15

13

T19

39

T20

11

auto[1]

627

1

T15

10

T19

13

T20

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	782	1			T15	23		T22	15		T52	3
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	54	1			T19	30		T233	4		T206	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	46	1			T230	10		T306	9		T316	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	28	1			T206	1		T317	4		T318	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	34	1			T230	7		T319	4		T317	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	26	1			T38	1		T209	1		T72	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T320	6		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	48	1			T21	1		T49	8		T71	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	13	1			T206	4		T321	3		T318	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	10	1			T69	1		T245	9		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T233	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	19	1			T49	7		T88	4		T195	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T20	1		T307	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	10	1			T49	3		T238	6		T69	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T238	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	52	1			T20	2		T234	4		T306	8
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	24	1			T38	4		T307	9		T322	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	26	1			T230	8		T234	3		T231	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	1	1			T238	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	66	1			T238	2		T306	7		T138	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	9	1			T138	2		T307	6		T323	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T72	1		T324	3		T325	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	9	1			T195	1		T326	2		T327	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T321	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	1	1			T245	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T308	3		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T230	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

68

1

T49

7

T230

2

T234

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

93

1

T38

1

T67

11

T251

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T15

6

T304

4

T251

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

95

1

T22

12

T231

4

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

38

1

T20

2

T49

8

T326

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

85

1

T15

4

T206

4

T328

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T53

3

T83

3

T306

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

94

1

T15

13

T19

10

T45

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T136

5

T153

1

T305

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T38

4

T142

2

T316

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

48

1

T39

5

T66

3

T67

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T45

3

T230

8

T247

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T52

3

T66

2

T204

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T233

4

T155

4

T93

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T45

1

T239

2

T329

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

83

1

T88

8

T238

2

T138

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

51

1

T49

3

T159

2

T238

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

72

1

T19

10

T20

1

T53

12

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T83

4

T159

1

T88

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

31

1

T42

6

T233

2

T318

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T272

8

T330

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T22

3

T39

3

T270

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T21

1

T89

2

T331

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70

1

T230

10

T206

1

T136

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T230

7

T246

2

T328

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T39

4

T206

5

T328

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T89

3

T187

1

T330

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T19

10

T246

2

T138

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T246

1

T304

1

T316

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

10

1

T247

2

T332

1

T187

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T67

1

T333

1

T332

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded