Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1194

1

T16

16

T110

13

T243

11

auto[1]

1218

1

T16

24

T110

7

T243

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

587

1

T16

10

T110

5

T243

7

from_0to1

588

1

T16

11

T110

4

T243

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1218

1

T16

20

T110

9

T243

8

auto[1]

1194

1

T16

20

T110

11

T243

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T16

21

T110

11

T243

12

auto[1]

1249

1

T16

19

T110

9

T243

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

82

1

T16

2

T110

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

85

1

T83

1

T338

1

T344

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T16

1

T243

2

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T110

1

T243

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

84

1

T110

1

T243

2

T83

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T16

2

T243

1

T45

2

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T16

4

T110

1

T243

1

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T16

2

T110

1

T243

2

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T16

4

T110

1

T243

2

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T16

1

T110

2

T243

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T243

1

T83

1

T338

3

auto[1]

from_1to0

auto[1]

auto[1]

79

1

T16

2

T345

1

T159

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T16

1

T83

1

T345

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T16

1

T110

1

T243

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T243

1

T83

1

T158

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T16

1

T45

1

T344

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1198

1

T16

20

T110

16

T243

8

auto[1]

1214

1

T16

20

T110

4

T243

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

607

1

T16

11

T110

5

T243

4

from_0to1

595

1

T16

11

T110

4

T243

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1212

1

T16

21

T110

8

T243

10

auto[1]

1200

1

T16

19

T110

12

T243

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T16

18

T110

13

T243

4

auto[1]

1216

1

T16

22

T110

7

T243

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T16

1

T110

1

T45

1

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T16

2

T110

2

T243

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T110

2

T83

1

T45

2

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T16

1

T83

2

T158

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T16

1

T110

1

T45

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T16

5

T243

2

T158

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T16

1

T110

1

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

83

1

T110

1

T243

1

T345

3

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T16

2

T243

1

T158

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T16

1

T83

1

T345

2

auto[1]

from_1to0

auto[1]

auto[0]

88

1

T16

3

T158

1

T338

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T16

1

T243

2

T45

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T16

1

T243

1

T345

2

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T110

1

T83

2

T45

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T158

1

T344

1

T159

1

auto[1]

from_0to1

auto[1]

auto[1]

86

1

T16

3

T243

1

T45

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T16

23

T110

12

T243

8

auto[1]

1212

1

T16

17

T110

8

T243

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T16

8

T110

6

T243

5

from_0to1

557

1

T16

8

T110

6

T243

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1232

1

T16

20

T110

12

T243

10

auto[1]

1180

1

T16

20

T110

8

T243

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1230

1

T16

20

T110

12

T243

8

auto[1]

1182

1

T16

20

T110

8

T243

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T16

2

T158

2

T338

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T16

1

T110

3

T243

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T16

2

T45

1

T345

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T16

1

T110

2

T243

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T16

1

T110

2

T344

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T110

1

T158

1

T345

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T16

1

T338

1

T198

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T16

1

T243

1

T83

2

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T110

1

T83

1

T345

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T16

1

T83

1

T338

2

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T16

1

T243

1

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T243

2

T158

1

T345

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T16

2

T110

2

T243

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T16

1

T243

1

T45

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T16

2

T110

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T243

1

T345

1

T338

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1189

1

T16

17

T110

8

T243

11

auto[1]

1223

1

T16

23

T110

12

T243

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

587

1

T16

14

T110

5

T243

4

from_0to1

582

1

T16

13

T110

5

T243

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T16

23

T110

11

T243

7

auto[1]

1209

1

T16

17

T110

9

T243

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1195

1

T16

20

T110

13

T243

11

auto[1]

1217

1

T16

20

T110

7

T243

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T16

1

T110

1

T345

2

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T16

1

T110

1

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T16

3

T110

1

T243

2

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T243

1

T158

1

T338

1

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T16

2

T83

2

T345

3

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T16

1

T243

1

T158

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T16

1

T110

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T16

1

T338

2

T159

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T16

1

T110

2

T243

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T16

5

T158

1

T338

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T16

2

T83

1

T345

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T16

1

T83

1

T338

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T16

3

T158

1

T345

1

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T16

2

T110

1

T243

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T110

2

T243

3

T338

2

auto[1]

from_0to1

auto[1]

auto[1]

91

1

T16

3

T110

1

T45

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1181

1

T16

22

T110

12

T243

8

auto[1]

1231

1

T16

18

T110

8

T243

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

573

1

T16

11

T110

7

T243

2

from_0to1

574

1

T16

11

T110

7

T243

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1234

1

T16

22

T110

12

T243

13

auto[1]

1178

1

T16

18

T110

8

T243

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T16

23

T110

9

T243

9

auto[1]

1225

1

T16

17

T110

11

T243

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T16

1

T110

1

T158

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T16

1

T110

1

T243

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T16

1

T110

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T16

1

T110

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T16

2

T110

1

T243

2

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T16

2

T110

1

T83

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T16

1

T110

2

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T110

1

T45

1

T338

2

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T16

1

T110

1

T45

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T16

3

T243

1

T45

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T16

2

T158

2

T345

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T16

1

T110

2

T83

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T16

1

T45

1

T158

1

auto[1]

from_0to1

auto[0]

auto[1]

90

1

T16

2

T110

2

T45

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T16

3

T45

1

T158

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T45

2

T158

2

T345

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1242

1

T16

21

T110

9

T243

13

auto[1]

1170

1

T16

19

T110

11

T243

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T16

8

T110

7

T243

5

from_0to1

578

1

T16

7

T110

6

T243

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1244

1

T16

21

T110

15

T243

8

auto[1]

1168

1

T16

19

T110

5

T243

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1215

1

T16

14

T110

7

T243

12

auto[1]

1197

1

T16

26

T110

13

T243

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T110

2

T243

1

T45

1

auto[0]

from_1to0

auto[0]

auto[1]

81

1

T16

1

T345

2

T338

2

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T16

1

T243

3

T83

2

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T16

1

T110

2

T243

1

auto[0]

from_0to1

auto[0]

auto[0]

88

1

T110

1

T243

1

T158

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T243

2

T83

2

T338

2

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T16

1

T243

1

T45

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T16

3

T110

1

T243

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T16

1

T45

1

T158

3

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T16

1

T110

3

T45

2

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T16

1

T83

1

T45

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T16

2

T83

1

T45

2

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T110

1

T345

1

T338

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T16

1

T110

3

T83

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T83

1

T45

2

T345

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T16

2

T45

1

T345

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1202

1

T16

17

T110

11

T243

7

auto[1]

1210

1

T16

23

T110

9

T243

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

580

1

T16

10

T110

5

T243

6

from_0to1

579

1

T16

10

T110

6

T243

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T16

22

T110

10

T243

10

auto[1]

1206

1

T16

18

T110

10

T243

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T16

22

T110

7

T243

7

auto[1]

1257

1

T16

18

T110

13

T243

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T83

1

T158

1

T345

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T16

1

T243

2

T45

1

auto[0]

from_1to0

auto[1]

auto[0]

75

1

T16

3

T83

1

T45

1

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T16

2

T45

1

T158

2

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T16

1

T110

1

T83

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T16

1

T110

2

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T16

1

T45

2

T158

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T16

1

T243

2

T83

2

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T16

3

T110

3

T83

2

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T16

1

T243

2

T158

1

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T243

1

T45

3

T344

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T110

2

T243

1

T83

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T16

2

T243

1

T83

1

auto[1]

from_0to1

auto[0]

auto[1]

87

1

T16

2

T110

1

T83

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T16

1

T110

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

89

1

T16

1

T110

1

T243

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1217

1

T16

17

T110

11

T243

11

auto[1]

1195

1

T16

23

T110

9

T243

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

566

1

T16

11

T110

3

T243

6

from_0to1

566

1

T16

12

T110

3

T243

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1219

1

T16

16

T110

10

T243

11

auto[1]

1193

1

T16

24

T110

10

T243

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T16

19

T110

9

T243

12

auto[1]

1216

1

T16

21

T110

11

T243

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T243

1

T158

1

T345

2

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T110

1

T45

1

T345

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T16

4

T110

1

T243

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T16

1

T243

1

T158

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T83

1

T45

1

T338

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T243

2

T45

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T16

2

T243

1

T158

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T16

1

T110

1

T338

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T243

1

T83

1

T158

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T16

1

T243

1

T83

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T16

2

T243

1

T45

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T16

3

T110

1

T83

1

auto[1]

from_0to1

auto[0]

auto[0]

74

1

T16

2

T243

1

T158

2

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T16

2

T243

1

T83

2

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T16

2

T243

1

T45

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T16

2

T110

2

T83

1