Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155111	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120619

1

T1

312

T6

19

T7

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142329	1			T1	841		T6	25		T7	25
values[0x0]	66520	1			T1	201		T6	13		T7	11
values[0x1]	66881	1			T1	205		T6	7		T7	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125968	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149762

1

T1

597

T6

21

T7

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1904	1			T2	2		T3	1		T8	6
valid_sources[0x01]	893	1			T3	1		T4	18		T8	6
valid_sources[0x02]	999	1			T8	2		T35	3		T5	3
valid_sources[0x03]	1095	1			T1	1		T3	1		T8	3
valid_sources[0x04]	926	1			T2	6		T8	2		T23	1
valid_sources[0x05]	912	1			T2	2		T4	33		T8	3
valid_sources[0x06]	1100	1			T1	11		T3	1		T4	38
valid_sources[0x07]	978	1			T4	34		T8	4		T35	5
valid_sources[0x08]	815	1			T1	21		T3	1		T8	4
valid_sources[0x09]	883	1			T1	14		T2	3		T8	2
valid_sources[0x0a]	2406	1			T1	1		T2	2		T8	4
valid_sources[0x0b]	958	1			T1	8		T8	3		T24	8
valid_sources[0x0c]	1148	1			T1	5		T8	4		T23	1
valid_sources[0x0d]	1255	1			T1	6		T2	1		T8	6
valid_sources[0x0e]	905	1			T1	1		T3	1		T8	4
valid_sources[0x0f]	1035	1			T1	3		T2	5		T3	2
valid_sources[0x10]	897	1			T2	4		T3	1		T4	38
valid_sources[0x11]	858	1			T6	1		T2	9		T3	1
valid_sources[0x12]	787	1			T1	2		T2	15		T8	5
valid_sources[0x13]	1031	1			T8	5		T23	2		T35	1
valid_sources[0x14]	1000	1			T1	4		T3	1		T8	5
valid_sources[0x15]	1618	1			T8	2		T23	1		T25	1
valid_sources[0x16]	1321	1			T6	5		T4	38		T8	7
valid_sources[0x17]	888	1			T8	5		T23	1		T35	2
valid_sources[0x18]	885	1			T2	12		T3	1		T8	5
valid_sources[0x19]	1360	1			T1	1		T4	57		T8	7
valid_sources[0x1a]	841	1			T1	12		T7	1		T8	2
valid_sources[0x1b]	1457	1			T1	16		T3	1		T4	38
valid_sources[0x1c]	1453	1			T1	2		T7	1		T2	13
valid_sources[0x1d]	1873	1			T1	3		T2	6		T4	38
valid_sources[0x1e]	989	1			T4	38		T35	1		T5	1
valid_sources[0x1f]	913	1			T2	33		T4	24		T8	6
valid_sources[0x20]	2280	1			T2	16		T4	43		T8	3
valid_sources[0x21]	1473	1			T1	6		T2	38		T8	2
valid_sources[0x22]	887	1			T2	1		T8	4		T35	2
valid_sources[0x23]	1072	1			T1	14		T2	11		T3	1
valid_sources[0x24]	873	1			T1	11		T2	8		T8	6
valid_sources[0x25]	1208	1			T1	1		T6	1		T8	5
valid_sources[0x26]	1004	1			T1	24		T2	1		T8	3
valid_sources[0x27]	1019	1			T1	1		T2	2		T8	7
valid_sources[0x28]	930	1			T6	1		T2	13		T8	5
valid_sources[0x29]	1567	1			T1	5		T2	1		T8	4
valid_sources[0x2a]	1266	1			T7	3		T2	8		T3	1
valid_sources[0x2b]	961	1			T1	5		T6	2		T2	2
valid_sources[0x2c]	1443	1			T1	8		T2	12		T8	5
valid_sources[0x2d]	882	1			T1	5		T8	6		T35	4
valid_sources[0x2e]	881	1			T1	6		T4	38		T8	2
valid_sources[0x2f]	765	1			T8	8		T35	3		T9	2
valid_sources[0x30]	989	1			T2	6		T3	1		T4	16
valid_sources[0x31]	1284	1			T1	7		T7	1		T8	7
valid_sources[0x32]	886	1			T1	14		T6	1		T2	7
valid_sources[0x33]	898	1			T1	22		T7	1		T8	3
valid_sources[0x34]	922	1			T2	4		T4	30		T8	2
valid_sources[0x35]	804	1			T1	4		T2	11		T8	5
valid_sources[0x36]	937	1			T2	4		T8	2		T35	12
valid_sources[0x37]	1066	1			T1	11		T2	15		T3	1
valid_sources[0x38]	919	1			T2	4		T4	38		T8	2
valid_sources[0x39]	996	1			T7	1		T2	7		T3	1
valid_sources[0x3a]	1834	1			T1	2		T8	11		T23	3
valid_sources[0x3b]	896	1			T2	13		T8	4		T5	2
valid_sources[0x3c]	929	1			T6	2		T2	1		T8	2
valid_sources[0x3d]	920	1			T2	8		T3	1		T8	5
valid_sources[0x3e]	945	1			T1	5		T6	2		T8	4
valid_sources[0x3f]	1460	1			T1	10		T2	5		T3	3
valid_sources[0x40]	993	1			T7	1		T2	2		T4	3
valid_sources[0x41]	1228	1			T1	10		T2	4		T3	1
valid_sources[0x42]	1212	1			T3	2		T4	8		T8	4
valid_sources[0x43]	919	1			T1	3		T7	2		T2	10
valid_sources[0x44]	1038	1			T7	2		T2	1		T3	1
valid_sources[0x45]	965	1			T1	15		T3	1		T8	6
valid_sources[0x46]	1197	1			T1	4		T4	66		T8	2
valid_sources[0x47]	867	1			T1	7		T6	1		T2	6
valid_sources[0x48]	1209	1			T2	21		T8	4		T35	3
valid_sources[0x49]	840	1			T1	5		T2	17		T3	3
valid_sources[0x4a]	887	1			T7	2		T3	1		T8	3
valid_sources[0x4b]	895	1			T1	4		T2	25		T8	2
valid_sources[0x4c]	1011	1			T1	15		T2	2		T8	2
valid_sources[0x4d]	1066	1			T2	8		T3	1		T8	5
valid_sources[0x4e]	1155	1			T1	3		T2	7		T3	2
valid_sources[0x4f]	781	1			T1	1		T6	1		T8	5
valid_sources[0x50]	824	1			T1	24		T2	2		T3	1
valid_sources[0x51]	913	1			T1	10		T7	1		T4	3
valid_sources[0x52]	1017	1			T7	1		T2	13		T4	24
valid_sources[0x53]	771	1			T1	11		T8	4		T35	1
valid_sources[0x54]	709	1			T1	6		T7	1		T23	2
valid_sources[0x55]	1045	1			T1	2		T2	1		T3	1
valid_sources[0x56]	1166	1			T2	9		T4	38		T8	4
valid_sources[0x57]	1516	1			T1	20		T3	1		T8	5
valid_sources[0x58]	852	1			T8	6		T23	1		T25	2
valid_sources[0x59]	822	1			T1	6		T3	1		T8	6
valid_sources[0x5a]	1299	1			T1	8		T3	1		T8	8
valid_sources[0x5b]	871	1			T2	6		T8	9		T5	1
valid_sources[0x5c]	1030	1			T1	3		T6	1		T4	38
valid_sources[0x5d]	1205	1			T1	30		T8	6		T35	1
valid_sources[0x5e]	799	1			T1	17		T2	2		T8	2
valid_sources[0x5f]	757	1			T1	13		T8	2		T23	2
valid_sources[0x60]	907	1			T1	2		T3	1		T8	5
valid_sources[0x61]	1251	1			T1	14		T7	1		T3	2
valid_sources[0x62]	687	1			T1	7		T3	1		T8	2
valid_sources[0x63]	910	1			T1	5		T2	5		T8	3
valid_sources[0x64]	2136	1			T2	3		T4	9		T8	4
valid_sources[0x65]	2039	1			T4	38		T8	5		T23	3
valid_sources[0x66]	857	1			T1	8		T7	1		T3	1
valid_sources[0x67]	1667	1			T1	10		T2	4		T4	76
valid_sources[0x68]	931	1			T2	2		T4	18		T8	4
valid_sources[0x69]	943	1			T3	1		T8	5		T23	1
valid_sources[0x6a]	1040	1			T1	6		T2	4		T4	64
valid_sources[0x6b]	1001	1			T1	4		T2	1		T8	3
valid_sources[0x6c]	1917	1			T1	2		T6	2		T4	28
valid_sources[0x6d]	932	1			T1	15		T7	1		T2	2
valid_sources[0x6e]	871	1			T8	4		T23	1		T283	33
valid_sources[0x6f]	968	1			T1	5		T4	20		T8	5
valid_sources[0x70]	868	1			T1	2		T4	38		T8	6
valid_sources[0x71]	756	1			T1	3		T7	1		T4	43
valid_sources[0x72]	1428	1			T8	5		T35	4		T5	1
valid_sources[0x73]	1153	1			T1	18		T7	1		T2	6
valid_sources[0x74]	855	1			T8	4		T23	3		T5	1
valid_sources[0x75]	1008	1			T1	5		T2	1		T3	1
valid_sources[0x76]	1067	1			T1	22		T8	6		T23	2
valid_sources[0x77]	1086	1			T4	18		T8	5		T23	1
valid_sources[0x78]	878	1			T2	3		T3	3		T8	8
valid_sources[0x79]	933	1			T1	6		T4	34		T8	10
valid_sources[0x7a]	896	1			T1	2		T3	1		T8	7
valid_sources[0x7b]	900	1			T7	1		T2	6		T8	6
valid_sources[0x7c]	846	1			T8	2		T23	1		T35	1
valid_sources[0x7d]	829	1			T1	10		T7	2		T2	7
valid_sources[0x7e]	809	1			T1	3		T8	3		T35	2
valid_sources[0x7f]	2316	1			T1	8		T2	11		T3	3
valid_sources[0x80]	847	1			T1	17		T8	6		T25	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65437

1

T1

129

T6

15

T7

12

values[0x0]

all_enables

biggest_size

32405

1

T1

108

T6

3

T7

4

values[0x1]

all_enables

biggest_size

22777

1

T1

75

T6

1

T7

2