Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1304240379	11302	0	0
auto_block_debounce_ctl_rd_A	1304240379	2154	0	0
auto_block_out_ctl_rd_A	1304240379	2880	0	0
com_det_ctl_0_rd_A	1304240379	3705	0	0
com_det_ctl_1_rd_A	1304240379	3754	0	0
com_det_ctl_2_rd_A	1304240379	3788	0	0
com_det_ctl_3_rd_A	1304240379	3922	0	0
com_out_ctl_0_rd_A	1304240379	4232	0	0
com_out_ctl_1_rd_A	1304240379	4222	0	0
com_out_ctl_2_rd_A	1304240379	4240	0	0
com_out_ctl_3_rd_A	1304240379	4426	0	0
com_pre_det_ctl_0_rd_A	1304240379	1669	0	0
com_pre_det_ctl_1_rd_A	1304240379	1564	0	0
com_pre_det_ctl_2_rd_A	1304240379	1540	0	0
com_pre_det_ctl_3_rd_A	1304240379	1532	0	0
com_pre_sel_ctl_0_rd_A	1304240379	4570	0	0
com_pre_sel_ctl_1_rd_A	1304240379	4622	0	0
com_pre_sel_ctl_2_rd_A	1304240379	4508	0	0
com_pre_sel_ctl_3_rd_A	1304240379	4562	0	0
com_sel_ctl_0_rd_A	1304240379	4640	0	0
com_sel_ctl_1_rd_A	1304240379	4832	0	0
com_sel_ctl_2_rd_A	1304240379	4409	0	0
com_sel_ctl_3_rd_A	1304240379	4384	0	0
ec_rst_ctl_rd_A	1304240379	2545	0	0
intr_enable_rd_A	1304240379	2184	0	0
key_intr_ctl_rd_A	1304240379	4150	0	0
key_intr_debounce_ctl_rd_A	1304240379	1521	0	0
key_invert_ctl_rd_A	1304240379	6458	0	0
pin_allowed_ctl_rd_A	1304240379	7693	0	0
pin_out_ctl_rd_A	1304240379	6294	0	0
pin_out_value_rd_A	1304240379	6148	0	0
regwen_rd_A	1304240379	1800	0	0
ulp_ac_debounce_ctl_rd_A	1304240379	1762	0	0
ulp_ctl_rd_A	1304240379	1768	0	0
ulp_lid_debounce_ctl_rd_A	1304240379	1957	0	0
ulp_pwrb_debounce_ctl_rd_A	1304240379	1894	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	11302	0	0
T1	211463	3	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	0	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	1	0	0
T10	0	10	0	0
T23	104706	490	0	0
T24	88462	206	0	0
T25	44714	0	0	0
T35	0	751	0	0
T258	0	450	0	0
T259	0	212	0	0
T260	0	674	0	0
T273	0	48	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	2154	0	0
T1	211463	70	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	167	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	2	0	0
T33	0	107	0	0
T274	0	227	0	0
T275	0	6	0	0
T276	0	14	0	0
T277	0	9	0	0
T278	0	2	0	0
T279	0	55	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	2880	0	0
T1	211463	213	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	136	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	8	0	0
T33	0	266	0	0
T274	0	204	0	0
T275	0	11	0	0
T276	0	9	0	0
T277	0	20	0	0
T278	0	6	0	0
T279	0	113	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	3705	0	0
T1	211463	37	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	149	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	8	0	0
T25	44714	0	0	0
T32	0	10	0	0
T33	0	83	0	0
T35	0	6	0	0
T261	0	11	0	0
T274	0	236	0	0
T275	0	28	0	0
T276	0	10	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	3754	0	0
T1	211463	42	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	156	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	5	0	0
T33	0	70	0	0
T35	0	1	0	0
T261	0	20	0	0
T274	0	172	0	0
T275	0	20	0	0
T276	0	8	0	0
T277	0	8	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	3788	0	0
T1	211463	34	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	136	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	1	0	0
T25	44714	0	0	0
T32	0	12	0	0
T33	0	53	0	0
T35	0	8	0	0
T274	0	200	0	0
T275	0	19	0	0
T276	0	16	0	0
T280	0	4	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	3922	0	0
T1	211463	48	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	226	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	12	0	0
T33	0	96	0	0
T35	0	6	0	0
T261	0	15	0	0
T274	0	234	0	0
T275	0	19	0	0
T276	0	8	0	0
T277	0	12	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4232	0	0
T1	211463	108	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	159	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	31	0	0
T33	0	143	0	0
T35	0	12	0	0
T261	0	25	0	0
T274	0	175	0	0
T275	0	8	0	0
T276	0	14	0	0
T277	0	1	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4222	0	0
T1	211463	63	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	180	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	33	0	0
T33	0	205	0	0
T35	0	5	0	0
T274	0	223	0	0
T275	0	32	0	0
T276	0	14	0	0
T277	0	3	0	0
T278	0	9	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4240	0	0
T1	211463	74	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	164	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	22	0	0
T33	0	132	0	0
T35	0	6	0	0
T261	0	6	0	0
T274	0	205	0	0
T275	0	20	0	0
T276	0	5	0	0
T280	0	5	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4426	0	0
T1	211463	101	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	189	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	12	0	0
T33	0	158	0	0
T261	0	30	0	0
T274	0	181	0	0
T275	0	16	0	0
T276	0	9	0	0
T277	0	22	0	0
T278	0	10	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1669	0	0
T1	211463	33	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	165	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	6	0	0
T33	0	51	0	0
T35	0	3	0	0
T261	0	11	0	0
T274	0	223	0	0
T275	0	2	0	0
T276	0	19	0	0
T277	0	3	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1564	0	0
T1	211463	49	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	161	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	11	0	0
T33	0	63	0	0
T35	0	5	0	0
T261	0	17	0	0
T274	0	184	0	0
T275	0	6	0	0
T276	0	12	0	0
T280	0	2	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1540	0	0
T1	211463	32	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	162	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	6	0	0
T33	0	69	0	0
T35	0	23	0	0
T261	0	18	0	0
T274	0	220	0	0
T275	0	25	0	0
T276	0	16	0	0
T277	0	12	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1532	0	0
T1	211463	37	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	143	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	4	0	0
T25	44714	0	0	0
T32	0	3	0	0
T33	0	89	0	0
T35	0	14	0	0
T261	0	6	0	0
T274	0	218	0	0
T275	0	18	0	0
T276	0	19	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4570	0	0
T1	211463	86	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	142	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	33	0	0
T33	0	230	0	0
T261	0	16	0	0
T274	0	222	0	0
T276	0	18	0	0
T277	0	6	0	0
T278	0	3	0	0
T279	0	110	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4622	0	0
T1	211463	143	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	166	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	31	0	0
T33	0	225	0	0
T35	0	9	0	0
T261	0	18	0	0
T274	0	210	0	0
T275	0	27	0	0
T276	0	12	0	0
T280	0	3	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4508	0	0
T1	211463	64	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	184	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	4	0	0
T25	44714	0	0	0
T32	0	15	0	0
T33	0	219	0	0
T35	0	3	0	0
T274	0	214	0	0
T275	0	17	0	0
T276	0	15	0	0
T280	0	1	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4562	0	0
T1	211463	82	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	169	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	34	0	0
T33	0	239	0	0
T35	0	5	0	0
T261	0	11	0	0
T274	0	256	0	0
T275	0	19	0	0
T276	0	16	0	0
T277	0	6	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4640	0	0
T1	211463	127	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	142	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	33	0	0
T33	0	175	0	0
T35	0	10	0	0
T261	0	15	0	0
T274	0	221	0	0
T275	0	10	0	0
T276	0	11	0	0
T280	0	10	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4832	0	0
T1	211463	122	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	233	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	21	0	0
T33	0	300	0	0
T35	0	1	0	0
T261	0	20	0	0
T274	0	237	0	0
T275	0	30	0	0
T276	0	25	0	0
T277	0	22	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4409	0	0
T1	211463	89	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	139	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	20	0	0
T33	0	213	0	0
T35	0	2	0	0
T274	0	245	0	0
T275	0	17	0	0
T276	0	5	0	0
T277	0	5	0	0
T280	0	2	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4384	0	0
T1	211463	86	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	186	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	28	0	0
T33	0	169	0	0
T274	0	203	0	0
T275	0	18	0	0
T276	0	9	0	0
T277	0	42	0	0
T278	0	7	0	0
T280	0	4	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	2545	0	0
T1	211463	42	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	168	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	13	0	0
T33	0	67	0	0
T261	0	12	0	0
T274	0	212	0	0
T275	0	19	0	0
T276	0	15	0	0
T277	0	7	0	0
T278	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	2184	0	0
T1	211463	41	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	180	0	0
T6	201391	28	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	10	0	0
T33	0	100	0	0
T35	0	14	0	0
T274	0	249	0	0
T275	0	22	0	0
T276	0	14	0	0
T281	0	11	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	4150	0	0
T1	211463	270	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	183	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	5	0	0
T33	0	458	0	0
T35	0	10	0	0
T261	0	21	0	0
T274	0	223	0	0
T275	0	48	0	0
T276	0	8	0	0
T280	0	1	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1521	0	0
T1	211463	25	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	172	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	2	0	0
T25	44714	0	0	0
T32	0	3	0	0
T33	0	41	0	0
T35	0	4	0	0
T274	0	241	0	0
T275	0	10	0	0
T276	0	6	0	0
T277	0	2	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	6458	0	0
T1	211463	241	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	158	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	102	0	0
T33	0	506	0	0
T35	0	31	0	0
T261	0	6	0	0
T274	0	249	0	0
T275	0	28	0	0
T276	0	9	0	0
T280	0	2	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	7693	0	0
T1	211463	433	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	167	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	40	0	0
T33	0	642	0	0
T261	0	4	0	0
T274	0	243	0	0
T275	0	37	0	0
T276	0	15	0	0
T277	0	2	0	0
T278	0	6	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	6294	0	0
T1	211463	183	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	178	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	33	0	0
T33	0	349	0	0
T261	0	3	0	0
T274	0	191	0	0
T275	0	10	0	0
T276	0	12	0	0
T277	0	28	0	0
T278	0	16	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	6148	0	0
T1	211463	150	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	182	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	36	0	0
T33	0	286	0	0
T35	0	3	0	0
T261	0	1	0	0
T274	0	235	0	0
T275	0	5	0	0
T276	0	9	0	0
T280	0	5	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1800	0	0
T1	211463	53	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	180	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	5	0	0
T33	0	67	0	0
T35	0	13	0	0
T261	0	9	0	0
T274	0	208	0	0
T275	0	26	0	0
T276	0	11	0	0
T280	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1762	0	0
T1	211463	19	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	164	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	6	0	0
T33	0	66	0	0
T35	0	8	0	0
T274	0	201	0	0
T276	0	5	0	0
T277	0	33	0	0
T278	0	9	0	0
T280	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1768	0	0
T1	211463	31	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	135	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	1	0	0
T25	44714	0	0	0
T32	0	9	0	0
T33	0	62	0	0
T35	0	7	0	0
T274	0	234	0	0
T275	0	35	0	0
T276	0	8	0	0
T280	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1957	0	0
T1	211463	33	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	148	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	0	0	0
T25	44714	0	0	0
T32	0	4	0	0
T33	0	74	0	0
T35	0	10	0	0
T261	0	9	0	0
T274	0	248	0	0
T275	0	13	0	0
T276	0	18	0	0
T280	0	5	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304240379	1894	0	0
T1	211463	41	0	0
T2	103895	0	0	0
T3	49399	0	0	0
T4	80192	154	0	0
T6	201391	0	0	0
T7	193145	0	0	0
T8	219729	0	0	0
T23	104706	0	0	0
T24	88462	1	0	0
T25	44714	0	0	0
T32	0	5	0	0
T33	0	63	0	0
T35	0	21	0	0
T261	0	19	0	0
T274	0	212	0	0
T275	0	16	0	0
T276	0	6	0	0