| T209 |
/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.1404146701 |
|
|
Dec 27 01:28:53 PM PST 23 |
Dec 27 01:29:18 PM PST 23 |
39374263628 ps |
| T210 |
/workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1943473173 |
|
|
Dec 27 01:27:39 PM PST 23 |
Dec 27 01:27:43 PM PST 23 |
2620384099 ps |
| T425 |
/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.385665578 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:00 PM PST 23 |
3315859285 ps |
| T426 |
/workspace/coverage/default/40.sysrst_ctrl_alert_test.2510830611 |
|
|
Dec 27 01:29:22 PM PST 23 |
Dec 27 01:29:26 PM PST 23 |
2018977702 ps |
| T234 |
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2946974035 |
|
|
Dec 27 01:28:33 PM PST 23 |
Dec 27 01:31:25 PM PST 23 |
66913401843 ps |
| T328 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect.2919252787 |
|
|
Dec 27 01:27:07 PM PST 23 |
Dec 27 01:30:04 PM PST 23 |
66472133840 ps |
| T59 |
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2470856780 |
|
|
Dec 27 01:29:03 PM PST 23 |
Dec 27 01:30:21 PM PST 23 |
37825557881 ps |
| T211 |
/workspace/coverage/default/20.sysrst_ctrl_smoke.1010585242 |
|
|
Dec 27 01:28:02 PM PST 23 |
Dec 27 01:28:06 PM PST 23 |
2113397624 ps |
| T212 |
/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.494524247 |
|
|
Dec 27 01:28:16 PM PST 23 |
Dec 27 01:28:23 PM PST 23 |
2608553533 ps |
| T213 |
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3317637180 |
|
|
Dec 27 01:29:49 PM PST 23 |
Dec 27 01:36:25 PM PST 23 |
284237660076 ps |
| T214 |
/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3037917554 |
|
|
Dec 27 01:29:36 PM PST 23 |
Dec 27 01:31:04 PM PST 23 |
35543995308 ps |
| T427 |
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3601082520 |
|
|
Dec 27 01:29:50 PM PST 23 |
Dec 27 01:30:00 PM PST 23 |
3421962952 ps |
| T428 |
/workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.4027345016 |
|
|
Dec 27 01:28:30 PM PST 23 |
Dec 27 01:28:43 PM PST 23 |
2609348141 ps |
| T429 |
/workspace/coverage/default/12.sysrst_ctrl_alert_test.1969501969 |
|
|
Dec 27 01:27:47 PM PST 23 |
Dec 27 01:27:53 PM PST 23 |
2017004322 ps |
| T430 |
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.967494329 |
|
|
Dec 27 01:29:49 PM PST 23 |
Dec 27 01:31:01 PM PST 23 |
24322922501 ps |
| T207 |
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2572036123 |
|
|
Dec 27 01:30:06 PM PST 23 |
Dec 27 01:30:18 PM PST 23 |
2880663489 ps |
| T133 |
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3880999810 |
|
|
Dec 27 01:29:21 PM PST 23 |
Dec 27 01:29:23 PM PST 23 |
3952120603 ps |
| T238 |
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.466839360 |
|
|
Dec 27 01:29:58 PM PST 23 |
Dec 27 01:31:23 PM PST 23 |
93916906654 ps |
| T255 |
/workspace/coverage/default/0.sysrst_ctrl_sec_cm.3090483532 |
|
|
Dec 27 01:27:07 PM PST 23 |
Dec 27 01:27:35 PM PST 23 |
42154394991 ps |
| T89 |
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2015789097 |
|
|
Dec 27 01:29:43 PM PST 23 |
Dec 27 01:32:09 PM PST 23 |
55670008127 ps |
| T267 |
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1315475017 |
|
|
Dec 27 01:28:59 PM PST 23 |
Dec 27 01:29:03 PM PST 23 |
2629232262 ps |
| T268 |
/workspace/coverage/default/47.sysrst_ctrl_smoke.493175642 |
|
|
Dec 27 01:29:17 PM PST 23 |
Dec 27 01:29:19 PM PST 23 |
2122730069 ps |
| T431 |
/workspace/coverage/default/37.sysrst_ctrl_alert_test.572202284 |
|
|
Dec 27 01:29:27 PM PST 23 |
Dec 27 01:29:31 PM PST 23 |
2019209723 ps |
| T72 |
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.2321178666 |
|
|
Dec 27 01:29:42 PM PST 23 |
Dec 27 01:34:29 PM PST 23 |
122390753511 ps |
| T60 |
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3064305380 |
|
|
Dec 27 01:28:20 PM PST 23 |
Dec 27 01:28:28 PM PST 23 |
3988062855 ps |
| T306 |
/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3504351590 |
|
|
Dec 27 01:28:11 PM PST 23 |
Dec 27 01:31:25 PM PST 23 |
74878402909 ps |
| T432 |
/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2038057171 |
|
|
Dec 27 01:28:02 PM PST 23 |
Dec 27 01:28:07 PM PST 23 |
2612837766 ps |
| T433 |
/workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.2610772298 |
|
|
Dec 27 01:27:00 PM PST 23 |
Dec 27 01:27:11 PM PST 23 |
3692596821 ps |
| T239 |
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3256739104 |
|
|
Dec 27 01:28:07 PM PST 23 |
Dec 27 01:29:11 PM PST 23 |
71047702995 ps |
| T61 |
/workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1056180029 |
|
|
Dec 27 01:29:14 PM PST 23 |
Dec 27 01:30:13 PM PST 23 |
30208753819 ps |
| T134 |
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1957086122 |
|
|
Dec 27 01:30:09 PM PST 23 |
Dec 27 01:30:14 PM PST 23 |
2046590012 ps |
| T135 |
/workspace/coverage/default/20.sysrst_ctrl_pin_access_test.4239305202 |
|
|
Dec 27 01:28:03 PM PST 23 |
Dec 27 01:28:07 PM PST 23 |
2196671105 ps |
| T136 |
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1032853445 |
|
|
Dec 27 01:27:19 PM PST 23 |
Dec 27 01:34:28 PM PST 23 |
159484775184 ps |
| T137 |
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.708887210 |
|
|
Dec 27 01:29:55 PM PST 23 |
Dec 27 01:32:04 PM PST 23 |
48321166157 ps |
| T138 |
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3578364598 |
|
|
Dec 27 01:29:08 PM PST 23 |
Dec 27 01:30:11 PM PST 23 |
43309252019 ps |
| T139 |
/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3812923011 |
|
|
Dec 27 01:27:56 PM PST 23 |
Dec 27 01:28:00 PM PST 23 |
2637966062 ps |
| T140 |
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2240002839 |
|
|
Dec 27 01:28:36 PM PST 23 |
Dec 27 01:28:44 PM PST 23 |
10490420178 ps |
| T141 |
/workspace/coverage/default/19.sysrst_ctrl_pin_override_test.1115753159 |
|
|
Dec 27 01:28:03 PM PST 23 |
Dec 27 01:28:07 PM PST 23 |
2521195600 ps |
| T142 |
/workspace/coverage/default/10.sysrst_ctrl_combo_detect.2970409670 |
|
|
Dec 27 01:28:18 PM PST 23 |
Dec 27 01:28:57 PM PST 23 |
70490812103 ps |
| T434 |
/workspace/coverage/default/17.sysrst_ctrl_stress_all.279868105 |
|
|
Dec 27 01:27:51 PM PST 23 |
Dec 27 01:28:25 PM PST 23 |
12047080127 ps |
| T435 |
/workspace/coverage/default/1.sysrst_ctrl_smoke.684822281 |
|
|
Dec 27 01:26:47 PM PST 23 |
Dec 27 01:26:49 PM PST 23 |
2129286970 ps |
| T90 |
/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3532631949 |
|
|
Dec 27 01:29:08 PM PST 23 |
Dec 27 01:30:16 PM PST 23 |
30831177719 ps |
| T129 |
/workspace/coverage/default/30.sysrst_ctrl_edge_detect.3314622395 |
|
|
Dec 27 01:29:05 PM PST 23 |
Dec 27 01:29:11 PM PST 23 |
3244869086 ps |
| T436 |
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1821220049 |
|
|
Dec 27 01:29:20 PM PST 23 |
Dec 27 01:29:24 PM PST 23 |
3409863399 ps |
| T437 |
/workspace/coverage/default/28.sysrst_ctrl_smoke.3914383729 |
|
|
Dec 27 01:29:01 PM PST 23 |
Dec 27 01:29:08 PM PST 23 |
2107540839 ps |
| T438 |
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1684914010 |
|
|
Dec 27 01:29:38 PM PST 23 |
Dec 27 01:29:42 PM PST 23 |
2635467339 ps |
| T439 |
/workspace/coverage/default/8.sysrst_ctrl_smoke.110920039 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:04 PM PST 23 |
2115491869 ps |
| T91 |
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.657374468 |
|
|
Dec 27 01:27:48 PM PST 23 |
Dec 27 01:27:58 PM PST 23 |
29896844458 ps |
| T111 |
/workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.3317821006 |
|
|
Dec 27 01:28:17 PM PST 23 |
Dec 27 01:28:24 PM PST 23 |
6523111296 ps |
| T112 |
/workspace/coverage/default/21.sysrst_ctrl_stress_all.1816878128 |
|
|
Dec 27 01:28:04 PM PST 23 |
Dec 27 01:30:00 PM PST 23 |
323046136032 ps |
| T340 |
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3358112728 |
|
|
Dec 27 01:29:55 PM PST 23 |
Dec 27 01:31:39 PM PST 23 |
41029619023 ps |
| T152 |
/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3758469254 |
|
|
Dec 27 01:28:01 PM PST 23 |
Dec 27 01:29:02 PM PST 23 |
24105788160 ps |
| T113 |
/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1937782120 |
|
|
Dec 27 01:28:54 PM PST 23 |
Dec 27 01:28:59 PM PST 23 |
5475224490 ps |
| T440 |
/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1680193478 |
|
|
Dec 27 01:28:25 PM PST 23 |
Dec 27 01:28:28 PM PST 23 |
2589436125 ps |
| T198 |
/workspace/coverage/default/13.sysrst_ctrl_stress_all.3132966771 |
|
|
Dec 27 01:28:15 PM PST 23 |
Dec 27 01:28:26 PM PST 23 |
13285182923 ps |
| T143 |
/workspace/coverage/default/39.sysrst_ctrl_edge_detect.3712356704 |
|
|
Dec 27 01:29:21 PM PST 23 |
Dec 27 01:29:23 PM PST 23 |
3351559204 ps |
| T441 |
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1118514305 |
|
|
Dec 27 01:30:06 PM PST 23 |
Dec 27 01:30:12 PM PST 23 |
2210625242 ps |
| T144 |
/workspace/coverage/default/12.sysrst_ctrl_edge_detect.1794002198 |
|
|
Dec 27 01:27:43 PM PST 23 |
Dec 27 01:27:55 PM PST 23 |
4394526483 ps |
| T442 |
/workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.593001350 |
|
|
Dec 27 01:29:08 PM PST 23 |
Dec 27 01:29:16 PM PST 23 |
2503883514 ps |
| T443 |
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.18721443 |
|
|
Dec 27 01:29:56 PM PST 23 |
Dec 27 01:30:05 PM PST 23 |
2611513109 ps |
| T231 |
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2091642971 |
|
|
Dec 27 01:29:43 PM PST 23 |
Dec 27 01:31:28 PM PST 23 |
78260093423 ps |
| T444 |
/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.162332170 |
|
|
Dec 27 01:28:08 PM PST 23 |
Dec 27 01:28:17 PM PST 23 |
3186014657 ps |
| T445 |
/workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1665059806 |
|
|
Dec 27 01:28:40 PM PST 23 |
Dec 27 01:28:54 PM PST 23 |
4891627073 ps |
| T127 |
/workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3619565556 |
|
|
Dec 27 01:29:05 PM PST 23 |
Dec 27 01:29:11 PM PST 23 |
10960817907 ps |
| T446 |
/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.599768515 |
|
|
Dec 27 01:26:51 PM PST 23 |
Dec 27 01:26:58 PM PST 23 |
2163763061 ps |
| T447 |
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1487914321 |
|
|
Dec 27 01:30:02 PM PST 23 |
Dec 27 01:30:06 PM PST 23 |
2117602850 ps |
| T448 |
/workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1900489733 |
|
|
Dec 27 01:28:53 PM PST 23 |
Dec 27 01:28:57 PM PST 23 |
5996009555 ps |
| T449 |
/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2601386282 |
|
|
Dec 27 01:29:01 PM PST 23 |
Dec 27 01:29:04 PM PST 23 |
2841855982 ps |
| T450 |
/workspace/coverage/default/22.sysrst_ctrl_pin_override_test.734935994 |
|
|
Dec 27 01:27:55 PM PST 23 |
Dec 27 01:28:00 PM PST 23 |
2520601120 ps |
| T232 |
/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2358706685 |
|
|
Dec 27 01:28:08 PM PST 23 |
Dec 27 01:28:36 PM PST 23 |
34881972092 ps |
| T451 |
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2898270950 |
|
|
Dec 27 01:29:17 PM PST 23 |
Dec 27 01:29:19 PM PST 23 |
2147608667 ps |
| T199 |
/workspace/coverage/default/28.sysrst_ctrl_edge_detect.1504670309 |
|
|
Dec 27 01:28:01 PM PST 23 |
Dec 27 01:28:07 PM PST 23 |
3240171835 ps |
| T452 |
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3739608051 |
|
|
Dec 27 01:29:40 PM PST 23 |
Dec 27 01:29:42 PM PST 23 |
2286798030 ps |
| T69 |
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1765294312 |
|
|
Dec 27 01:29:58 PM PST 23 |
Dec 27 01:30:35 PM PST 23 |
47254723399 ps |
| T453 |
/workspace/coverage/default/2.sysrst_ctrl_pin_override_test.75454594 |
|
|
Dec 27 01:26:53 PM PST 23 |
Dec 27 01:26:56 PM PST 23 |
2528695500 ps |
| T333 |
/workspace/coverage/default/1.sysrst_ctrl_combo_detect.3642138334 |
|
|
Dec 27 01:26:49 PM PST 23 |
Dec 27 01:32:30 PM PST 23 |
122500801534 ps |
| T454 |
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1880468840 |
|
|
Dec 27 01:29:51 PM PST 23 |
Dec 27 01:29:59 PM PST 23 |
3463670026 ps |
| T455 |
/workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1221920022 |
|
|
Dec 27 01:28:42 PM PST 23 |
Dec 27 01:28:49 PM PST 23 |
11651639128 ps |
| T68 |
/workspace/coverage/default/1.sysrst_ctrl_feature_disable.941367544 |
|
|
Dec 27 01:27:07 PM PST 23 |
Dec 27 01:27:19 PM PST 23 |
38159468743 ps |
| T456 |
/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3010240481 |
|
|
Dec 27 01:27:52 PM PST 23 |
Dec 27 01:28:00 PM PST 23 |
9294747856 ps |
| T457 |
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3721903220 |
|
|
Dec 27 01:27:10 PM PST 23 |
Dec 27 01:27:13 PM PST 23 |
2496794246 ps |
| T458 |
/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2449714019 |
|
|
Dec 27 01:27:44 PM PST 23 |
Dec 27 01:28:00 PM PST 23 |
5236943306 ps |
| T319 |
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.221597047 |
|
|
Dec 27 01:30:00 PM PST 23 |
Dec 27 01:30:48 PM PST 23 |
37102449137 ps |
| T304 |
/workspace/coverage/default/26.sysrst_ctrl_stress_all.3675083374 |
|
|
Dec 27 01:28:54 PM PST 23 |
Dec 27 01:30:48 PM PST 23 |
114205227649 ps |
| T200 |
/workspace/coverage/default/24.sysrst_ctrl_edge_detect.3843033194 |
|
|
Dec 27 01:29:05 PM PST 23 |
Dec 27 01:35:27 PM PST 23 |
264497106175 ps |
| T459 |
/workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.2793171805 |
|
|
Dec 27 01:29:17 PM PST 23 |
Dec 27 01:29:25 PM PST 23 |
2453757087 ps |
| T460 |
/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3400333494 |
|
|
Dec 27 01:29:04 PM PST 23 |
Dec 27 01:29:09 PM PST 23 |
2616102737 ps |
| T461 |
/workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.2275610132 |
|
|
Dec 27 01:27:51 PM PST 23 |
Dec 27 01:27:59 PM PST 23 |
2447585121 ps |
| T462 |
/workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2085595734 |
|
|
Dec 27 01:27:56 PM PST 23 |
Dec 27 01:31:09 PM PST 23 |
1466958158455 ps |
| T316 |
/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3616735842 |
|
|
Dec 27 01:29:10 PM PST 23 |
Dec 27 01:29:49 PM PST 23 |
58923335662 ps |
| T463 |
/workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1292481291 |
|
|
Dec 27 01:27:49 PM PST 23 |
Dec 27 01:27:55 PM PST 23 |
2470826473 ps |
| T464 |
/workspace/coverage/default/32.sysrst_ctrl_smoke.2042935724 |
|
|
Dec 27 01:28:50 PM PST 23 |
Dec 27 01:28:57 PM PST 23 |
2110561700 ps |
| T465 |
/workspace/coverage/default/36.sysrst_ctrl_alert_test.4141550125 |
|
|
Dec 27 01:28:58 PM PST 23 |
Dec 27 01:29:09 PM PST 23 |
2017008931 ps |
| T466 |
/workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.2730818478 |
|
|
Dec 27 01:27:18 PM PST 23 |
Dec 27 01:27:22 PM PST 23 |
2623867950 ps |
| T467 |
/workspace/coverage/default/39.sysrst_ctrl_alert_test.1871465577 |
|
|
Dec 27 01:29:49 PM PST 23 |
Dec 27 01:29:58 PM PST 23 |
2015670843 ps |
| T468 |
/workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2435017511 |
|
|
Dec 27 01:26:49 PM PST 23 |
Dec 27 01:26:56 PM PST 23 |
2477355960 ps |
| T469 |
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3593951911 |
|
|
Dec 27 01:29:50 PM PST 23 |
Dec 27 01:29:58 PM PST 23 |
9096112311 ps |
| T470 |
/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.3284517563 |
|
|
Dec 27 01:28:07 PM PST 23 |
Dec 27 01:28:12 PM PST 23 |
2042793819 ps |
| T75 |
/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1256822807 |
|
|
Dec 27 01:28:17 PM PST 23 |
Dec 27 01:28:19 PM PST 23 |
6856561959 ps |
| T471 |
/workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2910740719 |
|
|
Dec 27 01:27:42 PM PST 23 |
Dec 27 01:27:54 PM PST 23 |
2838001752 ps |
| T153 |
/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.229922163 |
|
|
Dec 27 01:28:27 PM PST 23 |
Dec 27 01:29:27 PM PST 23 |
108769973333 ps |
| T472 |
/workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3143975599 |
|
|
Dec 27 01:28:54 PM PST 23 |
Dec 27 01:29:02 PM PST 23 |
2612671309 ps |
| T473 |
/workspace/coverage/default/32.sysrst_ctrl_edge_detect.838651343 |
|
|
Dec 27 01:28:46 PM PST 23 |
Dec 27 01:28:48 PM PST 23 |
3654646239 ps |
| T251 |
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2095042864 |
|
|
Dec 27 01:30:11 PM PST 23 |
Dec 27 01:39:34 PM PST 23 |
211371324814 ps |
| T474 |
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.4187539997 |
|
|
Dec 27 01:29:40 PM PST 23 |
Dec 27 01:29:44 PM PST 23 |
4609981490 ps |
| T475 |
/workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3157640182 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:01 PM PST 23 |
5189160117 ps |
| T476 |
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3426882449 |
|
|
Dec 27 01:29:18 PM PST 23 |
Dec 27 01:29:24 PM PST 23 |
2013256058 ps |
| T477 |
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3432537842 |
|
|
Dec 27 01:30:18 PM PST 23 |
Dec 27 01:30:33 PM PST 23 |
4453328491 ps |
| T145 |
/workspace/coverage/default/21.sysrst_ctrl_edge_detect.2816959872 |
|
|
Dec 27 01:27:55 PM PST 23 |
Dec 27 01:30:27 PM PST 23 |
308329908272 ps |
| T478 |
/workspace/coverage/default/21.sysrst_ctrl_smoke.2124172972 |
|
|
Dec 27 01:29:01 PM PST 23 |
Dec 27 01:29:04 PM PST 23 |
2128987843 ps |
| T479 |
/workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.318371800 |
|
|
Dec 27 01:28:12 PM PST 23 |
Dec 27 01:28:17 PM PST 23 |
2616011435 ps |
| T480 |
/workspace/coverage/default/27.sysrst_ctrl_pin_override_test.3415301689 |
|
|
Dec 27 01:28:47 PM PST 23 |
Dec 27 01:28:50 PM PST 23 |
2532813411 ps |
| T481 |
/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3214789619 |
|
|
Dec 27 01:28:16 PM PST 23 |
Dec 27 01:28:23 PM PST 23 |
2033200727 ps |
| T146 |
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.1224839580 |
|
|
Dec 27 01:29:54 PM PST 23 |
Dec 27 01:30:06 PM PST 23 |
3245639938 ps |
| T482 |
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.399721288 |
|
|
Dec 27 01:30:03 PM PST 23 |
Dec 27 01:30:06 PM PST 23 |
2621776630 ps |
| T483 |
/workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1424535847 |
|
|
Dec 27 01:29:04 PM PST 23 |
Dec 27 01:29:14 PM PST 23 |
3457316493 ps |
| T245 |
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1909762496 |
|
|
Dec 27 01:29:30 PM PST 23 |
Dec 27 01:30:44 PM PST 23 |
148485083281 ps |
| T484 |
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3589082232 |
|
|
Dec 27 01:29:26 PM PST 23 |
Dec 27 01:29:33 PM PST 23 |
2015781493 ps |
| T485 |
/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3109087488 |
|
|
Dec 27 01:27:42 PM PST 23 |
Dec 27 01:27:50 PM PST 23 |
2515950246 ps |
| T486 |
/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3652996782 |
|
|
Dec 27 01:28:04 PM PST 23 |
Dec 27 01:28:07 PM PST 23 |
2036088440 ps |
| T487 |
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1360493982 |
|
|
Dec 27 01:29:24 PM PST 23 |
Dec 27 01:29:28 PM PST 23 |
2494725096 ps |
| T488 |
/workspace/coverage/default/19.sysrst_ctrl_alert_test.1832210117 |
|
|
Dec 27 01:28:16 PM PST 23 |
Dec 27 01:28:23 PM PST 23 |
2015898305 ps |
| T489 |
/workspace/coverage/default/35.sysrst_ctrl_pin_access_test.706021626 |
|
|
Dec 27 01:29:07 PM PST 23 |
Dec 27 01:29:14 PM PST 23 |
2260452734 ps |
| T490 |
/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1567305777 |
|
|
Dec 27 01:26:51 PM PST 23 |
Dec 27 01:26:58 PM PST 23 |
2525899491 ps |
| T491 |
/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1251940378 |
|
|
Dec 27 01:28:56 PM PST 23 |
Dec 27 01:29:04 PM PST 23 |
5899422413 ps |
| T342 |
/workspace/coverage/default/32.sysrst_ctrl_stress_all.2585011705 |
|
|
Dec 27 01:28:48 PM PST 23 |
Dec 27 01:30:03 PM PST 23 |
497046907872 ps |
| T164 |
/workspace/coverage/default/23.sysrst_ctrl_edge_detect.4041598743 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:38:00 PM PST 23 |
238354307194 ps |
| T215 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all.2034158634 |
|
|
Dec 27 01:28:39 PM PST 23 |
Dec 27 01:28:47 PM PST 23 |
11598604556 ps |
| T216 |
/workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2747537289 |
|
|
Dec 27 01:28:50 PM PST 23 |
Dec 27 01:28:58 PM PST 23 |
2507831969 ps |
| T217 |
/workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2702499017 |
|
|
Dec 27 01:28:46 PM PST 23 |
Dec 27 01:28:56 PM PST 23 |
3443907139 ps |
| T218 |
/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2141793782 |
|
|
Dec 27 01:27:42 PM PST 23 |
Dec 27 01:28:08 PM PST 23 |
45554562918 ps |
| T165 |
/workspace/coverage/default/22.sysrst_ctrl_stress_all.1033810488 |
|
|
Dec 27 01:27:46 PM PST 23 |
Dec 27 01:28:22 PM PST 23 |
11809576948 ps |
| T219 |
/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2963954551 |
|
|
Dec 27 01:29:38 PM PST 23 |
Dec 27 01:29:46 PM PST 23 |
5104275904 ps |
| T220 |
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2659427421 |
|
|
Dec 27 01:30:10 PM PST 23 |
Dec 27 01:30:15 PM PST 23 |
5098223483 ps |
| T221 |
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3479924738 |
|
|
Dec 27 01:29:16 PM PST 23 |
Dec 27 01:29:19 PM PST 23 |
2932657091 ps |
| T222 |
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.4179751909 |
|
|
Dec 27 01:29:44 PM PST 23 |
Dec 27 01:29:52 PM PST 23 |
2442020886 ps |
| T332 |
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.744849972 |
|
|
Dec 27 01:28:33 PM PST 23 |
Dec 27 01:30:41 PM PST 23 |
108660885487 ps |
| T492 |
/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3192337192 |
|
|
Dec 27 01:28:56 PM PST 23 |
Dec 27 01:29:03 PM PST 23 |
2200690984 ps |
| T493 |
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1992975415 |
|
|
Dec 27 01:30:07 PM PST 23 |
Dec 27 01:30:17 PM PST 23 |
2014641543 ps |
| T494 |
/workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3279359396 |
|
|
Dec 27 01:27:45 PM PST 23 |
Dec 27 01:27:53 PM PST 23 |
2076112203 ps |
| T495 |
/workspace/coverage/default/28.sysrst_ctrl_stress_all.1822332889 |
|
|
Dec 27 01:28:11 PM PST 23 |
Dec 27 01:28:24 PM PST 23 |
9699493342 ps |
| T128 |
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.4192509989 |
|
|
Dec 27 01:27:41 PM PST 23 |
Dec 27 01:28:52 PM PST 23 |
27828913293 ps |
| T496 |
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2225156358 |
|
|
Dec 27 01:29:57 PM PST 23 |
Dec 27 01:30:02 PM PST 23 |
2031915312 ps |
| T497 |
/workspace/coverage/default/35.sysrst_ctrl_stress_all.2868375038 |
|
|
Dec 27 01:28:53 PM PST 23 |
Dec 27 01:29:16 PM PST 23 |
8505508331 ps |
| T498 |
/workspace/coverage/default/31.sysrst_ctrl_alert_test.1884281238 |
|
|
Dec 27 01:29:01 PM PST 23 |
Dec 27 01:29:06 PM PST 23 |
2014560446 ps |
| T499 |
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3698845410 |
|
|
Dec 27 01:29:26 PM PST 23 |
Dec 27 01:29:31 PM PST 23 |
2475181185 ps |
| T313 |
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1161923622 |
|
|
Dec 27 01:29:26 PM PST 23 |
Dec 27 01:32:15 PM PST 23 |
68451457377 ps |
| T500 |
/workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3076662345 |
|
|
Dec 27 01:28:06 PM PST 23 |
Dec 27 01:28:09 PM PST 23 |
3176123189 ps |
| T501 |
/workspace/coverage/default/18.sysrst_ctrl_combo_detect.62600549 |
|
|
Dec 27 01:28:03 PM PST 23 |
Dec 27 01:28:48 PM PST 23 |
31475321960 ps |
| T502 |
/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.1635822557 |
|
|
Dec 27 01:28:30 PM PST 23 |
Dec 27 01:28:38 PM PST 23 |
2509880247 ps |
| T503 |
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.257429613 |
|
|
Dec 27 01:30:12 PM PST 23 |
Dec 27 01:30:44 PM PST 23 |
51800660821 ps |
| T504 |
/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2511540200 |
|
|
Dec 27 01:28:14 PM PST 23 |
Dec 27 01:28:30 PM PST 23 |
3568582984 ps |
| T505 |
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3592516397 |
|
|
Dec 27 01:30:06 PM PST 23 |
Dec 27 01:30:16 PM PST 23 |
3415068195 ps |
| T321 |
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.591195117 |
|
|
Dec 27 01:29:56 PM PST 23 |
Dec 27 01:30:21 PM PST 23 |
72683783223 ps |
| T506 |
/workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1549612447 |
|
|
Dec 27 01:26:46 PM PST 23 |
Dec 27 01:26:54 PM PST 23 |
2511032799 ps |
| T507 |
/workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.1550941078 |
|
|
Dec 27 01:28:25 PM PST 23 |
Dec 27 01:37:07 PM PST 23 |
276612534340 ps |
| T186 |
/workspace/coverage/default/0.sysrst_ctrl_edge_detect.3268697979 |
|
|
Dec 27 01:26:54 PM PST 23 |
Dec 27 01:27:07 PM PST 23 |
4149416993 ps |
| T508 |
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.72404684 |
|
|
Dec 27 01:27:51 PM PST 23 |
Dec 27 01:27:58 PM PST 23 |
2136279083 ps |
| T509 |
/workspace/coverage/default/30.sysrst_ctrl_smoke.2886959874 |
|
|
Dec 27 01:28:22 PM PST 23 |
Dec 27 01:28:25 PM PST 23 |
2130958039 ps |
| T510 |
/workspace/coverage/default/39.sysrst_ctrl_stress_all.151861683 |
|
|
Dec 27 01:29:20 PM PST 23 |
Dec 27 01:32:23 PM PST 23 |
271300623261 ps |
| T511 |
/workspace/coverage/default/35.sysrst_ctrl_alert_test.470094985 |
|
|
Dec 27 01:28:58 PM PST 23 |
Dec 27 01:29:03 PM PST 23 |
2016242251 ps |
| T512 |
/workspace/coverage/default/12.sysrst_ctrl_pin_override_test.3665570717 |
|
|
Dec 27 01:27:51 PM PST 23 |
Dec 27 01:27:54 PM PST 23 |
2531146240 ps |
| T513 |
/workspace/coverage/default/26.sysrst_ctrl_edge_detect.2541698850 |
|
|
Dec 27 01:28:50 PM PST 23 |
Dec 27 01:28:53 PM PST 23 |
2908256712 ps |
| T514 |
/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1117338202 |
|
|
Dec 27 01:27:53 PM PST 23 |
Dec 27 01:27:56 PM PST 23 |
2264324033 ps |
| T515 |
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2932049987 |
|
|
Dec 27 01:29:41 PM PST 23 |
Dec 27 01:29:44 PM PST 23 |
3370822637 ps |
| T516 |
/workspace/coverage/default/14.sysrst_ctrl_pin_override_test.3151184180 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:00 PM PST 23 |
2536474697 ps |
| T517 |
/workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4169331412 |
|
|
Dec 27 01:27:21 PM PST 23 |
Dec 27 01:27:49 PM PST 23 |
36507669025 ps |
| T324 |
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.737973725 |
|
|
Dec 27 01:30:04 PM PST 23 |
Dec 27 01:35:04 PM PST 23 |
107704220723 ps |
| T518 |
/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.4075896496 |
|
|
Dec 27 01:29:04 PM PST 23 |
Dec 27 01:30:01 PM PST 23 |
22332460497 ps |
| T519 |
/workspace/coverage/default/29.sysrst_ctrl_pin_override_test.990222731 |
|
|
Dec 27 01:28:44 PM PST 23 |
Dec 27 01:28:47 PM PST 23 |
2552007138 ps |
| T317 |
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2187200292 |
|
|
Dec 27 01:30:18 PM PST 23 |
Dec 27 01:31:17 PM PST 23 |
73728449888 ps |
| T520 |
/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.207320499 |
|
|
Dec 27 01:29:02 PM PST 23 |
Dec 27 01:29:09 PM PST 23 |
2151805222 ps |
| T92 |
/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3128308175 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:59 PM PST 23 |
181529404957 ps |
| T190 |
/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.3204604174 |
|
|
Dec 27 01:28:17 PM PST 23 |
Dec 27 01:28:24 PM PST 23 |
2511206046 ps |
| T191 |
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2110496986 |
|
|
Dec 27 01:30:10 PM PST 23 |
Dec 27 01:30:14 PM PST 23 |
3176377142 ps |
| T192 |
/workspace/coverage/default/45.sysrst_ctrl_alert_test.591447661 |
|
|
Dec 27 01:29:29 PM PST 23 |
Dec 27 01:29:36 PM PST 23 |
2010959282 ps |
| T193 |
/workspace/coverage/default/9.sysrst_ctrl_alert_test.634923709 |
|
|
Dec 27 01:27:54 PM PST 23 |
Dec 27 01:27:58 PM PST 23 |
2039059136 ps |
| T166 |
/workspace/coverage/default/44.sysrst_ctrl_stress_all.830186860 |
|
|
Dec 27 01:29:24 PM PST 23 |
Dec 27 01:37:17 PM PST 23 |
1045841803469 ps |
| T194 |
/workspace/coverage/default/20.sysrst_ctrl_alert_test.1018798526 |
|
|
Dec 27 01:28:51 PM PST 23 |
Dec 27 01:28:55 PM PST 23 |
2027289183 ps |
| T195 |
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2609004421 |
|
|
Dec 27 01:30:07 PM PST 23 |
Dec 27 01:31:42 PM PST 23 |
51322310875 ps |
| T196 |
/workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2356858306 |
|
|
Dec 27 01:27:59 PM PST 23 |
Dec 27 01:28:06 PM PST 23 |
2134419691 ps |
| T197 |
/workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2943270748 |
|
|
Dec 27 01:28:05 PM PST 23 |
Dec 27 01:28:08 PM PST 23 |
3398343755 ps |
| T521 |
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2476033010 |
|
|
Dec 27 01:27:52 PM PST 23 |
Dec 27 01:27:58 PM PST 23 |
3990923877 ps |
| T522 |
/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.745502482 |
|
|
Dec 27 01:28:39 PM PST 23 |
Dec 27 01:28:43 PM PST 23 |
2482508934 ps |
| T318 |
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3583913556 |
|
|
Dec 27 01:29:57 PM PST 23 |
Dec 27 01:31:22 PM PST 23 |
108880227448 ps |
| T523 |
/workspace/coverage/default/23.sysrst_ctrl_alert_test.834638584 |
|
|
Dec 27 01:28:28 PM PST 23 |
Dec 27 01:28:39 PM PST 23 |
2012237416 ps |
| T524 |
/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3825597391 |
|
|
Dec 27 01:28:33 PM PST 23 |
Dec 27 01:28:37 PM PST 23 |
2614921286 ps |
| T252 |
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.3835961321 |
|
|
Dec 27 01:29:55 PM PST 23 |
Dec 27 01:30:57 PM PST 23 |
89695600900 ps |
| T525 |
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.423095146 |
|
|
Dec 27 01:29:54 PM PST 23 |
Dec 27 01:30:06 PM PST 23 |
48205826176 ps |
| T122 |
/workspace/coverage/default/42.sysrst_ctrl_stress_all.4166486630 |
|
|
Dec 27 01:29:12 PM PST 23 |
Dec 27 01:29:22 PM PST 23 |
10767966865 ps |
| T329 |
/workspace/coverage/default/3.sysrst_ctrl_combo_detect.763734251 |
|
|
Dec 27 01:26:53 PM PST 23 |
Dec 27 01:28:50 PM PST 23 |
187463571198 ps |
| T526 |
/workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1972121594 |
|
|
Dec 27 01:29:39 PM PST 23 |
Dec 27 01:29:51 PM PST 23 |
3943265383 ps |
| T527 |
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1932806868 |
|
|
Dec 27 01:27:59 PM PST 23 |
Dec 27 01:28:51 PM PST 23 |
20279571597 ps |
| T528 |
/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1945773440 |
|
|
Dec 27 01:26:53 PM PST 23 |
Dec 27 01:27:10 PM PST 23 |
48873215676 ps |
| T240 |
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3498203121 |
|
|
Dec 27 01:29:45 PM PST 23 |
Dec 27 01:30:31 PM PST 23 |
82832546338 ps |
| T529 |
/workspace/coverage/default/5.sysrst_ctrl_smoke.3760245375 |
|
|
Dec 27 01:26:53 PM PST 23 |
Dec 27 01:26:57 PM PST 23 |
2117265835 ps |
| T326 |
/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2983506022 |
|
|
Dec 27 01:27:18 PM PST 23 |
Dec 27 01:29:53 PM PST 23 |
117643649182 ps |
| T530 |
/workspace/coverage/default/3.sysrst_ctrl_smoke.210371986 |
|
|
Dec 27 01:27:21 PM PST 23 |
Dec 27 01:27:26 PM PST 23 |
2116076106 ps |
| T531 |
/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.4100784168 |
|
|
Dec 27 01:29:31 PM PST 23 |
Dec 27 01:29:43 PM PST 23 |
2513790983 ps |
| T308 |
/workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.313946669 |
|
|
Dec 27 01:29:09 PM PST 23 |
Dec 27 01:29:50 PM PST 23 |
62955402172 ps |
| T175 |
/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3805226004 |
|
|
Dec 27 01:28:21 PM PST 23 |
Dec 27 01:28:30 PM PST 23 |
3779136544 ps |
| T176 |
/workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.1009717764 |
|
|
Dec 27 01:27:55 PM PST 23 |
Dec 27 01:28:01 PM PST 23 |
2465824148 ps |
| T93 |
/workspace/coverage/default/32.sysrst_ctrl_combo_detect.2284335882 |
|
|
Dec 27 01:28:51 PM PST 23 |
Dec 27 01:29:37 PM PST 23 |
70211466757 ps |
| T532 |
/workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3777286266 |
|
|
Dec 27 01:27:34 PM PST 23 |
Dec 27 01:27:39 PM PST 23 |
2968234505 ps |
| T533 |
/workspace/coverage/default/40.sysrst_ctrl_smoke.2535028625 |
|
|
Dec 27 01:29:29 PM PST 23 |
Dec 27 01:29:34 PM PST 23 |
2113804253 ps |
| T534 |
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.533119229 |
|
|
Dec 27 01:29:56 PM PST 23 |
Dec 27 01:30:00 PM PST 23 |
2289910264 ps |
| T535 |
/workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.628745481 |
|
|
Dec 27 01:27:55 PM PST 23 |
Dec 27 01:28:05 PM PST 23 |
3123110268 ps |
| T131 |
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1116098126 |
|
|
Dec 27 01:29:22 PM PST 23 |
Dec 27 01:29:27 PM PST 23 |
219042519336 ps |
| T536 |
/workspace/coverage/default/15.sysrst_ctrl_stress_all.2106655129 |
|
|
Dec 27 01:28:16 PM PST 23 |
Dec 27 01:28:23 PM PST 23 |
16281545668 ps |
| T537 |
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.480394603 |
|
|
Dec 27 01:26:53 PM PST 23 |
Dec 27 01:27:03 PM PST 23 |
2458738987 ps |
| T538 |
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1032722878 |
|
|
Dec 27 01:29:17 PM PST 23 |
Dec 27 01:29:29 PM PST 23 |
3782763754 ps |
| T208 |
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3313404030 |
|
|
Dec 27 01:29:47 PM PST 23 |
Dec 27 01:29:51 PM PST 23 |
2990729628 ps |
| T227 |
/workspace/coverage/default/24.sysrst_ctrl_combo_detect.3630287504 |
|
|
Dec 27 01:28:08 PM PST 23 |
Dec 27 01:28:34 PM PST 23 |
52680737799 ps |
| T228 |
/workspace/coverage/default/17.sysrst_ctrl_smoke.3376932587 |
|
|
Dec 27 01:27:50 PM PST 23 |
Dec 27 01:27:53 PM PST 23 |
2125047130 ps |
| T229 |
/workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1224167598 |
|
|
Dec 27 01:29:07 PM PST 23 |
Dec 27 01:29:10 PM PST 23 |
2750218996 ps |
| T167 |
/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.245983431 |
|
|
Dec 27 01:28:41 PM PST 23 |
Dec 27 01:30:34 PM PST 23 |
89146549851 ps |
| T169 |
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3430478788 |
|
|
Dec 27 01:30:06 PM PST 23 |
Dec 27 01:30:18 PM PST 23 |
2509919771 ps |
| T170 |
/workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.373870485 |
|
|
Dec 27 01:28:00 PM PST 23 |
Dec 27 01:28:09 PM PST 23 |
2440930232 ps |
| T171 |
/workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.4051877262 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:05 PM PST 23 |
3702194253 ps |
| T172 |
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1441685556 |
|
|
Dec 27 01:30:01 PM PST 23 |
Dec 27 01:31:09 PM PST 23 |
77863961116 ps |
| T173 |
/workspace/coverage/default/0.sysrst_ctrl_stress_all.1173328542 |
|
|
Dec 27 01:27:03 PM PST 23 |
Dec 27 01:27:44 PM PST 23 |
14524069042 ps |
| T174 |
/workspace/coverage/default/6.sysrst_ctrl_smoke.1914622518 |
|
|
Dec 27 01:27:44 PM PST 23 |
Dec 27 01:27:49 PM PST 23 |
2141439937 ps |
| T539 |
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2614928226 |
|
|
Dec 27 01:29:52 PM PST 23 |
Dec 27 01:30:02 PM PST 23 |
11053305431 ps |
| T540 |
/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1654976853 |
|
|
Dec 27 01:27:49 PM PST 23 |
Dec 27 01:28:49 PM PST 23 |
35239198143 ps |
| T541 |
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1830397819 |
|
|
Dec 27 01:29:13 PM PST 23 |
Dec 27 01:30:20 PM PST 23 |
28330013343 ps |
| T542 |
/workspace/coverage/default/31.sysrst_ctrl_edge_detect.2266994782 |
|
|
Dec 27 01:29:07 PM PST 23 |
Dec 27 01:29:16 PM PST 23 |
3090103100 ps |
| T543 |
/workspace/coverage/default/32.sysrst_ctrl_alert_test.1101684705 |
|
|
Dec 27 01:28:45 PM PST 23 |
Dec 27 01:28:52 PM PST 23 |
2013282293 ps |
| T76 |
/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1322982499 |
|
|
Dec 27 01:27:57 PM PST 23 |
Dec 27 01:28:04 PM PST 23 |
6805981149 ps |
| T544 |
/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.687320277 |
|
|
Dec 27 01:29:21 PM PST 23 |
Dec 27 01:29:29 PM PST 23 |
2435587333 ps |
| T545 |
/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.1707784740 |
|
|
Dec 27 01:27:47 PM PST 23 |
Dec 27 01:27:52 PM PST 23 |
2555588388 ps |
| T546 |
/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2773188480 |
|
|
Dec 27 01:28:44 PM PST 23 |
Dec 27 01:28:46 PM PST 23 |
2221505240 ps |
| T547 |
/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2573335942 |
|
|
Dec 27 01:28:48 PM PST 23 |
Dec 27 01:28:57 PM PST 23 |
2978068976 ps |
| T548 |
/workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2663494770 |
|
|
Dec 27 01:27:56 PM PST 23 |
Dec 27 01:28:05 PM PST 23 |
2610075335 ps |
| T549 |
/workspace/coverage/default/25.sysrst_ctrl_smoke.1058705325 |
|
|
Dec 27 01:28:11 PM PST 23 |
Dec 27 01:28:13 PM PST 23 |
2156005428 ps |
| T550 |
/workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.4231478145 |
|
|
Dec 27 01:28:30 PM PST 23 |
Dec 27 01:28:32 PM PST 23 |
2482685375 ps |
| T551 |
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2249514471 |
|
|
Dec 27 01:28:36 PM PST 23 |
Dec 27 01:28:44 PM PST 23 |
2614866150 ps |
| T552 |
/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2049542974 |
|
|
Dec 27 01:29:13 PM PST 23 |
Dec 27 01:29:16 PM PST 23 |
3301472724 ps |
| T553 |
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4181079668 |
|
|
Dec 27 01:28:36 PM PST 23 |
Dec 27 01:28:40 PM PST 23 |
4232024084 ps |
| T554 |
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1548520298 |
|
|
Dec 27 01:27:56 PM PST 23 |
Dec 27 01:28:07 PM PST 23 |
5115698411 ps |
| T555 |
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2675426810 |
|
|
Dec 27 01:29:54 PM PST 23 |
Dec 27 01:30:50 PM PST 23 |
36312403287 ps |
| T64 |
/workspace/coverage/default/49.sysrst_ctrl_stress_all.1763119120 |
|
|
Dec 27 01:30:09 PM PST 23 |
Dec 27 01:38:25 PM PST 23 |
204742538205 ps |
| T339 |
/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3547838289 |
|
|
Dec 27 01:29:31 PM PST 23 |
Dec 27 01:30:14 PM PST 23 |
58575582353 ps |
| T556 |
/workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2671845021 |
|
|
Dec 27 01:27:47 PM PST 23 |
Dec 27 01:27:51 PM PST 23 |
2289158293 ps |
| T557 |
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4023294437 |
|
|
Dec 27 01:29:39 PM PST 23 |
Dec 27 01:30:29 PM PST 23 |
48517582383 ps |
| T558 |
/workspace/coverage/default/11.sysrst_ctrl_edge_detect.4266403362 |
|
|
Dec 27 01:27:46 PM PST 23 |
Dec 27 01:27:52 PM PST 23 |
2433809319 ps |
| T559 |
/workspace/coverage/default/27.sysrst_ctrl_edge_detect.2695075859 |
|
|
Dec 27 01:29:10 PM PST 23 |
Dec 27 01:29:14 PM PST 23 |
3166049525 ps |
| T116 |
/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1306904015 |
|
|
Dec 27 01:29:12 PM PST 23 |
Dec 27 01:29:15 PM PST 23 |
4215381633 ps |
| T560 |
/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2244499743 |
|
|
Dec 27 01:27:00 PM PST 23 |
Dec 27 01:27:39 PM PST 23 |
27352500872 ps |
| T94 |
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1615364179 |
|
|
Dec 27 01:29:55 PM PST 23 |
Dec 27 01:33:03 PM PST 23 |
71369589275 ps |
| T561 |
/workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3605624930 |
|
|
Dec 27 01:28:44 PM PST 23 |
Dec 27 01:29:52 PM PST 23 |
24416417296 ps |