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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.14 98.91 96.33 100.00 97.44 98.29 99.63 89.38


Total test records in report: 912
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T562 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.2763724841 Dec 27 01:29:00 PM PST 23 Dec 27 01:29:02 PM PST 23 2097951901 ps
T563 /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1939125284 Dec 27 01:30:13 PM PST 23 Dec 27 01:30:34 PM PST 23 117868096814 ps
T564 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1950066390 Dec 27 01:30:07 PM PST 23 Dec 27 01:32:13 PM PST 23 64420269341 ps
T565 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2157616720 Dec 27 01:28:24 PM PST 23 Dec 27 01:29:35 PM PST 23 25832657509 ps
T566 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2465600077 Dec 27 01:26:54 PM PST 23 Dec 27 01:27:04 PM PST 23 2480287406 ps
T567 /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2493566299 Dec 27 01:28:00 PM PST 23 Dec 27 01:28:12 PM PST 23 3658830107 ps
T568 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1648945443 Dec 27 01:28:45 PM PST 23 Dec 27 01:28:47 PM PST 23 2659301614 ps
T569 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1040310883 Dec 27 01:26:50 PM PST 23 Dec 27 01:27:55 PM PST 23 26080377393 ps
T570 /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1237930520 Dec 27 01:28:42 PM PST 23 Dec 27 01:28:50 PM PST 23 2465927416 ps
T65 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2318724055 Dec 27 01:26:51 PM PST 23 Dec 27 01:32:58 PM PST 23 138994296682 ps
T307 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2199130851 Dec 27 01:29:47 PM PST 23 Dec 27 01:30:16 PM PST 23 190250782983 ps
T571 /workspace/coverage/default/39.sysrst_ctrl_smoke.2398224731 Dec 27 01:29:52 PM PST 23 Dec 27 01:29:55 PM PST 23 2144151966 ps
T572 /workspace/coverage/default/18.sysrst_ctrl_alert_test.3910651344 Dec 27 01:28:18 PM PST 23 Dec 27 01:28:21 PM PST 23 2023373066 ps
T305 /workspace/coverage/default/7.sysrst_ctrl_stress_all.2606101566 Dec 27 01:27:48 PM PST 23 Dec 27 01:28:36 PM PST 23 109833226463 ps
T573 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2814178582 Dec 27 01:28:54 PM PST 23 Dec 27 01:29:05 PM PST 23 3597580040 ps
T574 /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2488920423 Dec 27 01:26:54 PM PST 23 Dec 27 01:26:57 PM PST 23 4787211912 ps
T575 /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2218718828 Dec 27 01:28:02 PM PST 23 Dec 27 01:28:12 PM PST 23 3325238170 ps
T576 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2439522393 Dec 27 01:27:48 PM PST 23 Dec 27 01:27:52 PM PST 23 4784455116 ps
T577 /workspace/coverage/default/4.sysrst_ctrl_smoke.585942975 Dec 27 01:27:57 PM PST 23 Dec 27 01:28:00 PM PST 23 2126616547 ps
T578 /workspace/coverage/default/40.sysrst_ctrl_stress_all.4238394802 Dec 27 01:29:22 PM PST 23 Dec 27 01:29:28 PM PST 23 6691546025 ps
T579 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1774167808 Dec 27 01:27:19 PM PST 23 Dec 27 01:27:25 PM PST 23 5384064558 ps
T580 /workspace/coverage/default/28.sysrst_ctrl_alert_test.2758307120 Dec 27 01:28:23 PM PST 23 Dec 27 01:28:27 PM PST 23 2022616376 ps
T581 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2851468029 Dec 27 01:27:15 PM PST 23 Dec 27 01:27:21 PM PST 23 2515243430 ps
T117 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1015028497 Dec 27 01:30:10 PM PST 23 Dec 27 01:30:20 PM PST 23 7588619549 ps
T582 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1454419952 Dec 27 01:28:10 PM PST 23 Dec 27 01:28:12 PM PST 23 2892970222 ps
T583 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.382510272 Dec 27 01:28:07 PM PST 23 Dec 27 01:28:09 PM PST 23 2158578715 ps
T168 /workspace/coverage/default/8.sysrst_ctrl_stress_all.3066724444 Dec 27 01:28:32 PM PST 23 Dec 27 01:28:48 PM PST 23 13043319448 ps
T584 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1010593071 Dec 27 01:28:43 PM PST 23 Dec 27 01:29:43 PM PST 23 96210265766 ps
T585 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4274056096 Dec 27 01:28:31 PM PST 23 Dec 27 01:28:37 PM PST 23 4033260970 ps
T586 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3860571990 Dec 27 01:29:30 PM PST 23 Dec 27 01:29:42 PM PST 23 2512270087 ps
T587 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.4290166657 Dec 27 01:29:52 PM PST 23 Dec 27 01:30:38 PM PST 23 59276895344 ps
T327 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2488421324 Dec 27 01:29:15 PM PST 23 Dec 27 01:31:51 PM PST 23 93255810843 ps
T588 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3582802526 Dec 27 01:27:49 PM PST 23 Dec 27 01:27:56 PM PST 23 3284648621 ps
T589 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3852757774 Dec 27 01:27:57 PM PST 23 Dec 27 01:28:06 PM PST 23 5077502885 ps
T590 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.4079590330 Dec 27 01:29:33 PM PST 23 Dec 27 01:29:41 PM PST 23 2093088904 ps
T591 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3255728232 Dec 27 01:28:20 PM PST 23 Dec 27 01:28:29 PM PST 23 3231541592 ps
T592 /workspace/coverage/default/24.sysrst_ctrl_alert_test.4033335625 Dec 27 01:28:36 PM PST 23 Dec 27 01:28:42 PM PST 23 2013917808 ps
T593 /workspace/coverage/default/12.sysrst_ctrl_smoke.2641691532 Dec 27 01:27:59 PM PST 23 Dec 27 01:28:04 PM PST 23 2115184578 ps
T594 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3668810496 Dec 27 01:27:43 PM PST 23 Dec 27 01:27:49 PM PST 23 2076850340 ps
T595 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1302234731 Dec 27 01:29:20 PM PST 23 Dec 27 01:29:25 PM PST 23 2616064774 ps
T596 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4028343098 Dec 27 01:29:46 PM PST 23 Dec 27 01:29:50 PM PST 23 2622555526 ps
T597 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.436621949 Dec 27 01:29:02 PM PST 23 Dec 27 01:31:05 PM PST 23 47335380710 ps
T598 /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4201179713 Dec 27 01:28:59 PM PST 23 Dec 27 01:29:01 PM PST 23 2629902734 ps
T599 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.787045330 Dec 27 01:29:52 PM PST 23 Dec 27 01:30:02 PM PST 23 2613021711 ps
T201 /workspace/coverage/default/36.sysrst_ctrl_stress_all.439526882 Dec 27 01:28:41 PM PST 23 Dec 27 01:29:14 PM PST 23 15018743560 ps
T600 /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.279112977 Dec 27 01:28:33 PM PST 23 Dec 27 01:28:37 PM PST 23 4952486166 ps
T601 /workspace/coverage/default/15.sysrst_ctrl_smoke.127771917 Dec 27 01:28:08 PM PST 23 Dec 27 01:28:15 PM PST 23 2114462882 ps
T147 /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4114917092 Dec 27 01:27:08 PM PST 23 Dec 27 01:27:41 PM PST 23 66552859591 ps
T602 /workspace/coverage/default/26.sysrst_ctrl_smoke.1334172024 Dec 27 01:28:56 PM PST 23 Dec 27 01:28:59 PM PST 23 2115580895 ps
T603 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3926200043 Dec 27 01:29:57 PM PST 23 Dec 27 01:35:11 PM PST 23 113098167572 ps
T604 /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2855949128 Dec 27 01:30:16 PM PST 23 Dec 27 01:30:21 PM PST 23 2099637196 ps
T605 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.816661664 Dec 27 01:28:12 PM PST 23 Dec 27 01:31:25 PM PST 23 73714190121 ps
T606 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.248190029 Dec 27 01:27:57 PM PST 23 Dec 27 01:28:00 PM PST 23 2370257248 ps
T607 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.4054065356 Dec 27 01:28:30 PM PST 23 Dec 27 01:28:37 PM PST 23 2458157108 ps
T608 /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1732750961 Dec 27 01:27:48 PM PST 23 Dec 27 01:27:54 PM PST 23 2480312248 ps
T256 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3039988261 Dec 27 01:27:53 PM PST 23 Dec 27 01:28:16 PM PST 23 42160534004 ps
T269 /workspace/coverage/default/29.sysrst_ctrl_alert_test.3341514646 Dec 27 01:28:57 PM PST 23 Dec 27 01:29:01 PM PST 23 2022126928 ps
T270 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.2818585503 Dec 27 01:28:10 PM PST 23 Dec 27 01:33:06 PM PST 23 121274127188 ps
T123 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.4031826184 Dec 27 01:28:36 PM PST 23 Dec 27 01:28:38 PM PST 23 10346197600 ps
T271 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2488548475 Dec 27 01:27:34 PM PST 23 Dec 27 01:27:42 PM PST 23 2512610578 ps
T272 /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3696007952 Dec 27 01:30:00 PM PST 23 Dec 27 01:31:33 PM PST 23 143290238826 ps
T609 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3088192285 Dec 27 01:28:20 PM PST 23 Dec 27 01:28:27 PM PST 23 3977704714 ps
T610 /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1079769880 Dec 27 01:28:38 PM PST 23 Dec 27 01:28:40 PM PST 23 3333161258 ps
T611 /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.492615096 Dec 27 01:28:55 PM PST 23 Dec 27 01:29:02 PM PST 23 2442223033 ps
T612 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3626452054 Dec 27 01:28:55 PM PST 23 Dec 27 01:29:13 PM PST 23 37770179948 ps
T613 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.274081115 Dec 27 01:26:55 PM PST 23 Dec 27 01:26:57 PM PST 23 5544969493 ps
T614 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2029004475 Dec 27 01:27:45 PM PST 23 Dec 27 01:27:52 PM PST 23 4070287959 ps
T253 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2635586227 Dec 27 01:28:55 PM PST 23 Dec 27 01:31:36 PM PST 23 230168079563 ps
T615 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.3596767612 Dec 27 01:29:07 PM PST 23 Dec 27 01:29:11 PM PST 23 2644335499 ps
T616 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.366301701 Dec 27 01:29:59 PM PST 23 Dec 27 01:30:09 PM PST 23 3910759031 ps
T114 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.600953013 Dec 27 01:29:17 PM PST 23 Dec 27 01:29:22 PM PST 23 3415348547 ps
T617 /workspace/coverage/default/16.sysrst_ctrl_stress_all.3230876433 Dec 27 01:27:42 PM PST 23 Dec 27 01:28:28 PM PST 23 15602416015 ps
T618 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3991969598 Dec 27 01:30:05 PM PST 23 Dec 27 01:30:15 PM PST 23 3474628576 ps
T619 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2831877590 Dec 27 01:29:01 PM PST 23 Dec 27 01:29:04 PM PST 23 5132969652 ps
T620 /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.859848772 Dec 27 01:28:51 PM PST 23 Dec 27 01:28:54 PM PST 23 3614423028 ps
T621 /workspace/coverage/default/7.sysrst_ctrl_alert_test.1278069297 Dec 27 01:27:28 PM PST 23 Dec 27 01:27:31 PM PST 23 2034211654 ps
T622 /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.3757999709 Dec 27 01:26:48 PM PST 23 Dec 27 01:26:53 PM PST 23 2662712419 ps
T187 /workspace/coverage/default/11.sysrst_ctrl_stress_all.574096344 Dec 27 01:27:54 PM PST 23 Dec 27 01:29:26 PM PST 23 128332904392 ps
T623 /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3109829724 Dec 27 01:27:00 PM PST 23 Dec 27 01:27:04 PM PST 23 2522543405 ps
T624 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.766491002 Dec 27 01:26:58 PM PST 23 Dec 27 01:27:05 PM PST 23 3178362431 ps
T625 /workspace/coverage/default/33.sysrst_ctrl_alert_test.2000553724 Dec 27 01:29:02 PM PST 23 Dec 27 01:29:08 PM PST 23 2012427562 ps
T311 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2678136054 Dec 27 01:29:51 PM PST 23 Dec 27 01:35:40 PM PST 23 140611883197 ps
T626 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.566046999 Dec 27 01:27:52 PM PST 23 Dec 27 01:28:02 PM PST 23 3293027995 ps
T115 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2538313896 Dec 27 01:26:52 PM PST 23 Dec 27 01:27:01 PM PST 23 8694321648 ps
T627 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.255457082 Dec 27 01:26:54 PM PST 23 Dec 27 01:26:59 PM PST 23 4168501188 ps
T628 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.402788334 Dec 27 01:28:34 PM PST 23 Dec 27 01:28:36 PM PST 23 2176060333 ps
T629 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4142970490 Dec 27 01:30:06 PM PST 23 Dec 27 01:31:45 PM PST 23 74446256255 ps
T630 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2210018342 Dec 27 01:29:58 PM PST 23 Dec 27 01:30:47 PM PST 23 33381488904 ps
T631 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.115216441 Dec 27 01:26:54 PM PST 23 Dec 27 01:30:08 PM PST 23 74122348724 ps
T632 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.1566068471 Dec 27 01:27:53 PM PST 23 Dec 27 01:27:55 PM PST 23 2111764710 ps
T633 /workspace/coverage/default/37.sysrst_ctrl_stress_all.1484430201 Dec 27 01:29:18 PM PST 23 Dec 27 01:29:59 PM PST 23 14762943978 ps
T254 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3592648362 Dec 27 01:27:59 PM PST 23 Dec 27 01:29:47 PM PST 23 174719085817 ps
T124 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1441128891 Dec 27 01:28:24 PM PST 23 Dec 27 01:28:54 PM PST 23 24866447834 ps
T178 /workspace/coverage/default/18.sysrst_ctrl_stress_all.927935684 Dec 27 01:28:06 PM PST 23 Dec 27 01:29:13 PM PST 23 1580012387259 ps
T179 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.544218360 Dec 27 01:27:45 PM PST 23 Dec 27 01:27:50 PM PST 23 2523082698 ps
T180 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.2128778504 Dec 27 01:27:00 PM PST 23 Dec 27 01:28:53 PM PST 23 703337255755 ps
T148 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.2614909823 Dec 27 01:27:36 PM PST 23 Dec 27 01:27:44 PM PST 23 1013483150616 ps
T181 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.238770069 Dec 27 01:28:46 PM PST 23 Dec 27 01:29:38 PM PST 23 23831049924 ps
T182 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.4020924102 Dec 27 01:28:21 PM PST 23 Dec 27 01:29:06 PM PST 23 63101992034 ps
T183 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.2338839132 Dec 27 01:29:42 PM PST 23 Dec 27 01:29:51 PM PST 23 2459541274 ps
T184 /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2435773382 Dec 27 01:28:16 PM PST 23 Dec 27 01:28:24 PM PST 23 2457753273 ps
T185 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1274567385 Dec 27 01:30:05 PM PST 23 Dec 27 01:30:14 PM PST 23 2524604138 ps
T634 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.1114413434 Dec 27 01:28:43 PM PST 23 Dec 27 01:28:47 PM PST 23 2121973685 ps
T635 /workspace/coverage/default/26.sysrst_ctrl_alert_test.1610360577 Dec 27 01:28:43 PM PST 23 Dec 27 01:28:44 PM PST 23 2110611918 ps
T636 /workspace/coverage/default/3.sysrst_ctrl_alert_test.1502596161 Dec 27 01:28:06 PM PST 23 Dec 27 01:28:08 PM PST 23 2070157169 ps
T95 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1484133572 Dec 27 01:28:34 PM PST 23 Dec 27 01:29:23 PM PST 23 76287175059 ps
T637 /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3111307244 Dec 27 01:29:15 PM PST 23 Dec 27 01:29:18 PM PST 23 2634809157 ps
T638 /workspace/coverage/default/47.sysrst_ctrl_stress_all.119746692 Dec 27 01:29:42 PM PST 23 Dec 27 01:29:45 PM PST 23 7144272343 ps
T639 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1337853000 Dec 27 01:28:35 PM PST 23 Dec 27 01:29:17 PM PST 23 78691169772 ps
T640 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.4286457032 Dec 27 01:29:08 PM PST 23 Dec 27 01:29:15 PM PST 23 4749511269 ps
T641 /workspace/coverage/default/37.sysrst_ctrl_smoke.2381395840 Dec 27 01:29:17 PM PST 23 Dec 27 01:29:21 PM PST 23 2115994160 ps
T642 /workspace/coverage/default/49.sysrst_ctrl_smoke.993274905 Dec 27 01:29:43 PM PST 23 Dec 27 01:29:48 PM PST 23 2119848137 ps
T643 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.587518169 Dec 27 01:27:55 PM PST 23 Dec 27 01:27:59 PM PST 23 3457727561 ps
T314 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2119459494 Dec 27 01:30:15 PM PST 23 Dec 27 01:31:04 PM PST 23 66905459028 ps
T644 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.4227700384 Dec 27 01:28:16 PM PST 23 Dec 27 01:30:55 PM PST 23 62189844195 ps
T645 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3191031052 Dec 27 01:28:00 PM PST 23 Dec 27 01:28:05 PM PST 23 3509338791 ps
T646 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.856663392 Dec 27 01:27:49 PM PST 23 Dec 27 01:27:55 PM PST 23 2463666062 ps
T647 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.136829402 Dec 27 01:30:18 PM PST 23 Dec 27 01:31:36 PM PST 23 29335071259 ps
T648 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1309720820 Dec 27 01:29:27 PM PST 23 Dec 27 01:29:29 PM PST 23 2184586252 ps
T649 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.902382624 Dec 27 01:29:04 PM PST 23 Dec 27 01:29:11 PM PST 23 2245625119 ps
T650 /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2395511242 Dec 27 01:29:38 PM PST 23 Dec 27 01:29:45 PM PST 23 3984423570 ps
T651 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.468841010 Dec 27 01:29:05 PM PST 23 Dec 27 01:29:47 PM PST 23 34809772088 ps
T652 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2909951868 Dec 27 01:29:37 PM PST 23 Dec 27 01:29:42 PM PST 23 3239945656 ps
T653 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3782732750 Dec 27 01:29:52 PM PST 23 Dec 27 01:30:29 PM PST 23 47375723241 ps
T654 /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3856521283 Dec 27 01:28:12 PM PST 23 Dec 27 01:28:15 PM PST 23 2926407771 ps
T655 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1661812863 Dec 27 01:28:19 PM PST 23 Dec 27 01:28:22 PM PST 23 2631409224 ps
T202 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1184586643 Dec 27 01:29:12 PM PST 23 Dec 27 01:31:40 PM PST 23 59676941882 ps
T656 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3610904313 Dec 27 01:28:07 PM PST 23 Dec 27 01:28:15 PM PST 23 2513177040 ps
T657 /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2451993238 Dec 27 01:28:29 PM PST 23 Dec 27 01:28:38 PM PST 23 2477384945 ps
T658 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.528526869 Dec 27 01:28:33 PM PST 23 Dec 27 01:28:40 PM PST 23 3968724039 ps
T125 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1682674484 Dec 27 01:28:39 PM PST 23 Dec 27 01:28:42 PM PST 23 3592853305 ps
T331 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.629390408 Dec 27 01:29:39 PM PST 23 Dec 27 01:33:29 PM PST 23 166628132795 ps
T659 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2643862443 Dec 27 01:30:13 PM PST 23 Dec 27 01:30:36 PM PST 23 28347598777 ps
T660 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2869480349 Dec 27 01:29:39 PM PST 23 Dec 27 01:56:19 PM PST 23 618807093826 ps
T661 /workspace/coverage/default/24.sysrst_ctrl_stress_all.3342301940 Dec 27 01:28:09 PM PST 23 Dec 27 01:28:35 PM PST 23 6965666359 ps
T662 /workspace/coverage/default/10.sysrst_ctrl_smoke.3199515859 Dec 27 01:27:47 PM PST 23 Dec 27 01:27:58 PM PST 23 2120096828 ps
T663 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3303276157 Dec 27 01:28:11 PM PST 23 Dec 27 01:29:39 PM PST 23 34121532629 ps
T664 /workspace/coverage/default/25.sysrst_ctrl_alert_test.4032292904 Dec 27 01:28:54 PM PST 23 Dec 27 01:29:01 PM PST 23 2008750687 ps
T665 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.144559331 Dec 27 01:27:06 PM PST 23 Dec 27 01:27:15 PM PST 23 2042588023 ps
T666 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.4266218084 Dec 27 01:29:26 PM PST 23 Dec 27 01:29:30 PM PST 23 3486734723 ps
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T723 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.116727693 Dec 27 01:29:03 PM PST 23 Dec 27 01:29:06 PM PST 23 2529173252 ps
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T731 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.2283489868 Dec 27 01:28:00 PM PST 23 Dec 27 01:28:06 PM PST 23 2513262689 ps
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T736 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.2230782693 Dec 27 01:28:07 PM PST 23 Dec 27 01:28:16 PM PST 23 2508099767 ps
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T742 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3182911450 Dec 27 01:27:18 PM PST 23 Dec 27 01:27:23 PM PST 23 2415833229 ps
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T748 /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.1790901458 Dec 27 01:28:03 PM PST 23 Dec 27 01:28:06 PM PST 23 2182120794 ps
T309 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3512802503 Dec 27 01:28:00 PM PST 23 Dec 27 01:29:44 PM PST 23 77835888914 ps
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T749 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1468947471 Dec 27 01:29:50 PM PST 23 Dec 27 01:30:01 PM PST 23 2611467891 ps
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T753 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3001769113 Dec 27 01:28:31 PM PST 23 Dec 27 01:28:33 PM PST 23 2213090458 ps
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T759 /workspace/coverage/default/5.sysrst_ctrl_alert_test.1540799593 Dec 27 01:27:55 PM PST 23 Dec 27 01:28:00 PM PST 23 2020005455 ps
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