Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T13

9

T17

36

T49

16

auto[1]

634

1

T13

3

T50

5

T21

6

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1993

1

T13

7

T17

32

T49

16

auto[1]

615

1

T13

5

T17

4

T21

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1911

1

T13

6

T17

34

T49

13

auto[1]

697

1

T13

6

T17

2

T49

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1975

1

T13

9

T17

36

T49

10

auto[1]

633

1

T13

3

T49

6

T80

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2403

1

T13

10

T17

34

T49

13

auto[1]

205

1

T13

2

T17

2

T49

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2334

1

T13

12

T17

31

T49

10

auto[1]

274

1

T17

5

T49

6

T80

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T13

12

T17

29

T49

13

auto[1]

177

1

T17

7

T49

3

T80

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2416

1

T13

11

T17

29

T49

16

auto[1]

192

1

T13

1

T17

7

T90

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2434

1

T13

8

T17

30

T49

16

auto[1]

174

1

T13

4

T17

6

T51

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1990

1

T13

12

T17

33

T49

16

auto[1]

618

1

T17

3

T50

6

T80

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

977

1

T50

11

T21

9

T22

17

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

60

1

T13

2

T123

10

T247

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T13

3

T316

10

T327

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T51

1

T247

1

T258

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

71

1

T90

2

T55

6

T123

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T331

5

T329

5

T76

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T13

1

T313

3

T329

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T51

14

T221

3

T246

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T124

5

T102

5

T316

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10

1

T227

4

T332

1

T257

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T333

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T246

1

T334

2

T335

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T331

2

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T17

4

T336

1

T337

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

120

1

T55

10

T57

2

T221

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

40

1

T49

3

T123

6

T315

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

31

1

T51

2

T123

2

T124

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T316

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

15

1

T247

4

T316

5

T257

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T247

2

T331

4

T338

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

12

1

T56

7

T332

2

T339

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T334

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

19

1

T49

3

T55

8

T315

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T80

3

T252

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

9

1

T327

3

T340

6

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T17

3

T257

1

T333

1

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

127

1

T56

7

T44

3

T246

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

87

1

T17

3

T124

5

T227

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T221

3

T94

2

T247

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

149

1

T49

3

T55

4

T102

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T136

7

T72

1

T341

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T80

3

T21

3

T51

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

37

1

T22

1

T55

4

T221

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

153

1

T13

1

T51

2

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

71

1

T50

5

T41

4

T124

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

79

1

T50

6

T57

2

T41

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T55

6

T41

3

T311

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

89

1

T49

3

T22

6

T55

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T123

2

T72

2

T81

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T311

2

T315

3

T255

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T136

3

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

129

1

T17

4

T22

10

T44

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

45

1

T21

6

T90

2

T342

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T51

7

T312

5

T342

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T227

11

T246

1

T72

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

60

1

T51

1

T48

1

T227

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T222

6

T216

3

T322

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T252

5

T316

5

T148

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T256

2

T318

2

T323

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

24

1

T13

2

T48

1

T44

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T91

3

T313

3

T343

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T123

13

T104

2

T148

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T248

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T247

1

T213

2

T344

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T13

3

T91

2

T317

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T123

10

T222

2

T312

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T345

1

T321

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded