Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1170

1

T16

16

T63

9

T245

14

auto[1]

1110

1

T16

4

T63

11

T245

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T16

6

T63

4

T245

5

from_0to1

539

1

T16

5

T63

4

T245

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T16

9

T63

9

T245

8

auto[1]

1159

1

T16

11

T63

11

T245

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T16

7

T63

10

T245

9

auto[1]

1149

1

T16

13

T63

10

T245

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T360

3

T67

1

T98

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T16

2

T245

1

T98

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T16

1

T63

1

T245

2

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T16

2

T360

1

T67

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T16

1

T360

1

T67

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T16

2

T63

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T16

1

T63

3

T245

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T245

2

T98

1

T48

1

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T245

2

T98

1

T147

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T63

1

T48

2

T286

2

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T67

2

T98

1

T99

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T16

1

T63

2

T360

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T245

1

T360

2

T99

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T98

1

T361

1

T362

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T360

1

T67

1

T98

2

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T16

1

T98

1

T48

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114

1

T16

12

T63

10

T245

11

auto[1]

1166

1

T16

8

T63

10

T245

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T16

5

T63

4

T245

6

from_0to1

527

1

T16

4

T63

5

T245

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T16

6

T63

8

T245

12

auto[1]

1133

1

T16

14

T63

12

T245

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T16

11

T63

9

T245

14

auto[1]

1144

1

T16

9

T63

11

T245

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T245

1

T360

1

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T16

1

T245

1

T98

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T16

2

T63

1

T245

1

auto[0]

from_1to0

auto[1]

auto[1]

82

1

T63

1

T98

1

T99

3

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T63

1

T245

1

T67

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T63

1

T245

1

T98

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T16

1

T245

1

T360

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T360

1

T98

1

T147

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T245

3

T147

2

T286

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T16

1

T67

2

T98

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T63

1

T360

1

T98

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T16

1

T63

1

T67

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T245

1

T98

1

T147

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T360

1

T98

1

T48

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T16

3

T360

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T63

3

T245

2

T48

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T16

10

T63

8

T245

13

auto[1]

1165

1

T16

10

T63

12

T245

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T16

4

T63

6

T245

5

from_0to1

553

1

T16

4

T63

6

T245

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1160

1

T16

9

T63

7

T245

12

auto[1]

1120

1

T16

11

T63

13

T245

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T16

8

T63

10

T245

9

auto[1]

1133

1

T16

12

T63

10

T245

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T16

1

T63

1

T67

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T16

1

T245

2

T67

1

auto[0]

from_1to0

auto[1]

auto[0]

79

1

T245

1

T360

2

T67

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T360

1

T135

1

T44

2

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T16

1

T63

1

T245

2

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T245

2

T360

1

T98

2

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T63

1

T147

1

T361

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T16

1

T67

1

T98

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T63

1

T245

1

T360

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T48

1

T147

1

T286

2

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T16

1

T63

1

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T16

1

T63

3

T245

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T360

3

T67

1

T48

2

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T16

2

T360

1

T67

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T63

2

T67

2

T99

2

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T63

2

T222

1

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T16

13

T63

9

T245

9

auto[1]

1140

1

T16

7

T63

11

T245

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

530

1

T16

4

T63

5

T245

6

from_0to1

532

1

T16

4

T63

5

T245

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T16

13

T63

11

T245

13

auto[1]

1138

1

T16

7

T63

9

T245

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1149

1

T16

12

T63

13

T245

10

auto[1]

1131

1

T16

8

T63

7

T245

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T16

2

T63

1

T98

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T16

1

T63

1

T245

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T63

1

T245

2

T360

2

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T360

1

T99

1

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T67

2

T48

2

T147

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T16

1

T245

1

T135

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T16

1

T63

1

T245

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T245

2

T67

1

T222

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T286

2

T222

2

T68

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T245

2

T98

1

T99

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T63

2

T245

1

T360

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T16

1

T67

1

T99

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T16

1

T63

1

T245

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T63

1

T98

1

T99

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T63

2

T360

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T16

1

T98

1

T99

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T16

12

T63

6

T245

12

auto[1]

1153

1

T16

8

T63

14

T245

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

560

1

T16

3

T63

5

T245

5

from_0to1

561

1

T16

4

T63

5

T245

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T16

13

T63

6

T245

7

auto[1]

1147

1

T16

7

T63

14

T245

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T16

11

T63

11

T245

11

auto[1]

1127

1

T16

9

T63

9

T245

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T16

1

T245

2

T99

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T245

1

T360

1

T286

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T360

1

T67

1

T99

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T63

2

T98

2

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T16

1

T63

1

T360

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T16

1

T67

1

T286

3

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T63

1

T245

2

T147

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T16

1

T63

1

T360

1

auto[1]

from_1to0

auto[0]

auto[0]

75

1

T16

1

T63

1

T360

2

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T67

3

T98

1

T48

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T16

1

T63

1

T360

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T63

1

T245

2

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T16

1

T63

1

T360

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T245

1

T360

3

T98

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T67

1

T98

1

T147

2

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T63

1

T245

2

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1117

1

T16

12

T63

12

T245

10

auto[1]

1163

1

T16

8

T63

8

T245

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T16

6

T63

5

T245

5

from_0to1

541

1

T16

5

T63

5

T245

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T16

10

T63

11

T245

12

auto[1]

1134

1

T16

10

T63

9

T245

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T16

9

T63

9

T245

10

auto[1]

1157

1

T16

11

T63

11

T245

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T63

1

T98

1

T99

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T16

4

T67

1

T98

2

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T16

2

T360

1

T99

2

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T245

1

T48

2

T147

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T99

3

T48

2

T147

1

auto[0]

from_0to1

auto[0]

auto[1]

81

1

T16

1

T63

1

T245

2

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T63

1

T245

1

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T63

1

T67

1

T98

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T63

1

T245

1

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T245

1

T360

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T63

1

T245

1

T360

2

auto[1]

from_1to0

auto[1]

auto[1]

82

1

T63

2

T245

1

T360

1

auto[1]

from_0to1

auto[0]

auto[0]

81

1

T16

2

T63

1

T360

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T245

1

T67

1

T147

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T16

1

T245

1

T360

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T16

1

T63

1

T360

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T16

10

T63

9

T245

9

auto[1]

1141

1

T16

10

T63

11

T245

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

546

1

T16

6

T63

6

T245

5

from_0to1

543

1

T16

7

T63

5

T245

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T16

8

T63

15

T245

12

auto[1]

1142

1

T16

12

T63

5

T245

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T16

9

T63

12

T245

9

auto[1]

1146

1

T16

11

T63

8

T245

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T63

1

T245

1

T363

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T16

1

T63

1

T245

1

auto[0]

from_1to0

auto[1]

auto[0]

90

1

T16

2

T63

1

T98

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T245

1

T99

1

T147

2

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T16

2

T63

1

T99

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T16

1

T67

1

T48

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T16

2

T360

1

T99

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T63

1

T245

1

T360

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T63

3

T245

1

T360

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T16

1

T360

1

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T360

3

T98

3

T48

1

auto[1]

from_1to0

auto[1]

auto[1]

72

1

T16

2

T245

1

T360

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T63

1

T360

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T16

1

T63

2

T245

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T98

2

T48

1

T147

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T16

1

T245

1

T360

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T16

12

T63

12

T245

5

auto[1]

1137

1

T16

8

T63

8

T245

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T16

4

T63

3

T245

4

from_0to1

543

1

T16

5

T63

4

T245

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T16

10

T63

9

T245

11

auto[1]

1188

1

T16

10

T63

11

T245

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1156

1

T16

10

T63

9

T245

11

auto[1]

1124

1

T16

10

T63

11

T245

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T16

1

T63

1

T360

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T360

1

T67

1

T98

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T63

1

T360

2

T98

1

auto[0]

from_1to0

auto[1]

auto[1]

87

1

T16

2

T98

1

T48

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T16

1

T360

1

T98

1

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T63

2

T245

1

T67

2

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T16

1

T63

1

T360

2

auto[0]

from_0to1

auto[1]

auto[1]

75

1

T16

1

T360

1

T99

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T63

1

T245

2

T360

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T245

1

T67

3

T99

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T16

1

T147

1

T222

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T245

1

T99

2

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T245

2

T67

2

T286

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T16

2

T67

1

T98

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T245

1

T48

1

T147

1

auto[1]

from_0to1

auto[1]

auto[1]

82

1

T63

1

T360

2

T286

1