Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122975

1

T6

1249

T1

200

T7

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141140	1			T6	1077		T1	133		T7	20
values[0x0]	67888	1			T6	838		T1	76		T7	11
values[0x1]	68864	1			T6	854		T1	95		T7	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125661	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152231

1

T6

1488

T1

240

T7

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2835	1			T24	3		T27	5		T28	2
valid_sources[0x01]	769	1			T6	9		T24	1		T27	3
valid_sources[0x02]	937	1			T6	39		T24	1		T27	3
valid_sources[0x03]	775	1			T6	4		T2	1		T24	1
valid_sources[0x04]	1242	1			T24	4		T27	2		T28	2
valid_sources[0x05]	1837	1			T6	25		T2	1		T27	1
valid_sources[0x06]	941	1			T2	1		T27	2		T28	2
valid_sources[0x07]	974	1			T24	2		T27	2		T3	3
valid_sources[0x08]	726	1			T6	11		T2	1		T24	2
valid_sources[0x09]	892	1			T6	71		T2	1		T24	1
valid_sources[0x0a]	1023	1			T6	9		T2	3		T24	2
valid_sources[0x0b]	2247	1			T27	1		T28	5		T3	4
valid_sources[0x0c]	1022	1			T6	16		T2	2		T24	1
valid_sources[0x0d]	845	1			T6	46		T24	1		T27	1
valid_sources[0x0e]	899	1			T6	17		T24	1		T27	4
valid_sources[0x0f]	770	1			T6	21		T27	2		T3	4
valid_sources[0x10]	1168	1			T26	8		T27	3		T28	5
valid_sources[0x11]	797	1			T6	21		T2	1		T24	1
valid_sources[0x12]	861	1			T6	2		T27	2		T28	5
valid_sources[0x13]	1085	1			T2	4		T24	1		T27	2
valid_sources[0x14]	822	1			T6	37		T27	4		T28	1
valid_sources[0x15]	706	1			T6	1		T24	1		T27	1
valid_sources[0x16]	880	1			T6	5		T24	1		T27	3
valid_sources[0x17]	865	1			T6	14		T2	2		T24	1
valid_sources[0x18]	729	1			T6	13		T2	1		T24	1
valid_sources[0x19]	833	1			T24	1		T27	1		T28	6
valid_sources[0x1a]	792	1			T6	12		T27	2		T28	1
valid_sources[0x1b]	2308	1			T27	3		T28	1		T3	4
valid_sources[0x1c]	713	1			T6	9		T27	1		T3	2
valid_sources[0x1d]	717	1			T24	1		T27	3		T28	1
valid_sources[0x1e]	794	1			T6	8		T2	1		T28	1
valid_sources[0x1f]	731	1			T2	1		T27	4		T28	2
valid_sources[0x20]	1739	1			T6	150		T2	1		T27	2
valid_sources[0x21]	1037	1			T6	6		T2	1		T24	1
valid_sources[0x22]	1729	1			T6	7		T2	1		T24	1
valid_sources[0x23]	1066	1			T6	21		T24	1		T27	1
valid_sources[0x24]	1225	1			T1	3		T2	1		T24	1
valid_sources[0x25]	849	1			T2	1		T26	1		T27	1
valid_sources[0x26]	1070	1			T6	44		T24	1		T27	4
valid_sources[0x27]	901	1			T24	1		T27	2		T28	3
valid_sources[0x28]	727	1			T6	9		T2	1		T27	1
valid_sources[0x29]	1140	1			T6	22		T2	1		T24	2
valid_sources[0x2a]	742	1			T2	1		T27	3		T28	3
valid_sources[0x2b]	848	1			T2	1		T27	2		T28	1
valid_sources[0x2c]	973	1			T6	9		T2	2		T24	3
valid_sources[0x2d]	943	1			T24	1		T28	5		T3	2
valid_sources[0x2e]	707	1			T27	1		T28	3		T3	4
valid_sources[0x2f]	1162	1			T2	1		T24	1		T27	2
valid_sources[0x30]	898	1			T6	21		T27	2		T28	1
valid_sources[0x31]	1161	1			T6	3		T2	1		T24	1
valid_sources[0x32]	793	1			T6	15		T27	2		T3	3
valid_sources[0x33]	1336	1			T1	78		T24	1		T28	3
valid_sources[0x34]	994	1			T24	1		T27	2		T28	4
valid_sources[0x35]	999	1			T27	4		T28	1		T3	8
valid_sources[0x36]	1010	1			T6	1		T2	2		T27	3
valid_sources[0x37]	902	1			T6	16		T24	2		T27	2
valid_sources[0x38]	853	1			T6	1		T2	2		T27	1
valid_sources[0x39]	807	1			T27	2		T28	5		T3	5
valid_sources[0x3a]	1029	1			T1	1		T2	1		T24	1
valid_sources[0x3b]	1277	1			T6	3		T24	3		T27	7
valid_sources[0x3c]	794	1			T6	16		T27	1		T28	2
valid_sources[0x3d]	1589	1			T6	44		T1	3		T2	1
valid_sources[0x3e]	923	1			T24	1		T3	6		T9	3
valid_sources[0x3f]	1158	1			T6	1		T24	1		T28	2
valid_sources[0x40]	799	1			T24	1		T27	4		T28	1
valid_sources[0x41]	1493	1			T6	4		T2	2		T27	3
valid_sources[0x42]	1190	1			T2	2		T24	2		T27	1
valid_sources[0x43]	876	1			T27	3		T28	1		T3	3
valid_sources[0x44]	1829	1			T6	11		T24	2		T27	3
valid_sources[0x45]	804	1			T2	1		T24	2		T28	4
valid_sources[0x46]	945	1			T2	1		T24	1		T27	1
valid_sources[0x47]	1002	1			T24	1		T27	3		T28	3
valid_sources[0x48]	2009	1			T6	1		T2	1		T24	1
valid_sources[0x49]	808	1			T6	5		T24	3		T27	3
valid_sources[0x4a]	1994	1			T6	37		T1	42		T27	2
valid_sources[0x4b]	859	1			T24	1		T27	3		T28	4
valid_sources[0x4c]	930	1			T24	3		T27	4		T28	1
valid_sources[0x4d]	1011	1			T6	34		T2	2		T24	3
valid_sources[0x4e]	1067	1			T24	1		T27	2		T28	7
valid_sources[0x4f]	849	1			T24	1		T27	3		T28	4
valid_sources[0x50]	756	1			T6	14		T24	1		T27	3
valid_sources[0x51]	1816	1			T6	25		T2	1		T24	2
valid_sources[0x52]	761	1			T1	2		T2	1		T24	2
valid_sources[0x53]	823	1			T6	11		T24	1		T27	1
valid_sources[0x54]	1506	1			T6	28		T2	1		T24	1
valid_sources[0x55]	1061	1			T2	1		T27	1		T28	2
valid_sources[0x56]	1402	1			T6	3		T2	2		T28	1
valid_sources[0x57]	797	1			T27	1		T28	6		T3	2
valid_sources[0x58]	716	1			T27	2		T28	5		T29	1
valid_sources[0x59]	960	1			T24	1		T27	3		T28	8
valid_sources[0x5a]	853	1			T6	36		T24	2		T27	1
valid_sources[0x5b]	818	1			T2	1		T24	1		T27	5
valid_sources[0x5c]	1039	1			T6	40		T2	1		T27	2
valid_sources[0x5d]	752	1			T24	1		T27	1		T28	5
valid_sources[0x5e]	828	1			T6	2		T27	2		T3	6
valid_sources[0x5f]	902	1			T6	23		T27	1		T28	1
valid_sources[0x60]	1447	1			T6	10		T24	1		T27	1
valid_sources[0x61]	1043	1			T2	1		T24	1		T27	3
valid_sources[0x62]	875	1			T6	42		T27	2		T28	6
valid_sources[0x63]	1478	1			T6	11		T2	2		T27	3
valid_sources[0x64]	904	1			T6	44		T24	1		T27	2
valid_sources[0x65]	898	1			T2	1		T26	2		T28	4
valid_sources[0x66]	1112	1			T6	23		T24	1		T27	2
valid_sources[0x67]	1756	1			T6	5		T27	5		T28	3
valid_sources[0x68]	1717	1			T6	8		T2	1		T24	2
valid_sources[0x69]	1912	1			T2	1		T24	1		T27	3
valid_sources[0x6a]	1473	1			T6	17		T27	2		T28	3
valid_sources[0x6b]	1451	1			T6	3		T2	1		T24	1
valid_sources[0x6c]	883	1			T6	30		T24	1		T27	6
valid_sources[0x6d]	834	1			T1	5		T27	1		T28	3
valid_sources[0x6e]	778	1			T24	2		T27	2		T28	1
valid_sources[0x6f]	928	1			T24	1		T27	1		T28	1
valid_sources[0x70]	838	1			T2	1		T28	4		T3	2
valid_sources[0x71]	1462	1			T6	3		T2	2		T23	45
valid_sources[0x72]	1073	1			T2	1		T24	1		T27	2
valid_sources[0x73]	816	1			T28	4		T3	5		T4	2
valid_sources[0x74]	1074	1			T2	1		T24	1		T27	3
valid_sources[0x75]	3113	1			T2	5		T24	1		T27	1
valid_sources[0x76]	864	1			T6	4		T24	1		T26	1
valid_sources[0x77]	773	1			T6	12		T2	2		T24	3
valid_sources[0x78]	1099	1			T6	38		T24	1		T27	2
valid_sources[0x79]	737	1			T27	1		T28	4		T3	3
valid_sources[0x7a]	1170	1			T24	1		T27	8		T28	8
valid_sources[0x7b]	736	1			T6	17		T2	1		T27	2
valid_sources[0x7c]	1038	1			T2	1		T24	1		T27	5
valid_sources[0x7d]	864	1			T6	17		T27	4		T28	4
valid_sources[0x7e]	1053	1			T6	44		T24	3		T27	1
valid_sources[0x7f]	3247	1			T6	11		T24	2		T27	2
valid_sources[0x80]	764	1			T2	2		T24	1		T27	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65717

1

T6

534

T1

69

T7

10

values[0x0]

all_enables

biggest_size

33310

1

T6

409

T1

62

T7

7

values[0x1]

all_enables

biggest_size

23948

1

T6

306

T1

69

T7

1