Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.25	89.13	90.48		83.33	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.25	89.13	90.48		83.33	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T32,T18,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T32,T18,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T32,T18,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T18,T54
1	0	Covered	T38,T13,T14
1	1	Covered	T32,T18,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T18,T54
0	1	Covered	T78,T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T18,T54
0	1	Covered	T32,T18,T54
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T18,T54
1	-	Covered	T32,T18,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T32,T18,T54
0	1	Covered	T32,T18,T54
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T32,T18,T54
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T18,T54
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T18,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T48,T92
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T18,T54
DetectSt	-	-	-	-	1	-	-	Covered	T78,T109
DetectSt	-	-	-	-	0	1	-	Covered	T32,T18,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T18,T54
StableSt	-	-	-	-	-	-	0	Covered	T32,T18,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	237	0	0
CntIncr_A	9988962	240405	0	0
CntNoWrap_A	9988962	9322996	0	0
DetectStDropOut_A	9988962	2	0	0
DetectedOut_A	9988962	744	0	0
DetectedPulseOut_A	9988962	109	0	0
DisabledIdleSt_A	9988962	9077078	0	0
DisabledNoDetection_A	9988962	9079398	0	0
EnterDebounceSt_A	9988962	131	0	0
EnterDetectSt_A	9988962	111	0	0
EnterStableSt_A	9988962	109	0	0
PulseIsPulse_A	9988962	109	0	0
StayInStableSt	9988962	635	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9988962	6994	0	0
gen_low_level_sva.LowLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	109	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	237	0	0
T18	2439	2	0	0
T19	1323	0	0	0
T32	649	2	0	0
T33	525	0	0	0
T48	0	5	0	0
T54	0	2	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T65	0	1	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	4	0	0
T95	0	3	0	0
T96	0	2	0	0
T97	412	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	240405	0	0
T18	2439	21	0	0
T19	1323	0	0	0
T32	649	48	0	0
T33	525	0	0	0
T44	0	2809	0	0
T48	0	751	0	0
T54	0	53	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T65	0	47	0	0
T92	0	118	0	0
T93	0	87	0	0
T94	0	43	0	0
T95	0	110	0	0
T97	412	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9322996	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	246	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	2	0	0
T78	2639	1	0	0
T109	0	1	0	0
T114	699	0	0	0
T115	502	0	0	0
T116	405	0	0	0
T117	507	0	0	0
T118	402	0	0	0
T119	792	0	0	0
T120	666	0	0	0
T121	519	0	0	0
T122	1423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	744	0	0
T18	2439	5	0	0
T19	1323	0	0	0
T32	649	8	0	0
T33	525	0	0	0
T48	0	12	0	0
T54	0	4	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	8	0	0
T94	0	13	0	0
T95	0	3	0	0
T96	0	12	0	0
T97	412	0	0	0
T125	0	11	0	0
T126	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	109	0	0
T18	2439	1	0	0
T19	1323	0	0	0
T32	649	1	0	0
T33	525	0	0	0
T48	0	2	0	0
T54	0	1	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	412	0	0	0
T125	0	2	0	0
T126	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9077078	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	151	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9079398	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	152	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	131	0	0
T18	2439	1	0	0
T19	1323	0	0	0
T32	649	1	0	0
T33	525	0	0	0
T44	0	1	0	0
T48	0	4	0	0
T54	0	1	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T65	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	2	0	0
T97	412	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	111	0	0
T18	2439	1	0	0
T19	1323	0	0	0
T32	649	1	0	0
T33	525	0	0	0
T48	0	2	0	0
T54	0	1	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	412	0	0	0
T125	0	2	0	0
T126	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	109	0	0
T18	2439	1	0	0
T19	1323	0	0	0
T32	649	1	0	0
T33	525	0	0	0
T48	0	2	0	0
T54	0	1	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	412	0	0	0
T125	0	2	0	0
T126	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	109	0	0
T18	2439	1	0	0
T19	1323	0	0	0
T32	649	1	0	0
T33	525	0	0	0
T48	0	2	0	0
T54	0	1	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	412	0	0	0
T125	0	2	0	0
T126	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	635	0	0
T18	2439	4	0	0
T19	1323	0	0	0
T32	649	7	0	0
T33	525	0	0	0
T48	0	10	0	0
T54	0	3	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	7	0	0
T94	0	11	0	0
T95	0	2	0	0
T96	0	11	0	0
T97	412	0	0	0
T125	0	9	0	0
T126	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6994	0	0
T13	25693	26	0	0
T14	921	1	0	0
T15	10236	25	0	0
T16	2300	7	0	0
T17	24401	28	0	0
T18	0	8	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	3	0	0
T33	525	5	0	0
T38	523	5	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	109	0	0
T18	2439	1	0	0
T19	1323	0	0	0
T32	649	1	0	0
T33	525	0	0	0
T48	0	2	0	0
T54	0	1	0	0
T58	422	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	412	0	0	0
T125	0	2	0	0
T126	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T19,T82,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T19,T82,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T19,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T82,T39
1	0	Covered	T38,T13,T14
1	1	Covered	T19,T82,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T39,T40
0	1	Covered	T19,T68,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T39,T40
0	1	Unreachable
1	0	Covered	T19,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T82,T39
0	1	Covered	T19,T82,T39
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T39,T40
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T82,T39
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T82,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T82,T39
DetectSt	-	-	-	-	1	-	-	Covered	T19,T68,T87
DetectSt	-	-	-	-	0	1	-	Covered	T19,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T19,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	186	0	0
CntIncr_A	9988962	152838	0	0
CntNoWrap_A	9988962	9323047	0	0
DetectStDropOut_A	9988962	11	0	0
DetectedOut_A	9988962	589098	0	0
DetectedPulseOut_A	9988962	69	0	0
DisabledIdleSt_A	9988962	6569965	0	0
DisabledNoDetection_A	9988962	6572326	0	0
EnterDebounceSt_A	9988962	107	0	0
EnterDetectSt_A	9988962	80	0	0
EnterStableSt_A	9988962	69	0	0
PulseIsPulse_A	9988962	69	0	0
StayInStableSt	9988962	589029	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9988962	6994	0	0
gen_low_level_sva.LowLevelEvent_A	9988962	9325596	0	0
gen_sticky_sva.StableStDropOut_A	9988962	1674778	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	186	0	0
T19	1323	7	0	0
T20	621	0	0	0
T39	0	4	0	0
T40	0	4	0	0
T44	0	4	0	0
T48	0	4	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	2	0	0
T66	0	4	0	0
T67	0	1	0	0
T68	0	5	0	0
T82	655	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	152838	0	0
T19	1323	312	0	0
T20	621	0	0	0
T39	0	80	0	0
T40	0	90	0	0
T44	0	102	0	0
T48	0	175	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	12	0	0
T66	0	72	0	0
T67	0	72	0	0
T68	0	66	0	0
T82	655	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323047	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	11	0	0
T19	1323	2	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T68	12689	1	0	0
T87	0	3	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	3	0	0
T135	502	0	0	0
T136	10969	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	589098	0	0
T19	1323	80	0	0
T39	2010	604	0	0
T40	0	156	0	0
T44	0	817	0	0
T48	0	502	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	64	0	0
T66	0	320	0	0
T68	0	1	0	0
T69	0	211	0	0
T129	0	412	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	69	0	0
T19	1323	1	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T129	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6569965	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6572326	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	107	0	0
T19	1323	4	0	0
T20	621	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	3	0	0
T82	655	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	80	0	0
T19	1323	3	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	2	0	0
T69	0	1	0	0
T129	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	69	0	0
T19	1323	1	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T129	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	69	0	0
T19	1323	1	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T129	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	589029	0	0
T19	1323	79	0	0
T39	2010	602	0	0
T40	0	154	0	0
T44	0	815	0	0
T48	0	500	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	63	0	0
T66	0	318	0	0
T69	0	210	0	0
T87	0	239	0	0
T129	0	410	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6994	0	0
T13	25693	26	0	0
T14	921	1	0	0
T15	10236	25	0	0
T16	2300	7	0	0
T17	24401	28	0	0
T18	0	8	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	3	0	0
T33	525	5	0	0
T38	523	5	0	0
T58	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1674778	0	0
T19	1323	133	0	0
T39	2010	457	0	0
T40	0	273999	0	0
T44	0	216	0	0
T48	0	98752	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	548	0	0
T66	0	206	0	0
T68	0	160	0	0
T69	0	229	0	0
T129	0	604	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T14,T15
1	1	Covered	T38,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T19,T82,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T19,T82,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T19,T40,T65

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T82,T39
1	0	Covered	T38,T14,T15
1	1	Covered	T19,T82,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T40,T65
0	1	Covered	T66,T48,T69
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T40,T65
0	1	Unreachable
1	0	Covered	T19,T40,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T82,T39
0	1	Covered	T19,T82,T39
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T40,T65
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T82,T39
IdleSt	0	-	-	-	-	-	-	Covered	T38,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T40,T65
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T39,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T82,T39
DetectSt	-	-	-	-	1	-	-	Covered	T66,T48,T69
DetectSt	-	-	-	-	0	1	-	Covered	T19,T40,T65
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T40,T65
StableSt	-	-	-	-	-	-	0	Covered	T19,T40,T65
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	219	0	0
CntIncr_A	9988962	714499	0	0
CntNoWrap_A	9988962	9323014	0	0
DetectStDropOut_A	9988962	16	0	0
DetectedOut_A	9988962	653076	0	0
DetectedPulseOut_A	9988962	51	0	0
DisabledIdleSt_A	9988962	6569965	0	0
DisabledNoDetection_A	9988962	6572326	0	0
EnterDebounceSt_A	9988962	153	0	0
EnterDetectSt_A	9988962	67	0	0
EnterStableSt_A	9988962	51	0	0
PulseIsPulse_A	9988962	51	0	0
StayInStableSt	9988962	653025	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_sticky_sva.StableStDropOut_A	9988962	892714	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	219	0	0
T19	1323	2	0	0
T20	621	0	0	0
T39	0	9	0	0
T40	0	4	0	0
T44	0	4	0	0
T48	0	6	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	2	0	0
T66	0	10	0	0
T67	0	1	0	0
T68	0	2	0	0
T82	655	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	714499	0	0
T19	1323	80	0	0
T20	621	0	0	0
T39	0	684	0	0
T40	0	71168	0	0
T44	0	97	0	0
T48	0	129	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	49	0	0
T66	0	180	0	0
T67	0	25	0	0
T68	0	71	0	0
T82	655	112	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323014	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	16	0	0
T47	988	0	0	0
T48	116413	2	0	0
T66	1412	3	0	0
T69	0	1	0	0
T85	0	2	0	0
T123	22435	0	0	0
T137	0	3	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T147	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	653076	0	0
T19	1323	551	0	0
T40	343287	271523	0	0
T44	0	547	0	0
T48	0	463	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	179	0	0
T66	0	149	0	0
T68	0	351	0	0
T69	0	194	0	0
T87	0	522	0	0
T129	0	559	0	0
T130	424	0	0	0
T131	1113	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	51	0	0
T19	1323	1	0	0
T40	343287	2	0	0
T44	0	2	0	0
T48	0	1	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	2	0	0
T129	0	2	0	0
T130	424	0	0	0
T131	1113	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6569965	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6572326	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	153	0	0
T19	1323	1	0	0
T20	621	0	0	0
T39	0	9	0	0
T40	0	2	0	0
T44	0	2	0	0
T48	0	3	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	5	0	0
T67	0	1	0	0
T68	0	1	0	0
T82	655	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	67	0	0
T19	1323	1	0	0
T40	343287	2	0	0
T44	0	2	0	0
T48	0	3	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	5	0	0
T68	0	1	0	0
T69	0	2	0	0
T87	0	2	0	0
T129	0	2	0	0
T130	424	0	0	0
T131	1113	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	51	0	0
T19	1323	1	0	0
T40	343287	2	0	0
T44	0	2	0	0
T48	0	1	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	2	0	0
T129	0	2	0	0
T130	424	0	0	0
T131	1113	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	51	0	0
T19	1323	1	0	0
T40	343287	2	0	0
T44	0	2	0	0
T48	0	1	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T87	0	2	0	0
T129	0	2	0	0
T130	424	0	0	0
T131	1113	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	653025	0	0
T19	1323	550	0	0
T40	343287	271521	0	0
T44	0	545	0	0
T48	0	462	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	178	0	0
T66	0	147	0	0
T68	0	350	0	0
T69	0	193	0	0
T87	0	520	0	0
T129	0	557	0	0
T130	424	0	0	0
T131	1113	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	892714	0	0
T19	1323	86	0	0
T40	343287	112	0	0
T44	0	494	0	0
T48	0	73	0	0
T49	13582	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	395	0	0
T66	0	202	0	0
T68	0	91	0	0
T69	0	139	0	0
T87	0	193	0	0
T129	0	487	0	0
T130	424	0	0	0
T131	1113	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T19,T82,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T19,T82,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T19,T82,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T82,T39
1	0	Covered	T38,T13,T14
1	1	Covered	T19,T82,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T39,T40
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T39,T40
0	1	Unreachable
1	0	Covered	T19,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T82,T39
0	1	Covered	T19,T82,T39
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T82,T39
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T82,T39
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T82,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T88,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T82,T39
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T19,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T19,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	198	0	0
CntIncr_A	9988962	289565	0	0
CntNoWrap_A	9988962	9323035	0	0
DetectStDropOut_A	9988962	18	0	0
DetectedOut_A	9988962	601379	0	0
DetectedPulseOut_A	9988962	64	0	0
DisabledIdleSt_A	9988962	6569965	0	0
DisabledNoDetection_A	9988962	6572326	0	0
EnterDebounceSt_A	9988962	117	0	0
EnterDetectSt_A	9988962	82	0	0
EnterStableSt_A	9988962	64	0	0
PulseIsPulse_A	9988962	64	0	0
StayInStableSt	9988962	601315	0	0
gen_high_event_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_sticky_sva.StableStDropOut_A	9988962	1792936	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	198	0	0
T19	1323	2	0	0
T20	621	0	0	0
T39	0	4	0	0
T40	0	4	0	0
T44	0	7	0	0
T48	0	4	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	2	0	0
T66	0	4	0	0
T67	0	2	0	0
T68	0	2	0	0
T82	655	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	289565	0	0
T19	1323	30	0	0
T20	621	0	0	0
T39	0	102	0	0
T40	0	34886	0	0
T44	0	326	0	0
T48	0	47682	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	87	0	0
T66	0	74	0	0
T67	0	77	0	0
T68	0	85	0	0
T82	655	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323035	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	18	0	0
T20	621	0	0	0
T21	26108	0	0	0
T22	20165	0	0	0
T50	21511	0	0	0
T80	13348	0	0	0
T82	655	2	0	0
T83	0	5	0	0
T84	0	6	0	0
T110	426	0	0	0
T111	439	0	0	0
T112	529	0	0	0
T113	421	0	0	0
T149	0	1	0	0
T150	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	601379	0	0
T19	1323	161	0	0
T39	2010	627	0	0
T40	0	99060	0	0
T44	0	82	0	0
T48	0	51576	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	506	0	0
T66	0	383	0	0
T67	0	21	0	0
T68	0	399	0	0
T69	0	371	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	64	0	0
T19	1323	1	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6569965	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6572326	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	117	0	0
T19	1323	1	0	0
T20	621	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	6	0	0
T48	0	2	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T82	655	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	82	0	0
T19	1323	1	0	0
T20	621	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T49	13582	0	0	0
T50	21511	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T82	655	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	64	0	0
T19	1323	1	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	64	0	0
T19	1323	1	0	0
T39	2010	2	0	0
T40	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	1	0	0
T66	0	2	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	601315	0	0
T19	1323	160	0	0
T39	2010	625	0	0
T40	0	99058	0	0
T44	0	81	0	0
T48	0	51574	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	505	0	0
T66	0	381	0	0
T67	0	20	0	0
T68	0	398	0	0
T69	0	370	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1792936	0	0
T19	1323	541	0	0
T39	2010	419	0	0
T40	0	208883	0	0
T44	0	594	0	0
T48	0	187	0	0
T49	13582	0	0	0
T51	28724	0	0	0
T59	494	0	0	0
T60	522	0	0	0
T61	421	0	0	0
T62	582	0	0	0
T63	506	0	0	0
T64	491	0	0	0
T65	0	47	0	0
T66	0	167	0	0
T67	0	36	0	0
T68	0	39	0	0
T69	0	60	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T15,T16,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T62
1	0	Covered	T38,T13,T14
1	1	Covered	T15,T16,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T48
0	1	Covered	T16,T48,T47
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T48
1	-	Covered	T16,T48,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T48
0	1	Covered	T15,T16,T48
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T48
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T48
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T48
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T48,T47
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	80	0	0
CntIncr_A	9988962	42170	0	0
CntNoWrap_A	9988962	9323153	0	0
DetectStDropOut_A	9988962	0	0	0
DetectedOut_A	9988962	3445	0	0
DetectedPulseOut_A	9988962	40	0	0
DisabledIdleSt_A	9988962	8854012	0	0
DisabledNoDetection_A	9988962	8856323	0	0
EnterDebounceSt_A	9988962	41	0	0
EnterDetectSt_A	9988962	40	0	0
EnterStableSt_A	9988962	40	0	0
PulseIsPulse_A	9988962	40	0	0
StayInStableSt	9988962	3383	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	80	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T58	422	0	0	0
T88	0	2	0	0
T97	412	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	0	2	0	0
T154	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	42170	0	0
T15	10236	56	0	0
T16	2300	19	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	52	0	0
T47	0	132	0	0
T48	0	85	0	0
T58	422	0	0	0
T88	0	4312	0	0
T97	412	0	0	0
T151	0	85	0	0
T152	0	38	0	0
T153	0	43	0	0
T154	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323153	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3704	0	0
T16	2300	695	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3445	0	0
T15	10236	40	0	0
T16	2300	9	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	16	0	0
T47	0	166	0	0
T48	0	149	0	0
T58	422	0	0	0
T88	0	43	0	0
T97	412	0	0	0
T151	0	251	0	0
T152	0	254	0	0
T153	0	107	0	0
T154	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	40	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	422	0	0	0
T88	0	1	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8854012	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3439	0	0
T16	2300	528	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8856323	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3451	0	0
T16	2300	530	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	41	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	422	0	0	0
T88	0	1	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	40	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	422	0	0	0
T88	0	1	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	40	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	422	0	0	0
T88	0	1	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	40	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	422	0	0	0
T88	0	1	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3383	0	0
T15	10236	38	0	0
T16	2300	8	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	15	0	0
T47	0	163	0	0
T48	0	148	0	0
T58	422	0	0	0
T88	0	41	0	0
T97	412	0	0	0
T151	0	249	0	0
T152	0	252	0	0
T153	0	106	0	0
T154	0	53	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	16	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T58	422	0	0	0
T72	0	1	0	0
T97	412	0	0	0
T153	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T15,T16,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T20
1	0	Covered	T38,T13,T14
1	1	Covered	T15,T16,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T77,T159,T160
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T20
1	-	Covered	T15,T16,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T20
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T20
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T86,T161,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T20
DetectSt	-	-	-	-	1	-	-	Covered	T77,T159,T160
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T16,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	117	0	0
CntIncr_A	9988962	71841	0	0
CntNoWrap_A	9988962	9323116	0	0
DetectStDropOut_A	9988962	3	0	0
DetectedOut_A	9988962	6998	0	0
DetectedPulseOut_A	9988962	53	0	0
DisabledIdleSt_A	9988962	9160965	0	0
DisabledNoDetection_A	9988962	9163279	0	0
EnterDebounceSt_A	9988962	61	0	0
EnterDetectSt_A	9988962	56	0	0
EnterStableSt_A	9988962	53	0	0
PulseIsPulse_A	9988962	53	0	0
StayInStableSt	9988962	6926	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9988962	2701	0	0
gen_low_level_sva.LowLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	117	0	0
T15	10236	2	0	0
T16	2300	4	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	2	0	0
T44	0	4	0	0
T46	0	2	0	0
T47	0	4	0	0
T48	0	4	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	2	0	0
T153	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	71841	0	0
T15	10236	56	0	0
T16	2300	38	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	12	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	47	0	0
T44	0	104	0	0
T46	0	57	0	0
T47	0	132	0	0
T48	0	170	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	85	0	0
T153	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323116	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3704	0	0
T16	2300	693	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3	0	0
T77	512	1	0	0
T86	31498	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T163	958	0	0	0
T164	5466	0	0	0
T165	110820	0	0	0
T166	604	0	0	0
T167	426	0	0	0
T168	506	0	0	0
T169	44029	0	0	0
T170	129536	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6998	0	0
T15	10236	43	0	0
T16	2300	79	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	149	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	248	0	0
T44	0	336	0	0
T46	0	43	0	0
T47	0	79	0	0
T48	0	104	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	7	0	0
T153	0	192	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	53	0	0
T15	10236	1	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T153	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9160965	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3506	0	0
T16	2300	528	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9163279	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3519	0	0
T16	2300	530	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	61	0	0
T15	10236	1	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	56	0	0
T15	10236	1	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T153	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	53	0	0
T15	10236	1	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T153	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	53	0	0
T15	10236	1	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T153	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6926	0	0
T15	10236	42	0	0
T16	2300	76	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	148	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	247	0	0
T44	0	333	0	0
T46	0	42	0	0
T47	0	77	0	0
T48	0	101	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	6	0	0
T153	0	189	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	2701	0	0
T13	25693	0	0	0
T14	921	2	0	0
T15	10236	18	0	0
T16	2300	7	0	0
T17	24401	0	0	0
T18	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	6	0	0
T38	523	4	0	0
T58	0	1	0	0
T59	0	4	0	0
T60	0	4	0	0
T97	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	32	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T153	0	1	0	0