Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T14,T15,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T14,T15,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T14,T15,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T20
1	0	Covered	T38,T13,T14
1	1	Covered	T14,T15,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T20
0	1	Covered	T159
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T20
0	1	Covered	T20,T47,T46
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T20
1	-	Covered	T20,T47,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T20
0	1	Covered	T14,T15,T20
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T20
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T20
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T171
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T20
DetectSt	-	-	-	-	1	-	-	Covered	T159
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T20,T47,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	73	0	0
CntIncr_A	9988962	21972	0	0
CntNoWrap_A	9988962	9323160	0	0
DetectStDropOut_A	9988962	1	0	0
DetectedOut_A	9988962	5741	0	0
DetectedPulseOut_A	9988962	35	0	0
DisabledIdleSt_A	9988962	8890750	0	0
DisabledNoDetection_A	9988962	8893066	0	0
EnterDebounceSt_A	9988962	38	0	0
EnterDetectSt_A	9988962	36	0	0
EnterStableSt_A	9988962	35	0	0
PulseIsPulse_A	9988962	35	0	0
StayInStableSt	9988962	5683	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	73	0	0
T14	921	2	0	0
T15	10236	2	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	4	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	2	0	0
T47	0	4	0	0
T58	422	0	0	0
T72	0	2	0	0
T151	0	2	0	0
T154	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	21972	0	0
T14	921	56	0	0
T15	10236	18	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	24	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	57	0	0
T47	0	132	0	0
T58	422	0	0	0
T72	0	77	0	0
T151	0	85	0	0
T154	0	71	0	0
T172	0	68	0	0
T173	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323160	0	0
T13	25693	25287	0	0
T14	921	518	0	0
T15	10236	3704	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1	0	0
T159	15829	1	0	0
T174	27512	0	0	0
T175	895	0	0	0
T176	507	0	0	0
T177	499	0	0	0
T178	441	0	0	0
T179	15710	0	0	0
T180	16549	0	0	0
T181	17354	0	0	0
T182	722	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	5741	0	0
T14	921	116	0	0
T15	10236	42	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	62	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	43	0	0
T47	0	168	0	0
T58	422	0	0	0
T72	0	56	0	0
T151	0	251	0	0
T154	0	56	0	0
T172	0	45	0	0
T173	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	35	0	0
T14	921	1	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8890750	0	0
T13	25693	25287	0	0
T14	921	3	0	0
T15	10236	3639	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8893066	0	0
T13	25693	25289	0	0
T14	921	3	0	0
T15	10236	3652	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	38	0	0
T14	921	1	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	36	0	0
T14	921	1	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	35	0	0
T14	921	1	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	35	0	0
T14	921	1	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	5683	0	0
T14	921	114	0	0
T15	10236	40	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	59	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	42	0	0
T47	0	165	0	0
T58	422	0	0	0
T72	0	54	0	0
T151	0	249	0	0
T154	0	54	0	0
T172	0	43	0	0
T173	0	114	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	10	0	0
T20	621	1	0	0
T21	26108	0	0	0
T22	20165	0	0	0
T39	2010	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T51	28724	0	0	0
T80	13348	0	0	0
T110	426	0	0	0
T111	439	0	0	0
T112	529	0	0	0
T113	421	0	0	0
T157	0	2	0	0
T158	0	1	0	0
T173	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T42,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T15,T42,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T42,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T42,T47
1	0	Covered	T38,T13,T14
1	1	Covered	T15,T42,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T42,T47
0	1	Covered	T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T42,T47
0	1	Covered	T42,T47,T44
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T42,T47
1	-	Covered	T42,T47,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T42,T47
0	1	Covered	T15,T42,T47
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T42,T47
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T42,T47
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T42,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T42,T46
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T42,T47
DetectSt	-	-	-	-	1	-	-	Covered	T79
DetectSt	-	-	-	-	0	1	-	Covered	T15,T42,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T47,T44
StableSt	-	-	-	-	-	-	0	Covered	T15,T42,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	95	0	0
CntIncr_A	9988962	18030	0	0
CntNoWrap_A	9988962	9323138	0	0
DetectStDropOut_A	9988962	1	0	0
DetectedOut_A	9988962	4003	0	0
DetectedPulseOut_A	9988962	44	0	0
DisabledIdleSt_A	9988962	9239330	0	0
DisabledNoDetection_A	9988962	9241655	0	0
EnterDebounceSt_A	9988962	50	0	0
EnterDetectSt_A	9988962	45	0	0
EnterStableSt_A	9988962	44	0	0
PulseIsPulse_A	9988962	44	0	0
StayInStableSt	9988962	3939	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9988962	3065	0	0
gen_low_level_sva.LowLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	95	0	0
T15	10236	3	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	3	0	0
T44	0	4	0	0
T46	0	3	0	0
T47	0	4	0	0
T58	422	0	0	0
T72	0	2	0	0
T97	412	0	0	0
T152	0	4	0	0
T186	0	1	0	0
T187	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	18030	0	0
T15	10236	74	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	94	0	0
T44	0	104	0	0
T46	0	114	0	0
T47	0	132	0	0
T58	422	0	0	0
T72	0	77	0	0
T97	412	0	0	0
T152	0	76	0	0
T186	0	77	0	0
T187	0	15594	0	0
T188	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323138	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3703	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1	0	0
T79	13534	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	4003	0	0
T15	10236	140	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	116	0	0
T44	0	84	0	0
T46	0	108	0	0
T47	0	76	0	0
T58	422	0	0	0
T72	0	104	0	0
T97	412	0	0	0
T152	0	226	0	0
T173	0	211	0	0
T187	0	45	0	0
T188	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	44	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T97	412	0	0	0
T152	0	2	0	0
T173	0	2	0	0
T187	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9239330	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3439	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9241655	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3451	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	50	0	0
T15	10236	2	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	2	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T97	412	0	0	0
T152	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	45	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T97	412	0	0	0
T152	0	2	0	0
T173	0	2	0	0
T187	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	44	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T97	412	0	0	0
T152	0	2	0	0
T173	0	2	0	0
T187	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	44	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T58	422	0	0	0
T72	0	1	0	0
T97	412	0	0	0
T152	0	2	0	0
T173	0	2	0	0
T187	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3939	0	0
T15	10236	138	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	115	0	0
T44	0	81	0	0
T46	0	106	0	0
T47	0	74	0	0
T58	422	0	0	0
T72	0	103	0	0
T97	412	0	0	0
T152	0	223	0	0
T173	0	208	0	0
T187	0	43	0	0
T188	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3065	0	0
T13	25693	0	0	0
T14	921	1	0	0
T15	10236	25	0	0
T16	2300	4	0	0
T17	24401	0	0	0
T18	0	8	0	0
T30	862	4	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	5	0	0
T38	523	6	0	0
T58	0	2	0	0
T59	0	4	0	0
T97	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	22	0	0
T42	858	1	0	0
T44	0	1	0	0
T47	988	2	0	0
T66	1412	0	0	0
T72	0	1	0	0
T123	22435	0	0	0
T127	521	0	0	0
T128	607	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T152	0	1	0	0
T173	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T15,T16,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T20
1	0	Covered	T38,T13,T14
1	1	Covered	T15,T16,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T16,T20
1	-	Covered	T15,T16,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T16,T20
0	1	Covered	T15,T16,T20
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T20
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T16,T20
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T193,T140,T185
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T16,T20
DetectSt	-	-	-	-	1	-	-	Covered	T79
DetectSt	-	-	-	-	0	1	-	Covered	T15,T16,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T16,T20
StableSt	-	-	-	-	-	-	0	Covered	T15,T16,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	151	0	0
CntIncr_A	9988962	43380	0	0
CntNoWrap_A	9988962	9323082	0	0
DetectStDropOut_A	9988962	1	0	0
DetectedOut_A	9988962	6024	0	0
DetectedPulseOut_A	9988962	73	0	0
DisabledIdleSt_A	9988962	9117071	0	0
DisabledNoDetection_A	9988962	9119376	0	0
EnterDebounceSt_A	9988962	79	0	0
EnterDetectSt_A	9988962	74	0	0
EnterStableSt_A	9988962	73	0	0
PulseIsPulse_A	9988962	73	0	0
StayInStableSt	9988962	5919	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	151	0	0
T15	10236	4	0	0
T16	2300	4	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	4	0	0
T48	0	8	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	2	0	0
T152	0	2	0	0
T186	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	43380	0	0
T15	10236	74	0	0
T16	2300	38	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	12	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	29	0	0
T46	0	57	0	0
T47	0	132	0	0
T48	0	368	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	85	0	0
T152	0	38	0	0
T186	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323082	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3702	0	0
T16	2300	693	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1	0	0
T79	13534	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6024	0	0
T15	10236	87	0	0
T16	2300	96	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	129	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	142	0	0
T46	0	107	0	0
T47	0	339	0	0
T48	0	328	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	124	0	0
T152	0	114	0	0
T186	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	73	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	4	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T186	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9117071	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3439	0	0
T16	2300	528	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9119376	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3451	0	0
T16	2300	530	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	79	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	4	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T186	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	74	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	4	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T186	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	73	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	4	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T186	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	73	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	4	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T186	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	5919	0	0
T15	10236	84	0	0
T16	2300	93	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	128	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	140	0	0
T46	0	106	0	0
T47	0	336	0	0
T48	0	322	0	0
T58	422	0	0	0
T97	412	0	0	0
T151	0	122	0	0
T152	0	113	0	0
T186	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	39	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T20	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T58	422	0	0	0
T97	412	0	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T172	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T13,T15
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T194
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T16,T42
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T16
1	-	Covered	T14,T16,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T194
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T16,T42
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	87	0	0
CntIncr_A	9988962	2254	0	0
CntNoWrap_A	9988962	9323146	0	0
DetectStDropOut_A	9988962	1	0	0
DetectedOut_A	9988962	3808	0	0
DetectedPulseOut_A	9988962	42	0	0
DisabledIdleSt_A	9988962	9305157	0	0
DisabledNoDetection_A	9988962	9307470	0	0
EnterDebounceSt_A	9988962	44	0	0
EnterDetectSt_A	9988962	43	0	0
EnterStableSt_A	9988962	42	0	0
PulseIsPulse_A	9988962	42	0	0
StayInStableSt	9988962	3747	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9988962	6678	0	0
gen_low_level_sva.LowLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	87	0	0
T14	921	4	0	0
T15	10236	2	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	6	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T58	422	0	0	0
T152	0	2	0	0
T153	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	2254	0	0
T14	921	112	0	0
T15	10236	56	0	0
T16	2300	19	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	141	0	0
T43	0	53	0	0
T44	0	52	0	0
T46	0	57	0	0
T47	0	66	0	0
T58	422	0	0	0
T152	0	38	0	0
T153	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323146	0	0
T13	25693	25287	0	0
T14	921	516	0	0
T15	10236	3704	0	0
T16	2300	695	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1	0	0
T194	727	1	0	0
T195	421	0	0	0
T196	423	0	0	0
T197	416	0	0	0
T198	444	0	0	0
T199	490	0	0	0
T200	524	0	0	0
T201	8402	0	0	0
T202	28895	0	0	0
T203	1892	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3808	0	0
T14	921	159	0	0
T15	10236	41	0	0
T16	2300	9	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	130	0	0
T43	0	94	0	0
T44	0	44	0	0
T46	0	44	0	0
T47	0	40	0	0
T58	422	0	0	0
T152	0	183	0	0
T153	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	42	0	0
T14	921	2	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	422	0	0	0
T152	0	1	0	0
T153	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9305157	0	0
T13	25693	25287	0	0
T14	921	3	0	0
T15	10236	3506	0	0
T16	2300	528	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9307470	0	0
T13	25693	25289	0	0
T14	921	3	0	0
T15	10236	3519	0	0
T16	2300	530	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	44	0	0
T14	921	2	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	422	0	0	0
T152	0	1	0	0
T153	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	43	0	0
T14	921	2	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	422	0	0	0
T152	0	1	0	0
T153	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	42	0	0
T14	921	2	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	422	0	0	0
T152	0	1	0	0
T153	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	42	0	0
T14	921	2	0	0
T15	10236	1	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T58	422	0	0	0
T152	0	1	0	0
T153	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3747	0	0
T14	921	157	0	0
T15	10236	39	0	0
T16	2300	8	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	126	0	0
T43	0	93	0	0
T44	0	43	0	0
T46	0	42	0	0
T47	0	39	0	0
T58	422	0	0	0
T152	0	181	0	0
T153	0	86	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6678	0	0
T13	25693	27	0	0
T14	921	2	0	0
T15	10236	21	0	0
T16	2300	8	0	0
T17	24401	25	0	0
T18	0	7	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	5	0	0
T38	523	4	0	0
T58	0	4	0	0
T97	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	21	0	0
T14	921	2	0	0
T15	10236	0	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T58	422	0	0	0
T72	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T173	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T38,T13,T15
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T86,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T45,T48
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T16
1	-	Covered	T14,T45,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T139,T185
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T86,T193
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T45,T48
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	117	0	0
CntIncr_A	9988962	68443	0	0
CntNoWrap_A	9988962	9323116	0	0
DetectStDropOut_A	9988962	2	0	0
DetectedOut_A	9988962	153494	0	0
DetectedPulseOut_A	9988962	54	0	0
DisabledIdleSt_A	9988962	9013577	0	0
DisabledNoDetection_A	9988962	9015896	0	0
EnterDebounceSt_A	9988962	61	0	0
EnterDetectSt_A	9988962	56	0	0
EnterStableSt_A	9988962	54	0	0
PulseIsPulse_A	9988962	54	0	0
StayInStableSt	9988962	153415	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	117	0	0
T14	921	2	0	0
T15	10236	4	0	0
T16	2300	2	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T48	0	8	0	0
T58	422	0	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	68443	0	0
T14	921	56	0	0
T15	10236	74	0	0
T16	2300	19	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	53	0	0
T45	0	29	0	0
T48	0	368	0	0
T58	422	0	0	0
T151	0	85	0	0
T152	0	76	0	0
T153	0	43	0	0
T187	0	15594	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323116	0	0
T13	25693	25287	0	0
T14	921	518	0	0
T15	10236	3702	0	0
T16	2300	695	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	2	0	0
T86	31498	1	0	0
T165	110820	0	0	0
T166	604	0	0	0
T167	426	0	0	0
T168	506	0	0	0
T169	44029	0	0	0
T170	129536	0	0	0
T193	0	1	0	0
T204	724	0	0	0
T205	420	0	0	0
T206	454	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	153494	0	0
T14	921	199	0	0
T15	10236	182	0	0
T16	2300	145	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	40	0	0
T45	0	71	0	0
T48	0	289	0	0
T58	422	0	0	0
T151	0	133	0	0
T152	0	40	0	0
T153	0	231	0	0
T187	0	6386	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	54	0	0
T14	921	1	0	0
T15	10236	2	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	4	0	0
T58	422	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9013577	0	0
T13	25693	25287	0	0
T14	921	3	0	0
T15	10236	3439	0	0
T16	2300	528	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9015896	0	0
T13	25693	25289	0	0
T14	921	3	0	0
T15	10236	3451	0	0
T16	2300	530	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	61	0	0
T14	921	1	0	0
T15	10236	2	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	4	0	0
T58	422	0	0	0
T151	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	56	0	0
T14	921	1	0	0
T15	10236	2	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	4	0	0
T58	422	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	54	0	0
T14	921	1	0	0
T15	10236	2	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	4	0	0
T58	422	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	54	0	0
T14	921	1	0	0
T15	10236	2	0	0
T16	2300	1	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T48	0	4	0	0
T58	422	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	153415	0	0
T14	921	198	0	0
T15	10236	178	0	0
T16	2300	143	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T43	0	38	0	0
T45	0	70	0	0
T48	0	283	0	0
T58	422	0	0	0
T151	0	132	0	0
T152	0	39	0	0
T153	0	230	0	0
T187	0	6385	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	27	0	0
T14	921	1	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T45	0	1	0	0
T48	0	2	0	0
T58	422	0	0	0
T85	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T187	0	1	0	0
T207	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T38,T13,T14
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T45,T44,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T45,T44,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T45,T44,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T45
1	0	Covered	T38,T13,T14
1	1	Covered	T45,T44,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T44,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T44,T46
0	1	Covered	T72,T85,T86
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T44,T46
1	-	Covered	T72,T85,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T44,T46
0	1	Covered	T45,T44,T46
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T44,T46
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T44,T46
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T44,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T159
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T44,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T44,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T72,T85,T86
StableSt	-	-	-	-	-	-	0	Covered	T45,T44,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	61	0	0
CntIncr_A	9988962	1563	0	0
CntNoWrap_A	9988962	9323172	0	0
DetectStDropOut_A	9988962	0	0	0
DetectedOut_A	9988962	3424	0	0
DetectedPulseOut_A	9988962	30	0	0
DisabledIdleSt_A	9988962	9088466	0	0
DisabledNoDetection_A	9988962	9090785	0	0
EnterDebounceSt_A	9988962	31	0	0
EnterDetectSt_A	9988962	30	0	0
EnterStableSt_A	9988962	30	0	0
PulseIsPulse_A	9988962	30	0	0
StayInStableSt	9988962	3378	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9988962	6347	0	0
gen_low_level_sva.LowLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	61	0	0
T44	0	2	0	0
T45	602	2	0	0
T46	0	2	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	2	0	0
T85	0	2	0	0
T86	0	2	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	2	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	2	0	0
T191	0	2	0	0
T208	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1563	0	0
T44	0	52	0	0
T45	602	29	0	0
T46	0	57	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	77	0	0
T85	0	61	0	0
T86	0	69	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	23	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	43	0	0
T191	0	34	0	0
T208	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9323172	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3424	0	0
T44	0	209	0	0
T45	602	42	0	0
T46	0	108	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	152	0	0
T85	0	251	0	0
T86	0	39	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	38	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	50	0	0
T191	0	75	0	0
T208	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	30	0	0
T44	0	1	0	0
T45	602	1	0	0
T46	0	1	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	1	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	1	0	0
T191	0	1	0	0
T208	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9088466	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3506	0	0
T16	2300	528	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9090785	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3519	0	0
T16	2300	530	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	31	0	0
T44	0	1	0	0
T45	602	1	0	0
T46	0	1	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	1	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	1	0	0
T191	0	1	0	0
T208	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	30	0	0
T44	0	1	0	0
T45	602	1	0	0
T46	0	1	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	1	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	1	0	0
T191	0	1	0	0
T208	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	30	0	0
T44	0	1	0	0
T45	602	1	0	0
T46	0	1	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	1	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	1	0	0
T191	0	1	0	0
T208	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	30	0	0
T44	0	1	0	0
T45	602	1	0	0
T46	0	1	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	1	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	1	0	0
T191	0	1	0	0
T208	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3378	0	0
T44	0	207	0	0
T45	602	40	0	0
T46	0	106	0	0
T47	988	0	0	0
T48	116413	0	0	0
T72	0	151	0	0
T85	0	250	0	0
T86	0	38	0	0
T98	511	0	0	0
T99	502	0	0	0
T139	0	36	0	0
T142	423	0	0	0
T143	427	0	0	0
T144	422	0	0	0
T145	491	0	0	0
T146	407	0	0	0
T153	0	48	0	0
T191	0	74	0	0
T208	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	6347	0	0
T13	25693	26	0	0
T14	921	1	0	0
T15	10236	22	0	0
T16	2300	5	0	0
T17	24401	26	0	0
T18	0	8	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	3	0	0
T38	523	5	0	0
T58	0	4	0	0
T59	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	12	0	0
T72	71873	1	0	0
T79	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T158	0	1	0	0
T159	0	1	0	0
T188	550	0	0	0
T191	0	1	0	0
T209	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0
T212	497	0	0	0
T213	25168	0	0	0
T214	1349	0	0	0
T215	444	0	0	0
T216	12521	0	0	0
T217	7836	0	0	0
T218	437	0	0	0
T219	424	0	0	0