Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T13,T17,T49
1	1	Covered	T13,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T80,T56,T100
1	0	Covered	T80,T56,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T49
1	-	Covered	T13,T17,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T49
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T13,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T241,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T80,T56,T100
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	0	0	-	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	3009	0	0
CntIncr_A	9988962	103809	0	0
CntNoWrap_A	9988962	9320224	0	0
DetectStDropOut_A	9988962	396	0	0
DetectedOut_A	9988962	77788	0	0
DetectedPulseOut_A	9988962	979	0	0
DisabledIdleSt_A	9988962	8855470	0	0
DisabledNoDetection_A	9988962	8857617	0	0
EnterDebounceSt_A	9988962	1523	0	0
EnterDetectSt_A	9988962	1487	0	0
EnterStableSt_A	9988962	979	0	0
PulseIsPulse_A	9988962	979	0	0
StayInStableSt	9988962	76683	0	0
gen_high_event_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	852	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3009	0	0
T13	25693	28	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	12	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	20	0	0
T51	0	20	0	0
T55	0	58	0	0
T56	0	52	0	0
T57	0	16	0	0
T80	0	30	0	0
T90	0	68	0	0
T123	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	103809	0	0
T13	25693	4242	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	480	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	360	0	0
T51	0	830	0	0
T55	0	2523	0	0
T56	0	1201	0	0
T57	0	552	0	0
T80	0	883	0	0
T90	0	2414	0	0
T123	0	2842	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9320224	0	0
T13	25693	25259	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23937	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	396	0	0
T21	26108	0	0	0
T22	20165	0	0	0
T39	2010	0	0	0
T51	28724	0	0	0
T56	0	22	0	0
T64	491	0	0	0
T80	13348	12	0	0
T81	0	5	0	0
T89	0	4	0	0
T90	11929	0	0	0
T100	0	16	0	0
T101	0	10	0	0
T102	0	4	0	0
T103	0	18	0	0
T105	0	16	0	0
T241	0	4	0	0
T243	422	0	0	0
T244	442	0	0	0
T245	3016	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	77788	0	0
T13	25693	2341	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	614	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	676	0	0
T51	0	1082	0	0
T55	0	1347	0	0
T57	0	319	0	0
T90	0	1637	0	0
T123	0	1889	0	0
T124	0	3259	0	0
T221	0	1619	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	979	0	0
T13	25693	14	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	10	0	0
T51	0	10	0	0
T55	0	29	0	0
T57	0	8	0	0
T90	0	34	0	0
T123	0	29	0	0
T124	0	18	0	0
T221	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8855470	0	0
T13	25693	6273	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	17673	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8857617	0	0
T13	25693	6273	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	17680	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1523	0	0
T13	25693	14	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	10	0	0
T51	0	10	0	0
T55	0	29	0	0
T56	0	26	0	0
T57	0	8	0	0
T80	0	15	0	0
T90	0	34	0	0
T123	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1487	0	0
T13	25693	14	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	10	0	0
T51	0	10	0	0
T55	0	29	0	0
T56	0	26	0	0
T57	0	8	0	0
T80	0	15	0	0
T90	0	34	0	0
T123	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	979	0	0
T13	25693	14	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	10	0	0
T51	0	10	0	0
T55	0	29	0	0
T57	0	8	0	0
T90	0	34	0	0
T123	0	29	0	0
T124	0	18	0	0
T221	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	979	0	0
T13	25693	14	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	10	0	0
T51	0	10	0	0
T55	0	29	0	0
T57	0	8	0	0
T90	0	34	0	0
T123	0	29	0	0
T124	0	18	0	0
T221	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	76683	0	0
T13	25693	2326	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	608	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	666	0	0
T51	0	1070	0	0
T55	0	1315	0	0
T57	0	311	0	0
T90	0	1601	0	0
T123	0	1856	0	0
T124	0	3237	0	0
T221	0	1599	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	852	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	10	0	0
T51	0	8	0	0
T55	0	26	0	0
T57	0	8	0	0
T90	0	32	0	0
T123	0	25	0	0
T124	0	14	0	0
T221	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T17
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T13,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T18
0	1	Covered	T50,T21,T22
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T18
0	1	Covered	T13,T17,T18
1	0	Covered	T74,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T18
1	-	Covered	T13,T17,T18

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T18
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T50,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T50,T21,T22
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T18
DetectSt	-	-	-	-	0	0	-	Covered	T13,T17,T18
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T18
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	1046	0	0
CntIncr_A	9988962	52630	0	0
CntNoWrap_A	9988962	9322187	0	0
DetectStDropOut_A	9988962	50	0	0
DetectedOut_A	9988962	16284	0	0
DetectedPulseOut_A	9988962	429	0	0
DisabledIdleSt_A	9988962	8943511	0	0
DisabledNoDetection_A	9988962	8945073	0	0
EnterDebounceSt_A	9988962	565	0	0
EnterDetectSt_A	9988962	483	0	0
EnterStableSt_A	9988962	429	0	0
PulseIsPulse_A	9988962	429	0	0
StayInStableSt	9988962	15821	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	393	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1046	0	0
T13	25693	2	0	0
T14	921	0	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	4	0	0
T18	2439	2	0	0
T21	0	8	0	0
T22	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T50	0	9	0	0
T51	0	4	0	0
T90	0	5	0	0
T91	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	52630	0	0
T13	25693	302	0	0
T14	921	0	0	0
T15	10236	20	0	0
T16	2300	0	0	0
T17	24401	108	0	0
T18	2439	25	0	0
T21	0	250	0	0
T22	0	125	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T50	0	312	0	0
T51	0	158	0	0
T90	0	144	0	0
T91	0	1261	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9322187	0	0
T13	25693	25285	0	0
T14	921	520	0	0
T15	10236	3705	0	0
T16	2300	697	0	0
T17	24401	23945	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	50	0	0
T20	621	0	0	0
T21	26108	2	0	0
T22	20165	1	0	0
T39	2010	0	0	0
T44	0	3	0	0
T48	0	1	0	0
T50	21511	4	0	0
T80	13348	0	0	0
T91	0	9	0	0
T104	0	1	0	0
T106	0	3	0	0
T107	0	8	0	0
T108	0	10	0	0
T110	426	0	0	0
T111	439	0	0	0
T112	529	0	0	0
T113	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	16284	0	0
T13	25693	55	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	153	0	0
T18	2439	3	0	0
T21	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	346	0	0
T51	0	138	0	0
T54	0	3	0	0
T55	0	315	0	0
T90	0	112	0	0
T123	0	391	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	429	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	2	0	0
T18	2439	1	0	0
T21	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	7	0	0
T90	0	2	0	0
T123	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8943511	0	0
T13	25693	22947	0	0
T14	921	520	0	0
T15	10236	3679	0	0
T16	2300	697	0	0
T17	24401	23334	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8945073	0	0
T13	25693	22948	0	0
T14	921	521	0	0
T15	10236	3692	0	0
T16	2300	700	0	0
T17	24401	23342	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	565	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	1	0	0
T16	2300	0	0	0
T17	24401	2	0	0
T18	2439	1	0	0
T21	0	4	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T50	0	5	0	0
T51	0	2	0	0
T90	0	3	0	0
T91	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	483	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	2	0	0
T18	2439	1	0	0
T21	0	4	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T50	0	4	0	0
T51	0	2	0	0
T54	0	1	0	0
T90	0	2	0	0
T91	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	429	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	2	0	0
T18	2439	1	0	0
T21	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	7	0	0
T90	0	2	0	0
T123	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	429	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	2	0	0
T18	2439	1	0	0
T21	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	7	0	0
T90	0	2	0	0
T123	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	15821	0	0
T13	25693	54	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	151	0	0
T18	2439	2	0	0
T21	0	4	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	342	0	0
T51	0	136	0	0
T54	0	2	0	0
T55	0	308	0	0
T90	0	108	0	0
T123	0	387	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	393	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	2	0	0
T18	2439	1	0	0
T21	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T51	0	2	0	0
T54	0	1	0	0
T55	0	7	0	0
T123	0	4	0	0
T124	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T13,T17,T49
1	1	Covered	T13,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T49,T80,T56
1	0	Covered	T49,T80,T56

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T51
0	1	Covered	T13,T17,T51
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T51
1	-	Covered	T13,T17,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T49
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T13,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T241,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T49,T80,T56
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T51
DetectSt	-	-	-	-	0	0	-	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T51
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T51
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	3044	0	0
CntIncr_A	9988962	119510	0	0
CntNoWrap_A	9988962	9320189	0	0
DetectStDropOut_A	9988962	457	0	0
DetectedOut_A	9988962	61567	0	0
DetectedPulseOut_A	9988962	782	0	0
DisabledIdleSt_A	9988962	8868353	0	0
DisabledNoDetection_A	9988962	8870556	0	0
EnterDebounceSt_A	9988962	1542	0	0
EnterDetectSt_A	9988962	1505	0	0
EnterStableSt_A	9988962	782	0	0
PulseIsPulse_A	9988962	782	0	0
StayInStableSt	9988962	60715	0	0
gen_high_event_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	711	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3044	0	0
T13	25693	50	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	18	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	50	0	0
T51	0	56	0	0
T55	0	52	0	0
T56	0	54	0	0
T57	0	46	0	0
T80	0	60	0	0
T90	0	8	0	0
T123	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	119510	0	0
T13	25693	7350	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	666	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	1709	0	0
T51	0	2352	0	0
T55	0	1638	0	0
T56	0	1249	0	0
T57	0	1380	0	0
T80	0	1780	0	0
T90	0	240	0	0
T123	0	1185	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9320189	0	0
T13	25693	25237	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23931	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	457	0	0
T21	26108	0	0	0
T22	20165	0	0	0
T39	2010	0	0	0
T49	13582	15	0	0
T51	28724	0	0	0
T56	0	20	0	0
T63	506	0	0	0
T64	491	0	0	0
T80	13348	22	0	0
T100	0	11	0	0
T101	0	6	0	0
T103	0	9	0	0
T105	0	3	0	0
T124	0	2	0	0
T213	0	8	0	0
T243	422	0	0	0
T244	442	0	0	0
T246	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	61567	0	0
T13	25693	3738	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	1064	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T51	0	3947	0	0
T55	0	2335	0	0
T57	0	3044	0	0
T89	0	40	0	0
T90	0	65	0	0
T102	0	895	0	0
T123	0	981	0	0
T247	0	2247	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	782	0	0
T13	25693	25	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	9	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T51	0	28	0	0
T55	0	26	0	0
T57	0	23	0	0
T89	0	4	0	0
T90	0	4	0	0
T102	0	12	0	0
T123	0	15	0	0
T247	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8868353	0	0
T13	25693	5506	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	17377	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8870556	0	0
T13	25693	5506	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	17381	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1542	0	0
T13	25693	25	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	9	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	25	0	0
T51	0	28	0	0
T55	0	26	0	0
T56	0	27	0	0
T57	0	23	0	0
T80	0	30	0	0
T90	0	4	0	0
T123	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1505	0	0
T13	25693	25	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	9	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	25	0	0
T51	0	28	0	0
T55	0	26	0	0
T56	0	27	0	0
T57	0	23	0	0
T80	0	30	0	0
T90	0	4	0	0
T123	0	15	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	782	0	0
T13	25693	25	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	9	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T51	0	28	0	0
T55	0	26	0	0
T57	0	23	0	0
T89	0	4	0	0
T90	0	4	0	0
T102	0	12	0	0
T123	0	15	0	0
T247	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	782	0	0
T13	25693	25	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	9	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T51	0	28	0	0
T55	0	26	0	0
T57	0	23	0	0
T89	0	4	0	0
T90	0	4	0	0
T102	0	12	0	0
T123	0	15	0	0
T247	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	60715	0	0
T13	25693	3712	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	1052	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T51	0	3913	0	0
T55	0	2308	0	0
T57	0	3019	0	0
T89	0	36	0	0
T90	0	61	0	0
T102	0	882	0	0
T123	0	965	0	0
T247	0	2223	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	711	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T51	0	22	0	0
T55	0	25	0	0
T57	0	21	0	0
T89	0	4	0	0
T90	0	4	0	0
T102	0	11	0	0
T123	0	14	0	0
T247	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T13,T17,T50

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T50
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T17,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T50
0	1	Covered	T136,T216,T86
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T50
0	1	Covered	T13,T17,T50
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T50
1	-	Covered	T13,T17,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T17,T50
0	1	Covered	T13,T17,T50
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T50
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T50
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T22,T51,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T50
DetectSt	-	-	-	-	1	-	-	Covered	T136,T216,T86
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T50
DetectSt	-	-	-	-	0	0	-	Covered	T13,T17,T50
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T50
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	788	0	0
CntIncr_A	9988962	43967	0	0
CntNoWrap_A	9988962	9322445	0	0
DetectStDropOut_A	9988962	47	0	0
DetectedOut_A	9988962	15097	0	0
DetectedPulseOut_A	9988962	317	0	0
DisabledIdleSt_A	9988962	8977633	0	0
DisabledNoDetection_A	9988962	8979358	0	0
EnterDebounceSt_A	9988962	422	0	0
EnterDetectSt_A	9988962	367	0	0
EnterStableSt_A	9988962	317	0	0
PulseIsPulse_A	9988962	317	0	0
StayInStableSt	9988962	14749	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	283	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	788	0	0
T13	25693	2	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T21	0	6	0	0
T22	0	13	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T50	0	10	0	0
T51	0	11	0	0
T55	0	2	0	0
T57	0	4	0	0
T91	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	43967	0	0
T13	25693	300	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	156	0	0
T18	2439	0	0	0
T21	0	210	0	0
T22	0	430	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	256	0	0
T50	0	190	0	0
T51	0	335	0	0
T55	0	75	0	0
T57	0	166	0	0
T91	0	387	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9322445	0	0
T13	25693	25285	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23943	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	47	0	0
T44	182254	0	0	0
T46	733	0	0	0
T75	0	1	0	0
T86	0	1	0	0
T108	0	5	0	0
T136	10969	4	0	0
T179	0	3	0	0
T188	550	0	0	0
T202	0	7	0	0
T216	12521	7	0	0
T217	7836	0	0	0
T226	418	0	0	0
T227	28587	0	0	0
T228	402	0	0	0
T248	0	6	0	0
T249	0	4	0	0
T250	0	2	0	0
T251	515	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	15097	0	0
T13	25693	58	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	236	0	0
T18	2439	0	0	0
T21	0	90	0	0
T22	0	368	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	126	0	0
T50	0	175	0	0
T51	0	441	0	0
T55	0	54	0	0
T57	0	144	0	0
T91	0	34	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	317	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	3	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	2	0	0
T50	0	5	0	0
T51	0	5	0	0
T55	0	1	0	0
T57	0	2	0	0
T91	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8977633	0	0
T13	25693	21550	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	22888	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8979358	0	0
T13	25693	21551	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	22893	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	422	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	3	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	7	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	2	0	0
T50	0	5	0	0
T51	0	6	0	0
T55	0	1	0	0
T57	0	2	0	0
T91	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	367	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	3	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	2	0	0
T50	0	5	0	0
T51	0	5	0	0
T55	0	1	0	0
T57	0	2	0	0
T91	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	317	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	3	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	2	0	0
T50	0	5	0	0
T51	0	5	0	0
T55	0	1	0	0
T57	0	2	0	0
T91	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	317	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	3	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	2	0	0
T50	0	5	0	0
T51	0	5	0	0
T55	0	1	0	0
T57	0	2	0	0
T91	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	14749	0	0
T13	25693	57	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	233	0	0
T18	2439	0	0	0
T21	0	87	0	0
T22	0	362	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	124	0	0
T50	0	170	0	0
T51	0	431	0	0
T55	0	53	0	0
T57	0	142	0	0
T91	0	31	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	283	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	3	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	6	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	2	0	0
T48	0	2	0	0
T50	0	5	0	0
T55	0	1	0	0
T57	0	2	0	0
T91	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T13,T17,T49
1	1	Covered	T13,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T80,T56,T100
1	0	Covered	T80,T56,T57

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
1	0	Covered	T81,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T49
1	-	Covered	T13,T17,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T49
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T13,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T241,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T80,T56,T57
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	0	0	-	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	3058	0	0
CntIncr_A	9988962	113773	0	0
CntNoWrap_A	9988962	9320175	0	0
DetectStDropOut_A	9988962	363	0	0
DetectedOut_A	9988962	83290	0	0
DetectedPulseOut_A	9988962	911	0	0
DisabledIdleSt_A	9988962	8856749	0	0
DisabledNoDetection_A	9988962	8858923	0	0
EnterDebounceSt_A	9988962	1546	0	0
EnterDetectSt_A	9988962	1512	0	0
EnterStableSt_A	9988962	911	0	0
PulseIsPulse_A	9988962	911	0	0
StayInStableSt	9988962	82279	0	0
gen_high_event_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	794	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	3058	0	0
T13	25693	48	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	14	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	26	0	0
T51	0	22	0	0
T55	0	34	0	0
T56	0	56	0	0
T57	0	46	0	0
T80	0	60	0	0
T90	0	12	0	0
T123	0	36	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	113773	0	0
T13	25693	6384	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	476	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	819	0	0
T51	0	946	0	0
T55	0	1173	0	0
T56	0	1287	0	0
T57	0	2462	0	0
T80	0	1784	0	0
T90	0	276	0	0
T123	0	1404	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9320175	0	0
T13	25693	25239	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23935	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	363	0	0
T21	26108	0	0	0
T22	20165	0	0	0
T39	2010	0	0	0
T51	28724	0	0	0
T56	0	21	0	0
T64	491	0	0	0
T80	13348	22	0	0
T90	11929	0	0	0
T100	0	13	0	0
T101	0	23	0	0
T102	0	5	0	0
T103	0	28	0	0
T105	0	9	0	0
T241	0	25	0	0
T243	422	0	0	0
T244	442	0	0	0
T245	3016	0	0	0
T252	0	5	0	0
T253	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	83290	0	0
T13	25693	3992	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	333	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	973	0	0
T51	0	949	0	0
T55	0	834	0	0
T90	0	183	0	0
T123	0	755	0	0
T124	0	3540	0	0
T227	0	1245	0	0
T246	0	1680	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	911	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	7	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	13	0	0
T51	0	11	0	0
T55	0	17	0	0
T90	0	6	0	0
T123	0	18	0	0
T124	0	23	0	0
T227	0	10	0	0
T246	0	31	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8856749	0	0
T13	25693	5876	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	18075	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8858923	0	0
T13	25693	5877	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	18082	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1546	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	7	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	13	0	0
T51	0	11	0	0
T55	0	17	0	0
T56	0	28	0	0
T57	0	23	0	0
T80	0	30	0	0
T90	0	6	0	0
T123	0	18	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1512	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	7	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	13	0	0
T51	0	11	0	0
T55	0	17	0	0
T56	0	28	0	0
T57	0	23	0	0
T80	0	30	0	0
T90	0	6	0	0
T123	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	911	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	7	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	13	0	0
T51	0	11	0	0
T55	0	17	0	0
T90	0	6	0	0
T123	0	18	0	0
T124	0	23	0	0
T227	0	10	0	0
T246	0	31	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	911	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	7	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	13	0	0
T51	0	11	0	0
T55	0	17	0	0
T90	0	6	0	0
T123	0	18	0	0
T124	0	23	0	0
T227	0	10	0	0
T246	0	31	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	82279	0	0
T13	25693	3968	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	326	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	958	0	0
T51	0	937	0	0
T55	0	815	0	0
T90	0	177	0	0
T123	0	735	0	0
T124	0	3515	0	0
T227	0	1232	0	0
T246	0	1648	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	794	0	0
T13	25693	24	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	7	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	11	0	0
T51	0	10	0	0
T55	0	15	0	0
T90	0	6	0	0
T123	0	16	0	0
T124	0	21	0	0
T227	0	7	0	0
T246	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T13,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T13,T15,T16
1	1	Covered	T13,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T49,T50
0	1	Covered	T21,T91,T136
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T49,T50
0	1	Covered	T13,T50,T21
1	0	Covered	T74,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T49,T50
1	-	Covered	T13,T50,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T49,T50
0	1	Covered	T13,T49,T50
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T49,T50
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T55,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T21,T91,T136
DetectSt	-	-	-	-	0	1	-	Covered	T13,T49,T50
DetectSt	-	-	-	-	0	0	-	Covered	T13,T49,T50
StableSt	-	-	-	-	-	-	1	Covered	T13,T50,T21
StableSt	-	-	-	-	-	-	0	Covered	T13,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	845	0	0
CntIncr_A	9988962	47337	0	0
CntNoWrap_A	9988962	9322388	0	0
DetectStDropOut_A	9988962	56	0	0
DetectedOut_A	9988962	17561	0	0
DetectedPulseOut_A	9988962	336	0	0
DisabledIdleSt_A	9988962	8946939	0	0
DisabledNoDetection_A	9988962	8948618	0	0
EnterDebounceSt_A	9988962	450	0	0
EnterDetectSt_A	9988962	395	0	0
EnterStableSt_A	9988962	336	0	0
PulseIsPulse_A	9988962	336	0	0
StayInStableSt	9988962	17186	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	293	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	845	0	0
T13	25693	2	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	10	0	0
T22	0	2	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	9	0	0
T49	0	4	0	0
T50	0	23	0	0
T55	0	1	0	0
T91	0	4	0	0
T123	0	4	0	0
T124	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	47337	0	0
T13	25693	290	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	515	0	0
T22	0	121	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	629	0	0
T49	0	92	0	0
T50	0	705	0	0
T55	0	37	0	0
T91	0	280	0	0
T123	0	160	0	0
T124	0	348	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9322388	0	0
T13	25693	25285	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23949	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	56	0	0
T21	26108	2	0	0
T22	20165	0	0	0
T39	2010	0	0	0
T51	28724	0	0	0
T64	491	0	0	0
T73	0	3	0	0
T90	11929	0	0	0
T91	11898	2	0	0
T104	0	5	0	0
T136	0	9	0	0
T148	0	2	0	0
T243	422	0	0	0
T244	442	0	0	0
T245	3016	0	0	0
T254	0	2	0	0
T255	0	1	0	0
T256	0	5	0	0
T257	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	17561	0	0
T13	25693	68	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	169	0	0
T22	0	4	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	206	0	0
T44	0	82	0	0
T49	0	119	0	0
T50	0	124	0	0
T123	0	154	0	0
T124	0	204	0	0
T222	0	596	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	336	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T49	0	2	0	0
T50	0	11	0	0
T123	0	2	0	0
T124	0	3	0	0
T222	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8946939	0	0
T13	25693	21295	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23615	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8948618	0	0
T13	25693	21297	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23623	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	450	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	5	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	5	0	0
T49	0	2	0	0
T50	0	12	0	0
T55	0	1	0	0
T91	0	2	0	0
T123	0	2	0	0
T124	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	395	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	5	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T49	0	2	0	0
T50	0	11	0	0
T91	0	2	0	0
T123	0	2	0	0
T124	0	3	0	0
T222	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	336	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T49	0	2	0	0
T50	0	11	0	0
T123	0	2	0	0
T124	0	3	0	0
T222	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	336	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T49	0	2	0	0
T50	0	11	0	0
T123	0	2	0	0
T124	0	3	0	0
T222	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	17186	0	0
T13	25693	67	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	166	0	0
T22	0	3	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	202	0	0
T44	0	81	0	0
T49	0	115	0	0
T50	0	113	0	0
T123	0	152	0	0
T124	0	201	0	0
T222	0	588	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	293	0	0
T13	25693	1	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	0	0	0
T18	2439	0	0	0
T21	0	3	0	0
T22	0	1	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	4	0	0
T44	0	1	0	0
T50	0	11	0	0
T123	0	2	0	0
T124	0	3	0	0
T222	0	8	0	0
T227	0	2	0	0