Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T13,T17,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T13,T17,T49
1	1	Covered	T13,T17,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T100,T101,T246
1	0	Covered	T90,T246,T258

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T17,T49
1	-	Covered	T13,T17,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T17,T49
0	1	Covered	T13,T17,T49
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T17,T49
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T49
IdleSt	0	-	-	-	-	-	-	Covered	T13,T17,T49
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T17,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T89,T241,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	1	-	-	Covered	T90,T100,T101
DetectSt	-	-	-	-	0	1	-	Covered	T13,T17,T49
DetectSt	-	-	-	-	0	0	-	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	1	Covered	T13,T17,T49
StableSt	-	-	-	-	-	-	0	Covered	T13,T17,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	2786	0	0
CntIncr_A	9988962	106019	0	0
CntNoWrap_A	9988962	9320447	0	0
DetectStDropOut_A	9988962	395	0	0
DetectedOut_A	9988962	79554	0	0
DetectedPulseOut_A	9988962	804	0	0
DisabledIdleSt_A	9988962	8854878	0	0
DisabledNoDetection_A	9988962	8857048	0	0
EnterDebounceSt_A	9988962	1411	0	0
EnterDetectSt_A	9988962	1377	0	0
EnterStableSt_A	9988962	804	0	0
PulseIsPulse_A	9988962	804	0	0
StayInStableSt	9988962	78646	0	0
gen_high_event_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	700	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	2786	0	0
T13	25693	26	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	20	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	18	0	0
T51	0	56	0	0
T55	0	34	0	0
T56	0	14	0	0
T57	0	12	0	0
T80	0	16	0	0
T90	0	12	0	0
T123	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	106019	0	0
T13	25693	3458	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	700	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	468	0	0
T51	0	2604	0	0
T55	0	1037	0	0
T56	0	315	0	0
T57	0	360	0	0
T80	0	424	0	0
T90	0	449	0	0
T123	0	2116	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9320447	0	0
T13	25693	25261	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23929	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	395	0	0
T68	12689	0	0	0
T92	661	0	0	0
T93	780	0	0	0
T100	5233	22	0	0
T101	0	6	0	0
T103	0	24	0	0
T105	0	27	0	0
T135	502	0	0	0
T136	10969	0	0	0
T164	0	18	0	0
T221	13030	0	0	0
T222	33510	0	0	0
T241	0	1	0	0
T246	0	8	0	0
T251	515	0	0	0
T253	0	14	0	0
T258	0	8	0	0
T259	0	11	0	0
T260	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	79554	0	0
T13	25693	986	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	1421	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	1261	0	0
T51	0	3695	0	0
T55	0	970	0	0
T56	0	1666	0	0
T57	0	293	0	0
T80	0	1754	0	0
T123	0	1394	0	0
T124	0	1764	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	804	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	10	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	9	0	0
T51	0	28	0	0
T55	0	17	0	0
T56	0	7	0	0
T57	0	6	0	0
T80	0	8	0	0
T123	0	23	0	0
T124	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8854878	0	0
T13	25693	8084	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	17112	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8857048	0	0
T13	25693	8085	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	17115	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1411	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	10	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	9	0	0
T51	0	28	0	0
T55	0	17	0	0
T56	0	7	0	0
T57	0	6	0	0
T80	0	8	0	0
T90	0	6	0	0
T123	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	1377	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	10	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	9	0	0
T51	0	28	0	0
T55	0	17	0	0
T56	0	7	0	0
T57	0	6	0	0
T80	0	8	0	0
T90	0	6	0	0
T123	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	804	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	10	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	9	0	0
T51	0	28	0	0
T55	0	17	0	0
T56	0	7	0	0
T57	0	6	0	0
T80	0	8	0	0
T123	0	23	0	0
T124	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	804	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	10	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	9	0	0
T51	0	28	0	0
T55	0	17	0	0
T56	0	7	0	0
T57	0	6	0	0
T80	0	8	0	0
T123	0	23	0	0
T124	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	78646	0	0
T13	25693	973	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	1407	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	1250	0	0
T51	0	3661	0	0
T55	0	951	0	0
T56	0	1652	0	0
T57	0	287	0	0
T80	0	1743	0	0
T123	0	1365	0	0
T124	0	1747	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	700	0	0
T13	25693	13	0	0
T14	921	0	0	0
T15	10236	0	0	0
T16	2300	0	0	0
T17	24401	6	0	0
T18	2439	0	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	7	0	0
T51	0	22	0	0
T55	0	15	0	0
T57	0	6	0	0
T80	0	5	0	0
T123	0	17	0	0
T124	0	15	0	0
T221	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T17,T49
1	Covered	T38,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T38,T13,T14
1	1	Covered	T38,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T17,T49,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T38,T13,T14	VC_COV_UNR
1	Covered	T17,T49,T50

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T17,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T17,T49
1	0	Covered	T13,T15,T16
1	1	Covered	T17,T49,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T49,T50
0	1	Covered	T104,T216,T148
1	0	Covered	T74,T75

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T49,T50
0	1	Covered	T17,T50,T21
1	0	Covered	T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T49,T50
1	-	Covered	T17,T50,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6
DetectSt	168	Covered	T6
IdleSt	163	Covered	T6
StableSt	191	Covered	T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6
DebounceSt->IdleSt	163	Covered	T6
DetectSt->IdleSt	186	Covered	T6
DetectSt->StableSt	191	Covered	T6
IdleSt->DebounceSt	148	Covered	T6
StableSt->IdleSt	206	Covered	T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T49,T50
0	1	Covered	T17,T49,T50
0	0	Excluded	T38,T13,T14	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T49,T50
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T49,T50
IdleSt	0	-	-	-	-	-	-	Covered	T38,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T74,T75
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T80,T48
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T49,T50
DetectSt	-	-	-	-	1	-	-	Covered	T104,T216,T148
DetectSt	-	-	-	-	0	1	-	Covered	T17,T49,T50
DetectSt	-	-	-	-	0	0	-	Covered	T17,T49,T50
StableSt	-	-	-	-	-	-	1	Covered	T17,T50,T21
StableSt	-	-	-	-	-	-	0	Covered	T17,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T38,T13,T14
0	Covered	T38,T13,T14

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9988962	938	0	0
CntIncr_A	9988962	50974	0	0
CntNoWrap_A	9988962	9322295	0	0
DetectStDropOut_A	9988962	37	0	0
DetectedOut_A	9988962	18325	0	0
DetectedPulseOut_A	9988962	402	0	0
DisabledIdleSt_A	9988962	8954530	0	0
DisabledNoDetection_A	9988962	8956203	0	0
EnterDebounceSt_A	9988962	495	0	0
EnterDetectSt_A	9988962	443	0	0
EnterStableSt_A	9988962	402	0	0
PulseIsPulse_A	9988962	402	0	0
StayInStableSt	9988962	17900	0	0
gen_high_level_sva.HighLevelEvent_A	9988962	9325596	0	0
gen_not_sticky_sva.StableStDropOut_A	9988962	378	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	938	0	0
T17	24401	8	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	18	0	0
T22	0	20	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	4	0	0
T50	0	13	0	0
T51	0	4	0	0
T55	0	4	0	0
T56	0	14	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	7	0	0
T91	0	4	0	0
T97	412	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	50974	0	0
T17	24401	200	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	939	0	0
T22	0	690	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	84	0	0
T50	0	419	0	0
T51	0	178	0	0
T55	0	116	0	0
T56	0	301	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	220	0	0
T91	0	268	0	0
T97	412	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9322295	0	0
T13	25693	25287	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	23941	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	37	0	0
T104	11959	4	0	0
T148	0	12	0	0
T155	220337	0	0	0
T193	0	4	0	0
T216	0	1	0	0
T249	0	1	0	0
T261	0	2	0	0
T262	0	1	0	0
T263	0	1	0	0
T264	0	9	0	0
T265	0	2	0	0
T266	699	0	0	0
T267	26968	0	0	0
T268	455	0	0	0
T269	402	0	0	0
T270	414	0	0	0
T271	493	0	0	0
T272	11636	0	0	0
T273	443	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	18325	0	0
T17	24401	324	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	148	0	0
T22	0	575	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	127	0	0
T50	0	41	0	0
T51	0	114	0	0
T55	0	144	0	0
T56	0	612	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	181	0	0
T91	0	13	0	0
T97	412	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	402	0	0
T17	24401	4	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	9	0	0
T22	0	10	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	2	0	0
T50	0	6	0	0
T51	0	2	0	0
T55	0	2	0	0
T56	0	7	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	3	0	0
T91	0	2	0	0
T97	412	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8954530	0	0
T13	25693	24301	0	0
T14	921	520	0	0
T15	10236	3706	0	0
T16	2300	697	0	0
T17	24401	22531	0	0
T30	862	461	0	0
T31	405	4	0	0
T32	649	248	0	0
T33	525	124	0	0
T38	523	122	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	8956203	0	0
T13	25693	24303	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	22535	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	495	0	0
T17	24401	4	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	9	0	0
T22	0	10	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	2	0	0
T50	0	7	0	0
T51	0	2	0	0
T55	0	2	0	0
T56	0	7	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	4	0	0
T91	0	2	0	0
T97	412	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	443	0	0
T17	24401	4	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	9	0	0
T22	0	10	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	2	0	0
T50	0	6	0	0
T51	0	2	0	0
T55	0	2	0	0
T56	0	7	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	3	0	0
T91	0	2	0	0
T97	412	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	402	0	0
T17	24401	4	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	9	0	0
T22	0	10	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	2	0	0
T50	0	6	0	0
T51	0	2	0	0
T55	0	2	0	0
T56	0	7	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	3	0	0
T91	0	2	0	0
T97	412	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	402	0	0
T17	24401	4	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	9	0	0
T22	0	10	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	2	0	0
T50	0	6	0	0
T51	0	2	0	0
T55	0	2	0	0
T56	0	7	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	3	0	0
T91	0	2	0	0
T97	412	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	17900	0	0
T17	24401	320	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	139	0	0
T22	0	565	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T49	0	123	0	0
T50	0	35	0	0
T51	0	110	0	0
T55	0	142	0	0
T56	0	605	0	0
T58	422	0	0	0
T59	494	0	0	0
T80	0	175	0	0
T91	0	11	0	0
T97	412	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	9325596	0	0
T13	25693	25289	0	0
T14	921	521	0	0
T15	10236	3720	0	0
T16	2300	700	0	0
T17	24401	23957	0	0
T30	862	462	0	0
T31	405	5	0	0
T32	649	249	0	0
T33	525	125	0	0
T38	523	123	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9988962	378	0	0
T17	24401	4	0	0
T18	2439	0	0	0
T19	1323	0	0	0
T21	0	9	0	0
T22	0	10	0	0
T30	862	0	0	0
T31	405	0	0	0
T32	649	0	0	0
T33	525	0	0	0
T41	0	3	0	0
T50	0	6	0	0
T55	0	2	0	0
T56	0	7	0	0
T58	422	0	0	0
T59	494	0	0	0
T91	0	2	0	0
T97	412	0	0	0
T123	0	6	0	0
T124	0	1	0	0