Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1318649788	9981	0	0
auto_block_debounce_ctl_rd_A	1318649788	2348	0	0
auto_block_out_ctl_rd_A	1318649788	2759	0	0
com_det_ctl_0_rd_A	1318649788	4652	0	0
com_det_ctl_1_rd_A	1318649788	4919	0	0
com_det_ctl_2_rd_A	1318649788	4893	0	0
com_det_ctl_3_rd_A	1318649788	4666	0	0
com_out_ctl_0_rd_A	1318649788	5137	0	0
com_out_ctl_1_rd_A	1318649788	5250	0	0
com_out_ctl_2_rd_A	1318649788	5249	0	0
com_out_ctl_3_rd_A	1318649788	5435	0	0
com_pre_det_ctl_0_rd_A	1318649788	2020	0	0
com_pre_det_ctl_1_rd_A	1318649788	2004	0	0
com_pre_det_ctl_2_rd_A	1318649788	2023	0	0
com_pre_det_ctl_3_rd_A	1318649788	1909	0	0
com_pre_sel_ctl_0_rd_A	1318649788	5627	0	0
com_pre_sel_ctl_1_rd_A	1318649788	5506	0	0
com_pre_sel_ctl_2_rd_A	1318649788	5391	0	0
com_pre_sel_ctl_3_rd_A	1318649788	5444	0	0
com_sel_ctl_0_rd_A	1318649788	5505	0	0
com_sel_ctl_1_rd_A	1318649788	5099	0	0
com_sel_ctl_2_rd_A	1318649788	5607	0	0
com_sel_ctl_3_rd_A	1318649788	5355	0	0
ec_rst_ctl_rd_A	1318649788	3051	0	0
intr_enable_rd_A	1318649788	3177	0	0
key_intr_ctl_rd_A	1318649788	4402	0	0
key_intr_debounce_ctl_rd_A	1318649788	1991	0	0
key_invert_ctl_rd_A	1318649788	5828	0	0
pin_allowed_ctl_rd_A	1318649788	6089	0	0
pin_out_ctl_rd_A	1318649788	5128	0	0
pin_out_value_rd_A	1318649788	5053	0	0
regwen_rd_A	1318649788	2563	0	0
ulp_ac_debounce_ctl_rd_A	1318649788	2237	0	0
ulp_ctl_rd_A	1318649788	2111	0	0
ulp_lid_debounce_ctl_rd_A	1318649788	2062	0	0
ulp_pwrb_debounce_ctl_rd_A	1318649788	2036	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	9981	0	0
T1	40366	68	0	0
T2	38253	13	0	0
T7	199254	0	0	0
T9	0	4	0	0
T23	197742	0	0	0
T24	194472	425	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	773	0	0
T28	204177	671	0	0
T29	50620	0	0	0
T52	0	3	0	0
T277	0	372	0	0
T278	0	822	0	0
T279	0	340	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2348	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	31	0	0
T6	118820	59	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	46	0	0
T53	0	19	0	0
T276	0	12	0	0
T278	0	1	0	0
T279	0	7	0	0
T280	0	25	0	0
T288	0	79	0	0
T289	0	35	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2759	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	42	0	0
T6	118820	81	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	30	0	0
T37	0	30	0	0
T53	0	14	0	0
T278	0	9	0	0
T280	0	20	0	0
T288	0	134	0	0
T289	0	55	0	0
T290	0	8	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	4652	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	22	0	0
T6	118820	82	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	70	0	0
T53	0	17	0	0
T276	0	35	0	0
T278	0	14	0	0
T279	0	16	0	0
T280	0	15	0	0
T288	0	48	0	0
T290	0	7	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	4919	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	25	0	0
T6	118820	103	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	39	0	0
T53	0	6	0	0
T276	0	17	0	0
T279	0	4	0	0
T280	0	32	0	0
T288	0	32	0	0
T289	0	23	0	0
T290	0	3	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	4893	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	5	0	0
T6	118820	71	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	65	0	0
T53	0	11	0	0
T276	0	3	0	0
T278	0	1	0	0
T279	0	6	0	0
T280	0	26	0	0
T288	0	42	0	0
T290	0	4	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	4666	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	80	0	0
T6	118820	35	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	42	0	0
T53	0	29	0	0
T276	0	4	0	0
T279	0	5	0	0
T280	0	7	0	0
T288	0	32	0	0
T289	0	5	0	0
T290	0	11	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5137	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	43	0	0
T6	118820	61	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	49	0	0
T37	0	9	0	0
T276	0	9	0	0
T279	0	13	0	0
T288	0	96	0	0
T289	0	52	0	0
T290	0	2	0	0
T291	0	9	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5250	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	14	0	0
T6	118820	84	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	58	0	0
T53	0	4	0	0
T276	0	7	0	0
T278	0	26	0	0
T280	0	29	0	0
T288	0	81	0	0
T289	0	29	0	0
T290	0	16	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5249	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	38	0	0
T6	118820	80	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	62	0	0
T53	0	8	0	0
T276	0	15	0	0
T278	0	18	0	0
T279	0	4	0	0
T280	0	9	0	0
T288	0	138	0	0
T290	0	7	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5435	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	12	0	0
T6	118820	85	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	39	0	0
T53	0	7	0	0
T276	0	3	0	0
T278	0	25	0	0
T279	0	8	0	0
T280	0	14	0	0
T288	0	97	0	0
T289	0	51	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2020	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	66	0	0
T6	118820	66	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	39	0	0
T53	0	18	0	0
T276	0	14	0	0
T278	0	15	0	0
T280	0	6	0	0
T288	0	50	0	0
T289	0	15	0	0
T290	0	14	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2004	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	59	0	0
T6	118820	53	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	46	0	0
T53	0	3	0	0
T276	0	13	0	0
T278	0	34	0	0
T279	0	1	0	0
T280	0	27	0	0
T288	0	51	0	0
T290	0	15	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2023	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	50	0	0
T6	118820	62	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	55	0	0
T53	0	7	0	0
T278	0	4	0	0
T280	0	18	0	0
T288	0	43	0	0
T289	0	19	0	0
T290	0	1	0	0
T292	0	1	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1909	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	69	0	0
T6	118820	48	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	24	0	0
T53	0	13	0	0
T276	0	9	0	0
T278	0	4	0	0
T279	0	7	0	0
T280	0	18	0	0
T288	0	34	0	0
T290	0	6	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5627	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	14	0	0
T6	118820	55	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	57	0	0
T53	0	11	0	0
T276	0	15	0	0
T278	0	22	0	0
T279	0	12	0	0
T280	0	6	0	0
T288	0	133	0	0
T290	0	8	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5506	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	44	0	0
T6	118820	68	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	43	0	0
T53	0	14	0	0
T276	0	7	0	0
T278	0	10	0	0
T279	0	13	0	0
T280	0	40	0	0
T288	0	157	0	0
T290	0	3	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5391	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	42	0	0
T6	118820	73	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	38	0	0
T53	0	7	0	0
T276	0	4	0	0
T278	0	6	0	0
T279	0	6	0	0
T280	0	15	0	0
T288	0	106	0	0
T289	0	76	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5444	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	11	0	0
T6	118820	53	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	23	0	0
T53	0	22	0	0
T276	0	22	0	0
T278	0	6	0	0
T279	0	23	0	0
T280	0	7	0	0
T288	0	146	0	0
T289	0	55	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5505	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	47	0	0
T6	118820	98	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	53	0	0
T37	0	9	0	0
T53	0	1	0	0
T278	0	8	0	0
T279	0	14	0	0
T280	0	12	0	0
T288	0	104	0	0
T289	0	78	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5099	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	40	0	0
T6	118820	75	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	39	0	0
T53	0	3	0	0
T276	0	13	0	0
T278	0	13	0	0
T279	0	13	0	0
T280	0	28	0	0
T288	0	121	0	0
T290	0	2	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5607	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	66	0	0
T6	118820	51	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	50	0	0
T37	0	23	0	0
T53	0	21	0	0
T278	0	14	0	0
T280	0	21	0	0
T288	0	110	0	0
T289	0	90	0	0
T290	0	14	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5355	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	58	0	0
T6	118820	120	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	39	0	0
T53	0	18	0	0
T276	0	2	0	0
T278	0	14	0	0
T279	0	4	0	0
T280	0	3	0	0
T288	0	94	0	0
T290	0	9	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	3051	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	12	0	0
T6	118820	68	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	54	0	0
T53	0	15	0	0
T276	0	5	0	0
T278	0	3	0	0
T279	0	12	0	0
T280	0	18	0	0
T288	0	36	0	0
T290	0	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	3177	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	35	0	0
T6	118820	471	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	11	0	0
T26	91060	12	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	242	0	0
T276	0	5	0	0
T278	0	30	0	0
T279	0	6	0	0
T280	0	17	0	0
T293	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	4402	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	44	0	0
T6	118820	71	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	22	0	0
T53	0	20	0	0
T276	0	16	0	0
T278	0	3	0	0
T279	0	15	0	0
T280	0	23	0	0
T288	0	211	0	0
T290	0	6	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1991	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	60	0	0
T6	118820	90	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	29	0	0
T53	0	6	0	0
T276	0	7	0	0
T278	0	7	0	0
T279	0	17	0	0
T280	0	1	0	0
T288	0	43	0	0
T290	0	9	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5828	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	55	0	0
T6	118820	53	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	13	0	0
T53	0	2	0	0
T276	0	4	0	0
T278	0	7	0	0
T279	0	5	0	0
T288	0	254	0	0
T289	0	117	0	0
T290	0	6	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6089	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	21	0	0
T6	118820	58	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	33	0	0
T37	0	3	0	0
T53	0	8	0	0
T276	0	20	0	0
T278	0	33	0	0
T280	0	8	0	0
T288	0	402	0	0
T289	0	221	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5128	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	67	0	0
T6	118820	93	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	38	0	0
T53	0	20	0	0
T276	0	6	0	0
T278	0	3	0	0
T279	0	8	0	0
T280	0	26	0	0
T288	0	264	0	0
T290	0	11	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5053	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	21	0	0
T6	118820	103	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	40	0	0
T53	0	8	0	0
T278	0	16	0	0
T279	0	5	0	0
T280	0	18	0	0
T288	0	203	0	0
T289	0	99	0	0
T290	0	21	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2563	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	54	0	0
T6	118820	398	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	46	0	0
T53	0	236	0	0
T276	0	10	0	0
T278	0	5	0	0
T279	0	7	0	0
T280	0	31	0	0
T288	0	36	0	0
T290	0	8	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2237	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	47	0	0
T6	118820	90	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	62	0	0
T53	0	6	0	0
T276	0	34	0	0
T278	0	10	0	0
T279	0	1	0	0
T280	0	19	0	0
T288	0	35	0	0
T290	0	17	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2111	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	53	0	0
T6	118820	63	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	55	0	0
T37	0	2	0	0
T53	0	6	0	0
T276	0	14	0	0
T280	0	35	0	0
T288	0	38	0	0
T289	0	18	0	0
T290	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2062	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	33	0	0
T6	118820	48	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	71	0	0
T276	0	8	0	0
T278	0	5	0	0
T279	0	5	0	0
T280	0	6	0	0
T288	0	39	0	0
T289	0	31	0	0
T290	0	15	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2036	0	0
T1	40366	0	0	0
T2	38253	0	0	0
T3	0	49	0	0
T6	118820	92	0	0
T7	199254	0	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T34	0	55	0	0
T53	0	4	0	0
T276	0	11	0	0
T278	0	15	0	0
T279	0	13	0	0
T280	0	7	0	0
T288	0	52	0	0
T290	0	8	0	0