Unified Coverage Report :: Module :: sysrst_ctrl_pin

Module : sysrst_ctrl_pin

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_pin	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_pin

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cfg_ac_present_i_pin	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_pin

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	147	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
91	1	1
101	1	1
111	1	1
121	1	1
131	1	1
143	8	8
147	1	1

---

Cond Coverage for Module : sysrst_ctrl_pin

	Total	Covered	Percent
Conditions	96	96	100.00
Logical	96	96	100.00
Non-Logical	0	0
Event	0	0

 LINE       143
 EXPRESSION ((aon_enabled[0] && aon_allowed0[0] && ((!aon_values[0]))) ? 1'b0 : ((aon_enabled[0] && aon_allowed1[0] && aon_values[0]) ? 1'b1 : inputs[0]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T15,T16
1	Covered	T38,T13,T14

 LINE       143
 SUB-EXPRESSION (aon_enabled[0] && aon_allowed0[0] && ((!aon_values[0])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T33
1	0	1	Covered	T38,T15,T33
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T13,T14

 LINE       143
 SUB-EXPRESSION ((aon_enabled[0] && aon_allowed1[0] && aon_values[0]) ? 1'b1 : inputs[0])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T15,T16
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[0] && aon_allowed1[0] && aon_values[0])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T15,T16,T33
1	1	0	Covered	T38,T15,T18
1	1	1	Covered	T38,T15,T16

 LINE       143
 EXPRESSION ((aon_enabled[1] && aon_allowed0[1] && ((!aon_values[1]))) ? 1'b0 : ((aon_enabled[1] && aon_allowed1[1] && aon_values[1]) ? 1'b1 : inputs[1]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T15
1	Covered	T38,T13,T14

 LINE       143
 SUB-EXPRESSION (aon_enabled[1] && aon_allowed0[1] && ((!aon_values[1])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T13,T15
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T13,T14

 LINE       143
 SUB-EXPRESSION ((aon_enabled[1] && aon_allowed1[1] && aon_values[1]) ? 1'b1 : inputs[1])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T15
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[1] && aon_allowed1[1] && aon_values[1])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T15,T16,T18
1	1	1	Covered	T38,T15,T16

 LINE       143
 EXPRESSION ((aon_enabled[2] && aon_allowed0[2] && ((!aon_values[2]))) ? 1'b0 : ((aon_enabled[2] && aon_allowed1[2] && aon_values[2]) ? 1'b1 : inputs[2]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[2] && aon_allowed0[2] && ((!aon_values[2])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION ((aon_enabled[2] && aon_allowed1[2] && aon_values[2]) ? 1'b1 : inputs[2])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[2] && aon_allowed1[2] && aon_values[2])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T15,T16

 LINE       143
 EXPRESSION ((aon_enabled[3] && aon_allowed0[3] && ((!aon_values[3]))) ? 1'b0 : ((aon_enabled[3] && aon_allowed1[3] && aon_values[3]) ? 1'b1 : inputs[3]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[3] && aon_allowed0[3] && ((!aon_values[3])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T33
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION ((aon_enabled[3] && aon_allowed1[3] && aon_values[3]) ? 1'b1 : inputs[3])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[3] && aon_allowed1[3] && aon_values[3])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T33
1	1	1	Covered	T38,T15,T16

 LINE       143
 EXPRESSION ((aon_enabled[4] && aon_allowed0[4] && ((!aon_values[4]))) ? 1'b0 : ((aon_enabled[4] && aon_allowed1[4] && aon_values[4]) ? 1'b1 : inputs[4]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T33

 LINE       143
 SUB-EXPRESSION (aon_enabled[4] && aon_allowed0[4] && ((!aon_values[4])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T15,T16,T33

 LINE       143
 SUB-EXPRESSION ((aon_enabled[4] && aon_allowed1[4] && aon_values[4]) ? 1'b1 : inputs[4])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T15,T16,T33

 LINE       143
 SUB-EXPRESSION (aon_enabled[4] && aon_allowed1[4] && aon_values[4])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T15,T16,T33

 LINE       143
 EXPRESSION ((aon_enabled[5] && aon_allowed0[5] && ((!aon_values[5]))) ? 1'b0 : ((aon_enabled[5] && aon_allowed1[5] && aon_values[5]) ? 1'b1 : inputs[5]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[5] && aon_allowed0[5] && ((!aon_values[5])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T16,T33
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T33
1	1	1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION ((aon_enabled[5] && aon_allowed1[5] && aon_values[5]) ? 1'b1 : inputs[5])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[5] && aon_allowed1[5] && aon_values[5])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T15,T16

 LINE       143
 EXPRESSION ((aon_enabled[6] && aon_allowed0[6] && ((!aon_values[6]))) ? 1'b0 : ((aon_enabled[6] && aon_allowed1[6] && aon_values[6]) ? 1'b1 : inputs[6]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[6] && aon_allowed0[6] && ((!aon_values[6])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T33
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION ((aon_enabled[6] && aon_allowed1[6] && aon_values[6]) ? 1'b1 : inputs[6])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[6] && aon_allowed1[6] && aon_values[6])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T16
1	1	0	Covered	T38,T15,T33
1	1	1	Covered	T38,T15,T16

 LINE       143
 EXPRESSION ((aon_enabled[7] && aon_allowed0[7] && ((!aon_values[7]))) ? 1'b0 : ((aon_enabled[7] && aon_allowed1[7] && aon_values[7]) ? 1'b1 : inputs[7]))
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[7] && aon_allowed0[7] && ((!aon_values[7])))
                 -------1------    -------2-------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T15,T16,T33
1	1	0	Covered	T38,T15,T16
1	1	1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION ((aon_enabled[7] && aon_allowed1[7] && aon_values[7]) ? 1'b1 : inputs[7])
                 --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T38,T13,T14
1	Covered	T38,T15,T16

 LINE       143
 SUB-EXPRESSION (aon_enabled[7] && aon_allowed1[7] && aon_values[7])
                 -------1------    -------2-------    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T15,T16
1	0	1	Covered	T38,T15,T33
1	1	0	Covered	T15,T16,T33
1	1	1	Covered	T38,T15,T16

---

Branch Coverage for Module : sysrst_ctrl_pin

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00
TERNARY	143	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_pin.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	143	(((aon_enabled[0] && aon_allowed0[0]) && (!aon_values[0]))) ? 
-2-:	143	(((aon_enabled[0] && aon_allowed1[0]) && aon_values[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T13,T14
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T15,T16

	LineNo.	Expression
-1-:	143	(((aon_enabled[1] && aon_allowed0[1]) && (!aon_values[1]))) ? 
-2-:	143	(((aon_enabled[1] && aon_allowed1[1]) && aon_values[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T13,T14
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T13,T15

	LineNo.	Expression
-1-:	143	(((aon_enabled[2] && aon_allowed0[2]) && (!aon_values[2]))) ? 
-2-:	143	(((aon_enabled[2] && aon_allowed1[2]) && aon_values[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T15,T16
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	143	(((aon_enabled[3] && aon_allowed0[3]) && (!aon_values[3]))) ? 
-2-:	143	(((aon_enabled[3] && aon_allowed1[3]) && aon_values[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T15,T16
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	143	(((aon_enabled[4] && aon_allowed0[4]) && (!aon_values[4]))) ? 
-2-:	143	(((aon_enabled[4] && aon_allowed1[4]) && aon_values[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T16,T33
0	1	Covered	T15,T16,T33
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	143	(((aon_enabled[5] && aon_allowed0[5]) && (!aon_values[5]))) ? 
-2-:	143	(((aon_enabled[5] && aon_allowed1[5]) && aon_values[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T15,T16
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	143	(((aon_enabled[6] && aon_allowed0[6]) && (!aon_values[6]))) ? 
-2-:	143	(((aon_enabled[6] && aon_allowed1[6]) && aon_values[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T15,T16
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T13,T14

	LineNo.	Expression
-1-:	143	(((aon_enabled[7] && aon_allowed0[7]) && (!aon_values[7]))) ? 
-2-:	143	(((aon_enabled[7] && aon_allowed1[7]) && aon_values[7])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T38,T15,T16
0	1	Covered	T38,T15,T16
0	0	Covered	T38,T13,T14