Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_ec_rst_ctl_cdc

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_ulp_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.u_reg.u_combo_intr_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	88.73			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.62	100.00	94.46			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.36	100.00	87.76			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1730859	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	2082	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1730859	0	0
T1	40366	366	0	0
T2	38253	202	0	0
T3	0	4556	0	0
T4	0	817	0	0
T5	0	717	0	0
T6	118820	37759	0	0
T7	199254	0	0	0
T8	0	1399	0	0
T9	0	15933	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	410	0	0
T53	0	10657	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2082	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	10	0	0
T4	0	2	0	0
T5	0	5	0	0
T6	118820	44	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	951813	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1122	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	951813	0	0
T1	40366	324	0	0
T2	38253	212	0	0
T3	0	4475	0	0
T4	0	800	0	0
T5	0	580	0	0
T6	118820	38357	0	0
T7	199254	0	0	0
T8	0	1407	0	0
T9	0	15986	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	415	0	0
T53	0	10535	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1122	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	10	0	0
T4	0	2	0	0
T5	0	4	0	0
T6	118820	45	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	932400	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1130	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	932400	0	0
T1	40366	306	0	0
T2	38253	241	0	0
T3	0	5471	0	0
T4	0	715	0	0
T5	0	2765	0	0
T6	118820	31199	0	0
T7	199254	0	0	0
T8	0	1433	0	0
T9	0	15980	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	457	0	0
T53	0	8974	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1130	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	20	0	0
T6	118820	37	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	939082	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1121	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	939082	0	0
T1	40366	348	0	0
T2	38253	184	0	0
T3	0	6565	0	0
T4	0	789	0	0
T5	0	764	0	0
T6	118820	31066	0	0
T7	199254	0	0	0
T8	0	1449	0	0
T9	0	16005	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	435	0	0
T53	0	8753	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1121	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	15	0	0
T4	0	2	0	0
T5	0	5	0	0
T6	118820	37	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T6,T52,T3
1	-	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	956700	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1127	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	956700	0	0
T1	40366	364	0	0
T2	38253	194	0	0
T3	0	5375	0	0
T4	0	733	0	0
T5	0	1913	0	0
T6	118820	32105	0	0
T7	199254	0	0	0
T8	0	1391	0	0
T9	0	15846	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	429	0	0
T53	0	14414	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1127	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	14	0	0
T6	118820	38	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T1,T2,T52

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T52

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T8
1	-	Covered	T1,T52,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T19,T39,T40
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T52
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T19,T39,T40

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T1,T2,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T1,T2,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	559021	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	593	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	559021	0	0
T1	40366	354	0	0
T2	38253	232	0	0
T3	0	6816	0	0
T4	0	776	0	0
T5	0	2444	0	0
T7	199254	0	0	0
T8	0	1405	0	0
T9	0	15990	0	0
T10	0	28995	0	0
T11	0	1955	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T29	50620	0	0	0
T52	0	399	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	593	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	14	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	15	0	0
T11	0	20	0	0
T12	0	11	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T29	50620	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T1,T2,T52

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T52

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T52,T3
1	-	Covered	T1,T3,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T52
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T13,T14,T15

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T1,T2,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T1,T2,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1057181	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1205	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1057181	0	0
T1	40366	350	0	0
T2	38253	236	0	0
T3	0	7933	0	0
T4	0	683	0	0
T5	0	1453	0	0
T7	199254	0	0	0
T8	0	1419	0	0
T9	0	16130	0	0
T10	0	31265	0	0
T11	0	1872	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T29	50620	0	0	0
T52	0	455	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1205	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	14	0	0
T4	0	2	0	0
T5	0	8	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T11	0	19	0	0
T12	0	12	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T29	50620	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	2562136	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	3271	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2562136	0	0
T1	40366	370	0	0
T2	38253	206	0	0
T3	0	4988	0	0
T4	0	687	0	0
T5	0	1942	0	0
T6	118820	28722	0	0
T7	199254	0	0	0
T8	0	1435	0	0
T9	0	15839	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	471	0	0
T53	0	14410	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	3271	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	11	0	0
T4	0	2	0	0
T5	0	14	0	0
T6	118820	34	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	5381993	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	6791	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5381993	0	0
T1	40366	360	0	0
T2	38253	206	0	0
T3	0	1680	0	0
T4	0	751	0	0
T5	0	1705	0	0
T6	118820	32137	0	0
T7	199254	0	0	0
T8	0	1451	0	0
T9	0	16085	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	461	0	0
T53	0	6794	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6791	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	4	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	38	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	6548672	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	8061	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6548672	0	0
T1	40366	310	0	0
T2	38253	183	0	0
T3	0	6923	0	0
T4	0	690	0	0
T5	0	1671	0	0
T6	118820	39648	0	0
T7	199254	0	0	0
T8	0	1409	0	0
T9	0	15937	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	481	0	0
T53	0	14159	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	8061	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	16	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	47	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	5351878	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	6723	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	5351878	0	0
T1	40366	376	0	0
T2	38253	195	0	0
T3	0	5400	0	0
T4	0	784	0	0
T5	0	1207	0	0
T6	118820	34955	0	0
T7	199254	0	0	0
T8	0	1423	0	0
T9	0	15954	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	422	0	0
T53	0	8950	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6723	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	8	0	0
T6	118820	41	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	938139	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1109	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	938139	0	0
T1	40366	334	0	0
T2	38253	253	0	0
T3	0	6241	0	0
T4	0	825	0	0
T5	0	1700	0	0
T6	118820	39015	0	0
T7	199254	0	0	0
T8	0	1467	0	0
T9	0	15982	0	0
T10	0	31302	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6917	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1109	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	14	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	46	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1696162	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	2075	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1696162	0	0
T1	40366	312	0	0
T2	38253	252	0	0
T3	0	4446	0	0
T4	0	722	0	0
T5	0	1708	0	0
T6	118820	31042	0	0
T7	199254	0	0	0
T8	0	1411	0	0
T9	0	15994	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	401	0	0
T53	0	4936	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2075	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	10	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	37	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	19	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1186201	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1423	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1186201	0	0
T1	40366	338	0	0
T2	38253	213	0	0
T3	0	4000	0	0
T4	0	677	0	0
T5	0	1641	0	0
T6	118820	31119	0	0
T7	199254	0	0	0
T8	0	1397	0	0
T9	0	16041	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	453	0	0
T53	0	20319	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1423	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	9	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	37	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1044672	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1251	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1044672	0	0
T1	40366	314	0	0
T2	38253	196	0	0
T3	0	3112	0	0
T4	0	703	0	0
T5	0	1661	0	0
T6	118820	33886	0	0
T7	199254	0	0	0
T8	0	1403	0	0
T9	0	16006	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	441	0	0
T53	0	12388	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1251	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	7	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	40	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	6722446	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	6901	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6722446	0	0
T1	40366	332	0	0
T2	38253	257	0	0
T3	0	2160	0	0
T4	0	757	0	0
T5	0	1305	0	0
T6	118820	27680	0	0
T7	199254	0	0	0
T8	0	1395	0	0
T9	0	15917	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	405	0	0
T53	0	17032	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6901	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	5	0	0
T4	0	2	0	0
T5	0	9	0	0
T6	118820	33	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	6775157	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7117	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6775157	0	0
T1	40366	318	0	0
T2	38253	259	0	0
T3	0	7299	0	0
T4	0	747	0	0
T5	0	620	0	0
T6	118820	33866	0	0
T7	199254	0	0	0
T8	0	1427	0	0
T9	0	14732	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	463	0	0
T53	0	12261	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7117	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	17	0	0
T4	0	2	0	0
T5	0	4	0	0
T6	118820	39	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	9	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	6696494	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7033	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6696494	0	0
T1	40366	356	0	0
T2	38253	270	0	0
T3	0	3966	0	0
T4	0	735	0	0
T5	0	1165	0	0
T6	118820	38359	0	0
T7	199254	0	0	0
T8	0	1439	0	0
T9	0	16018	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	473	0	0
T53	0	4848	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7033	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	9	0	0
T4	0	2	0	0
T5	0	8	0	0
T6	118820	45	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	6786268	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7098	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	6786268	0	0
T1	40366	346	0	0
T2	38253	221	0	0
T3	0	1343	0	0
T4	0	845	0	0
T5	0	2213	0	0
T6	118820	36752	0	0
T7	199254	0	0	0
T8	0	1443	0	0
T9	0	16162	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	420	0	0
T53	0	14167	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7098	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	3	0	0
T4	0	2	0	0
T5	0	16	0	0
T6	118820	43	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1185625	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1374	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1185625	0	0
T1	40366	297	0	0
T2	38253	266	0	0
T3	0	8264	0	0
T4	0	739	0	0
T5	0	1565	0	0
T6	118820	32086	0	0
T7	199254	0	0	0
T8	0	1415	0	0
T9	0	15926	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	446	0	0
T53	0	14341	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1374	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	19	0	0
T4	0	2	0	0
T5	0	11	0	0
T6	118820	38	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1092452	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1286	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1092452	0	0
T1	40366	308	0	0
T2	38253	230	0	0
T3	0	5335	0	0
T4	0	693	0	0
T5	0	883	0	0
T6	118820	27139	0	0
T7	199254	0	0	0
T8	0	1465	0	0
T9	0	16084	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	431	0	0
T53	0	10914	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1286	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	6	0	0
T6	118820	32	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1119933	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1334	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1119933	0	0
T1	40366	299	0	0
T2	38253	264	0	0
T3	0	6193	0	0
T4	0	806	0	0
T5	0	1208	0	0
T6	118820	35033	0	0
T7	199254	0	0	0
T8	0	1461	0	0
T9	0	16118	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	426	0	0
T53	0	4926	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1334	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	14	0	0
T4	0	2	0	0
T5	0	8	0	0
T6	118820	41	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1110227	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1314	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1110227	0	0
T1	40366	362	0	0
T2	38253	219	0	0
T3	0	8265	0	0
T4	0	789	0	0
T5	0	881	0	0
T6	118820	35134	0	0
T7	199254	0	0	0
T8	0	1417	0	0
T9	0	16026	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	479	0	0
T53	0	6905	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1314	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	19	0	0
T4	0	2	0	0
T5	0	6	0	0
T6	118820	41	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	7349023	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7604	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7349023	0	0
T1	40366	295	0	0
T2	38253	258	0	0
T3	0	5295	0	0
T4	0	680	0	0
T5	0	448	0	0
T6	118820	36668	0	0
T7	199254	0	0	0
T8	0	1457	0	0
T9	0	15997	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	413	0	0
T53	0	8917	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7604	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	3	0	0
T6	118820	43	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	7326576	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7726	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7326576	0	0
T1	40366	326	0	0
T2	38253	228	0	0
T3	0	5012	0	0
T4	0	721	0	0
T5	0	1185	0	0
T6	118820	38402	0	0
T7	199254	0	0	0
T8	0	1455	0	0
T9	0	15986	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	439	0	0
T53	0	8597	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7726	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	11	0	0
T4	0	2	0	0
T5	0	8	0	0
T6	118820	45	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	7262479	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7632	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7262479	0	0
T1	40366	304	0	0
T2	38253	255	0	0
T3	0	6071	0	0
T4	0	781	0	0
T5	0	1601	0	0
T6	118820	26958	0	0
T7	199254	0	0	0
T8	0	1431	0	0
T9	0	15984	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	449	0	0
T53	0	10901	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7632	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	14	0	0
T4	0	2	0	0
T5	0	11	0	0
T6	118820	32	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	7297532	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	7692	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7297532	0	0
T1	40366	320	0	0
T2	38253	239	0	0
T3	0	5368	0	0
T4	0	740	0	0
T5	0	1421	0	0
T6	118820	38227	0	0
T7	199254	0	0	0
T8	0	1437	0	0
T9	0	16014	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	459	0	0
T53	0	17218	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	7692	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	10	0	0
T6	118820	45	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1705941	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	2014	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1705941	0	0
T1	40366	316	0	0
T2	38253	218	0	0
T3	0	5008	0	0
T4	0	691	0	0
T5	0	1661	0	0
T6	118820	37760	0	0
T7	199254	0	0	0
T8	0	1425	0	0
T9	0	16080	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	437	0	0
T53	0	6940	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	2014	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	11	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	44	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T2,T3
1	1	Covered	T6,T2,T52

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T2,T52
1	1	Covered	T6,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T2,T52
0	0	1	Covered	T6,T2,T3
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T2,T52
0	0	1	Covered	T6,T2,T3
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1666818	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1933	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1666818	0	0
T1	40366	0	0	0
T2	38253	223	0	0
T3	0	4507	0	0
T4	0	680	0	0
T5	0	1319	0	0
T6	118820	38465	0	0
T7	199254	0	0	0
T8	0	1393	0	0
T9	0	16125	0	0
T10	0	31628	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	403	0	0
T53	0	15786	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1933	0	0
T1	40366	0	0	0
T2	38253	1	0	0
T3	0	10	0	0
T4	0	2	0	0
T5	0	9	0	0
T6	118820	45	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T11	0	19	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1615490	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1918	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1615490	0	0
T1	40366	352	0	0
T2	38253	201	0	0
T3	0	3083	0	0
T4	0	674	0	0
T5	0	725	0	0
T6	118820	27737	0	0
T7	199254	0	0	0
T8	0	1453	0	0
T9	0	15932	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	408	0	0
T53	0	14131	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1918	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	7	0	0
T4	0	2	0	0
T5	0	5	0	0
T6	118820	33	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1630477	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1930	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1630477	0	0
T1	40366	372	0	0
T2	38253	266	0	0
T3	0	5295	0	0
T4	0	735	0	0
T5	0	1852	0	0
T6	118820	28695	0	0
T7	199254	0	0	0
T8	0	1459	0	0
T9	0	16118	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	433	0	0
T53	0	14242	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1930	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	12	0	0
T4	0	2	0	0
T5	0	13	0	0
T6	118820	34	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	8	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1667550	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1995	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1667550	0	0
T1	40366	340	0	0
T2	38253	244	0	0
T3	0	7041	0	0
T4	0	737	0	0
T5	0	2092	0	0
T6	118820	28754	0	0
T7	199254	0	0	0
T8	0	1445	0	0
T9	0	16019	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	467	0	0
T53	0	10482	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1995	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	16	0	0
T4	0	2	0	0
T5	0	15	0	0
T6	118820	34	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1612986	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1935	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1612986	0	0
T1	40366	342	0	0
T2	38253	239	0	0
T3	0	3172	0	0
T4	0	815	0	0
T5	0	2443	0	0
T6	118820	30214	0	0
T7	199254	0	0	0
T8	0	1413	0	0
T9	0	14665	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	487	0	0
T53	0	10905	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1935	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	7	0	0
T4	0	2	0	0
T5	0	18	0	0
T6	118820	36	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	9	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1607011	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1910	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1607011	0	0
T1	40366	358	0	0
T2	38253	186	0	0
T3	0	2635	0	0
T4	0	787	0	0
T5	0	1700	0	0
T6	118820	36568	0	0
T7	199254	0	0	0
T8	0	1469	0	0
T9	0	14584	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	424	0	0
T53	0	12234	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1910	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	6	0	0
T4	0	2	0	0
T5	0	12	0	0
T6	118820	43	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	9	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T6,T1,T2
0	0	1	Covered	T6,T1,T2
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	1590649	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1944	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1590649	0	0
T1	40366	322	0	0
T2	38253	243	0	0
T3	0	4037	0	0
T4	0	721	0	0
T5	0	2438	0	0
T6	118820	34117	0	0
T7	199254	0	0	0
T8	0	1441	0	0
T9	0	16022	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T52	0	465	0	0
T53	0	12373	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1944	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	9	0	0
T4	0	2	0	0
T5	0	18	0	0
T6	118820	40	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T53	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Unreachable
1	0	Covered	T1,T2,T52

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T52

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T7
0	1	Covered	T13,T17,T18
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T52
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T7
1	0	Not Covered
1	1	Covered	T13,T17,T18

---

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T1,T2,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T7

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T6,T1,T7
0	1	-	Covered	T1,T2,T52
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T6,T1,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1318649788	994507	0	0
DstReqKnown_A	10259703	9401398	0	0
SrcAckBusyChk_A	1318649788	1143	0	0
SrcBusyKnown_A	1318649788	1316820686	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	994507	0	0
T1	40366	328	0	0
T2	38253	214	0	0
T3	0	6317	0	0
T4	0	844	0	0
T5	0	666	0	0
T7	199254	0	0	0
T8	0	1389	0	0
T9	0	16206	0	0
T10	0	30870	0	0
T11	0	1940	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T29	50620	0	0	0
T52	0	476	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10259703	9401398	0	0
T1	424	17	0	0
T2	425	21	0	0
T6	4849	4449	0	0
T7	402	2	0	0
T23	403	3	0	0
T24	405	5	0	0
T25	408	8	0	0
T26	405	5	0	0
T27	450	50	0	0
T28	408	8	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1143	0	0
T1	40366	1	0	0
T2	38253	1	0	0
T3	0	11	0	0
T4	0	2	0	0
T5	0	4	0	0
T7	199254	0	0	0
T8	0	1	0	0
T9	0	10	0	0
T10	0	20	0	0
T11	0	20	0	0
T12	0	17	0	0
T23	197742	0	0	0
T24	194472	0	0	0
T25	44929	0	0	0
T26	91060	0	0	0
T27	40503	0	0	0
T28	204177	0	0	0
T29	50620	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1318649788	1316820686	0	0
T1	40366	39637	0	0
T2	38253	37823	0	0
T6	118820	118812	0	0
T7	199254	199180	0	0
T23	197742	197644	0	0
T24	194472	194403	0	0
T25	44929	44879	0	0
T26	91060	90995	0	0
T27	40503	40407	0	0
T28	204177	204123	0	0