Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_auto_blk_key_output_vseq::sysrst_ctrl_auto_blk_out_ctl_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 89.58 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_auto_blk_key_output_vseq.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_auto_blk_out_ctl_cg_(2) 70.83 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(3) 87.50 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg 100.00 1 100 1 64 64
sysrst_ctrl_auto_blk_out_ctl_cg_(1) 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(2)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
70.83 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 1 11 91.67
Crosses 12 6 6 50.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 1 1 50.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(2)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 2 2 50.00 100 1 1 0
cross_key1_out_sel_value 4 2 2 50.00 100 1 1 0
cross_key2_out_sel_value 4 2 2 50.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(3)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
87.50 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 3 9 75.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(3)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 1 3 75.00 100 1 1 0
cross_key1_out_sel_value 4 1 3 75.00 100 1 1 0
cross_key2_out_sel_value 4 1 3 75.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0



Group Instance : sysrst_ctrl_auto_blk_out_ctl_cg_(1)
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 12 0 12 100.00


Variables for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_key0_out_sel 2 0 2 100.00 100 1 1 2
cp_key0_out_value 2 0 2 100.00 100 1 1 2
cp_key1_out_sel 2 0 2 100.00 100 1 1 2
cp_key1_out_value 2 0 2 100.00 100 1 1 2
cp_key2_out_sel 2 0 2 100.00 100 1 1 2
cp_key2_out_value 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_auto_blk_out_ctl_cg_(1)
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cross_key0_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key1_out_sel_value 4 0 4 100.00 100 1 1 0
cross_key2_out_sel_value 4 0 4 100.00 100 1 1 0


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T52 1
auto[1] 2 1 T52 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T52 1
auto[1] 2 1 T52 2



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 2 1 T52 2
auto[1] 1 1 T52 1



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_key1_out_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 3 1 T52 3



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T52 1
auto[1] 2 1 T52 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNT
auto[0] 1 1 T52 1
auto[1] 2 1 T52 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T52 1
auto[1] auto[1] 2 1 T52 2



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key1_out_sel_value

Element holes
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] * -- -- 2


Covered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 2 1 T52 2
auto[0] auto[1] 1 1 T52 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNT
auto[0] auto[0] 1 1 T52 1
auto[1] auto[1] 2 1 T52 2


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 2 1 T52 1 T350 1
auto[1] 4 1 T52 2 T350 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 3 1 T52 1 T350 2
auto[1] 3 1 T52 2 T350 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 2 1 T52 2 - -
auto[1] 4 1 T52 1 T350 3



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 5 1 T52 3 T350 2
auto[1] 1 1 T350 1 - -



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 5 1 T52 3 T350 2
auto[1] 1 1 T350 1 - -



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] 2 1 T52 2 - -
auto[1] 4 1 T52 1 T350 3



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key0_out_sel_value

Uncovered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 2 1 T52 1 T350 1
auto[0] auto[1] 1 1 T350 1 - -
auto[1] auto[1] 3 1 T52 2 T350 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key1_out_sel_value

Uncovered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] 0 1 1


Covered bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 2 1 T52 2 - -
auto[0] auto[1] 3 1 T52 1 T350 2
auto[1] auto[1] 1 1 T350 1 - -



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 1 3 75.00 1


Automatically Generated Cross Bins for cross_key2_out_sel_value

Uncovered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] 0 1 1


Covered bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNT
auto[0] auto[0] 2 1 T52 2 - -
auto[1] auto[0] 3 1 T52 1 T350 2
auto[1] auto[1] 1 1 T350 1 - -


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 125 1 T41 1 T14 2 T32 1
auto[1] 119 1 T41 2 T14 1 T32 2



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 121 1 T41 3 T14 3 T32 2
auto[1] 123 1 T32 1 T17 1 T65 3



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 103 1 T41 1 T14 1 T17 3
auto[1] 141 1 T41 2 T14 2 T32 3



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 133 1 T14 2 T32 2 T65 2
auto[1] 111 1 T41 3 T14 1 T32 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 125 1 T41 2 T14 2 T32 1
auto[1] 119 1 T41 1 T14 1 T32 2



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 111 1 T41 2 T14 2 T32 2
auto[1] 133 1 T41 1 T14 1 T32 1



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 62 1 T41 1 T14 2 T32 1
auto[0] auto[1] 59 1 T41 2 T14 1 T32 1
auto[1] auto[0] 63 1 T65 1 T80 2 T53 3
auto[1] auto[1] 60 1 T32 1 T17 1 T65 2



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 55 1 T14 1 T65 2 T21 1
auto[0] auto[1] 78 1 T14 1 T32 2 T21 1
auto[1] auto[0] 48 1 T41 1 T17 3 T21 1
auto[1] auto[1] 63 1 T41 2 T14 1 T32 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 60 1 T41 1 T14 1 T17 1
auto[0] auto[1] 51 1 T41 1 T14 1 T32 2
auto[1] auto[0] 65 1 T41 1 T14 1 T32 1
auto[1] auto[1] 68 1 T17 1 T65 1 T21 1


Summary for Variable cp_key0_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 16 1 T43 2 T52 2 T95 2
auto[1] 18 1 T43 1 T52 1 T84 1



Summary for Variable cp_key0_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12 1 T52 1 T84 1 T95 1
auto[1] 22 1 T43 3 T52 2 T110 1



Summary for Variable cp_key1_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17 1 T52 2 T95 1 T72 1
auto[1] 17 1 T43 3 T52 1 T84 1



Summary for Variable cp_key1_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 19 1 T43 2 T52 2 T110 1
auto[1] 15 1 T43 1 T52 1 T84 1



Summary for Variable cp_key2_out_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_sel

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13 1 T43 2 T52 1 T95 1
auto[1] 21 1 T43 1 T52 2 T84 1



Summary for Variable cp_key2_out_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 17 1 T43 1 T52 2 T84 1
auto[1] 17 1 T43 2 T52 1 T95 2



Summary for Cross cross_key0_out_sel_value

Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key0_out_sel_value

Bins
cp_key0_out_valuecp_key0_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 3 1 T52 1 T72 1 T351 1
auto[0] auto[1] 9 1 T84 1 T95 1 T72 1
auto[1] auto[0] 13 1 T43 2 T52 1 T95 2
auto[1] auto[1] 9 1 T43 1 T52 1 T110 1



Summary for Cross cross_key1_out_sel_value

Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key1_out_sel_value

Bins
cp_key1_out_valuecp_key1_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 9 1 T52 1 T95 1 T72 1
auto[0] auto[1] 10 1 T43 2 T52 1 T110 1
auto[1] auto[0] 8 1 T52 1 T97 2 T212 1
auto[1] auto[1] 7 1 T43 1 T84 1 T95 1



Summary for Cross cross_key2_out_sel_value

Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cross_key2_out_sel_value

Bins
cp_key2_out_valuecp_key2_out_selCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 7 1 T43 1 T52 1 T95 1
auto[0] auto[1] 10 1 T52 1 T84 1 T110 1
auto[1] auto[0] 6 1 T43 1 T72 1 T97 1
auto[1] auto[1] 11 1 T43 1 T52 1 T95 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%