Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1913

1

T13

12

T14

1

T15

3

auto[1]

571

1

T14

2

T15

5

T16

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1917

1

T13

3

T14

1

T15

3

auto[1]

567

1

T13

9

T14

2

T15

5

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1845

1

T13

9

T14

1

T15

5

auto[1]

639

1

T13

3

T14

2

T15

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1890

1

T13

3

T14

3

T15

5

auto[1]

594

1

T13

9

T15

3

T16

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2312

1

T13

6

T14

3

T15

8

auto[1]

172

1

T13

6

T35

1

T48

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2288

1

T13

12

T14

3

T15

8

auto[1]

196

1

T16

5

T20

5

T81

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2262

1

T13

9

T14

3

T15

8

auto[1]

222

1

T13

3

T16

2

T78

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2280

1

T13

9

T14

3

T15

8

auto[1]

204

1

T13

3

T16

2

T20

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2247

1

T13

3

T14

3

T15

8

auto[1]

237

1

T13

9

T20

2

T48

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1829

1

T13

9

T15

4

T16

12

auto[1]

655

1

T13

3

T14

3

T15

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	880	1			T14	2		T15	4		T17	23
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	28	1			T13	3		T35	1		T106	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	79	1			T13	3		T100	1		T107	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	17	1			T108	4		T325	3		T326	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	80	1			T48	14		T82	3		T51	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	13	1			T48	4		T313	3		T327	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	24	1			T48	9		T224	6		T186	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	4	1			T13	3		T308	1		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	70	1			T78	1		T106	14		T107	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	8	1			T328	1		T329	7		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	18	1			T13	3		T316	2		T325	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	22	1			T307	20		T330	2		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	18	1			T67	2		T313	3		T331	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T331	2		T332	2		T333	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	45	1			T16	1		T219	2		T325	6
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	25	1			T81	6		T334	2		T325	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	22	1			T20	2		T164	1		T328	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T333	4		T335	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	18	1			T20	3		T219	4		T310	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T331	3		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T51	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	36	1			T307	22		T308	4		T320	7
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	4	1			T336	1		T337	3		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T329	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	3	1			T16	1		T108	2		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T336	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

86

1

T16

1

T51

2

T242

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

114

1

T17

7

T48

4

T106

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

64

1

T14

1

T62

5

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

132

1

T13

3

T106

7

T242

9

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

50

1

T16

1

T109

1

T219

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

72

1

T17

5

T44

6

T111

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T338

1

-

-

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

119

1

T17

10

T81

6

T52

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

50

1

T20

3

T51

2

T44

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

60

1

T334

2

T94

8

T327

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

43

1

T22

2

T82

3

T44

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T100

1

T107

4

T116

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T20

2

T43

1

T339

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T15

3

T22

1

T111

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T70

1

T223

1

T302

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

98

1

T13

3

T48

9

T43

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T78

1

T67

3

T325

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T21

2

T109

2

T60

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

57

1

T15

1

T17

1

T91

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T13

3

T35

1

T44

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T301

6

T321

9

T340

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

17

1

T92

3

T222

5

T66

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T22

1

T106

7

T241

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

59

1

T221

7

T222

7

T243

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

36

1

T48

14

T91

3

T302

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

15

1

T14

1

T339

1

T310

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T22

2

T341

2

T228

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T221

5

T92

2

T325

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T61

1

T244

1

T342

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T13

3

T62

1

T70

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T301

1

T306

1

T304

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded