Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	165204	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

129506

1

T7

7

T8

49

T1

130

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	150439	1			T7	11		T8	44		T1	141
values[0x0]	71752	1			T7	2		T8	21		T1	52
values[0x1]	72519	1			T7	8		T8	21		T1	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	134525	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160185

1

T7

10

T8

56

T1

163

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1133	1			T27	128		T4	9		T6	6
valid_sources[0x01]	2081	1			T1	1		T27	128		T4	12
valid_sources[0x02]	1332	1			T8	14		T1	1		T27	130
valid_sources[0x03]	1003	1			T2	30		T4	2		T6	16
valid_sources[0x04]	1849	1			T6	15		T9	8		T11	5
valid_sources[0x05]	895	1			T4	8		T6	4		T10	1
valid_sources[0x06]	1333	1			T1	3		T27	384		T6	6
valid_sources[0x07]	1191	1			T9	1		T11	4		T40	6
valid_sources[0x08]	1732	1			T4	1		T9	3		T11	3
valid_sources[0x09]	1349	1			T3	2		T40	12		T254	1
valid_sources[0x0a]	1003	1			T1	2		T4	1		T6	51
valid_sources[0x0b]	1026	1			T4	5		T6	12		T9	6
valid_sources[0x0c]	1231	1			T27	128		T4	6		T39	1
valid_sources[0x0d]	876	1			T1	1		T2	10		T4	4
valid_sources[0x0e]	956	1			T4	2		T6	23		T11	1
valid_sources[0x0f]	1227	1			T1	1		T27	384		T6	23
valid_sources[0x10]	1035	1			T4	16		T39	4		T6	34
valid_sources[0x11]	888	1			T1	4		T4	5		T6	15
valid_sources[0x12]	1275	1			T7	1		T2	5		T27	256
valid_sources[0x13]	1279	1			T1	1		T4	5		T9	4
valid_sources[0x14]	1535	1			T8	8		T2	7		T6	17
valid_sources[0x15]	873	1			T2	11		T3	3		T4	12
valid_sources[0x16]	1134	1			T29	2		T4	8		T6	11
valid_sources[0x17]	877	1			T2	3		T4	1		T6	20
valid_sources[0x18]	889	1			T4	8		T6	1		T9	1
valid_sources[0x19]	886	1			T6	3		T9	5		T49	21
valid_sources[0x1a]	997	1			T4	2		T6	8		T40	9
valid_sources[0x1b]	1040	1			T27	128		T6	10		T9	2
valid_sources[0x1c]	805	1			T1	2		T3	2		T11	2
valid_sources[0x1d]	1041	1			T1	1		T4	2		T6	20
valid_sources[0x1e]	973	1			T29	12		T6	56		T9	1
valid_sources[0x1f]	1643	1			T1	1		T4	3		T6	11
valid_sources[0x20]	1042	1			T6	8		T9	1		T11	3
valid_sources[0x21]	2211	1			T1	2		T4	10		T39	1
valid_sources[0x22]	1273	1			T7	3		T1	1		T2	9
valid_sources[0x23]	884	1			T4	2		T6	2		T9	4
valid_sources[0x24]	878	1			T39	1		T9	1		T11	3
valid_sources[0x25]	1161	1			T6	14		T9	6		T11	4
valid_sources[0x26]	1528	1			T2	20		T27	128		T4	14
valid_sources[0x27]	1176	1			T8	20		T6	17		T9	1
valid_sources[0x28]	1019	1			T4	3		T6	13		T9	3
valid_sources[0x29]	1195	1			T4	3		T9	5		T11	4
valid_sources[0x2a]	983	1			T4	2		T6	3		T9	13
valid_sources[0x2b]	1926	1			T1	1		T4	15		T6	18
valid_sources[0x2c]	1042	1			T27	128		T4	2		T6	9
valid_sources[0x2d]	1109	1			T3	1		T27	128		T6	41
valid_sources[0x2e]	1264	1			T1	1		T2	6		T5	1
valid_sources[0x2f]	1029	1			T1	3		T24	45		T6	18
valid_sources[0x30]	2386	1			T4	17		T39	3		T6	1
valid_sources[0x31]	905	1			T1	1		T29	1		T4	3
valid_sources[0x32]	908	1			T1	1		T27	128		T4	1
valid_sources[0x33]	1589	1			T6	23		T9	2		T11	2
valid_sources[0x34]	1020	1			T1	2		T27	128		T6	16
valid_sources[0x35]	1062	1			T1	1		T4	6		T5	3
valid_sources[0x36]	1055	1			T4	3		T5	7		T9	3
valid_sources[0x37]	1004	1			T1	6		T27	128		T4	10
valid_sources[0x38]	944	1			T1	1		T4	2		T39	1
valid_sources[0x39]	1180	1			T1	1		T2	12		T6	5
valid_sources[0x3a]	1776	1			T27	256		T4	14		T9	1
valid_sources[0x3b]	1425	1			T1	2		T4	3		T6	14
valid_sources[0x3c]	1945	1			T4	2		T9	2		T11	7
valid_sources[0x3d]	1198	1			T1	3		T2	14		T5	9
valid_sources[0x3e]	1290	1			T1	2		T29	1		T4	4
valid_sources[0x3f]	1009	1			T2	17		T4	31		T6	53
valid_sources[0x40]	1114	1			T27	128		T4	2		T9	6
valid_sources[0x41]	1172	1			T4	1		T6	29		T250	7
valid_sources[0x42]	1068	1			T1	2		T9	9		T250	4
valid_sources[0x43]	898	1			T5	2		T6	2		T9	2
valid_sources[0x44]	936	1			T4	6		T9	3		T10	14
valid_sources[0x45]	961	1			T1	2		T2	17		T4	2
valid_sources[0x46]	1185	1			T7	3		T27	128		T4	2
valid_sources[0x47]	986	1			T1	2		T6	20		T10	14
valid_sources[0x48]	903	1			T7	1		T1	1		T4	2
valid_sources[0x49]	1017	1			T1	1		T2	4		T29	1
valid_sources[0x4a]	1940	1			T1	1		T27	128		T4	3
valid_sources[0x4b]	1081	1			T1	2		T6	1		T9	5
valid_sources[0x4c]	828	1			T2	5		T29	2		T9	13
valid_sources[0x4d]	820	1			T4	1		T9	5		T11	2
valid_sources[0x4e]	1009	1			T7	1		T4	3		T39	5
valid_sources[0x4f]	1021	1			T8	34		T1	1		T27	128
valid_sources[0x50]	939	1			T1	10		T4	11		T9	10
valid_sources[0x51]	1032	1			T1	3		T4	10		T6	75
valid_sources[0x52]	1098	1			T27	128		T4	2		T6	14
valid_sources[0x53]	1227	1			T1	5		T27	128		T4	20
valid_sources[0x54]	887	1			T1	2		T29	5		T4	1
valid_sources[0x55]	1105	1			T1	2		T2	24		T27	128
valid_sources[0x56]	1004	1			T1	5		T4	10		T9	4
valid_sources[0x57]	979	1			T1	2		T3	1		T4	4
valid_sources[0x58]	1374	1			T4	3		T6	17		T49	3
valid_sources[0x59]	978	1			T4	20		T9	4		T250	7
valid_sources[0x5a]	1189	1			T1	5		T2	9		T9	3
valid_sources[0x5b]	1140	1			T1	3		T23	13		T27	128
valid_sources[0x5c]	979	1			T6	20		T9	1		T281	23
valid_sources[0x5d]	1383	1			T1	1		T4	5		T39	2
valid_sources[0x5e]	1083	1			T27	128		T4	6		T5	80
valid_sources[0x5f]	1201	1			T1	1		T4	15		T6	5
valid_sources[0x60]	1143	1			T1	1		T27	256		T6	35
valid_sources[0x61]	1030	1			T7	1		T27	128		T4	3
valid_sources[0x62]	844	1			T6	2		T9	7		T11	3
valid_sources[0x63]	1070	1			T27	128		T29	6		T9	3
valid_sources[0x64]	1269	1			T27	128		T6	4		T9	4
valid_sources[0x65]	762	1			T4	9		T9	2		T250	9
valid_sources[0x66]	899	1			T29	1		T4	10		T10	18
valid_sources[0x67]	870	1			T1	2		T4	1		T6	11
valid_sources[0x68]	1168	1			T4	8		T6	2		T9	3
valid_sources[0x69]	1158	1			T4	2		T9	6		T11	6
valid_sources[0x6a]	991	1			T1	2		T2	3		T4	2
valid_sources[0x6b]	1013	1			T4	1		T6	5		T9	7
valid_sources[0x6c]	1113	1			T27	128		T9	3		T250	3
valid_sources[0x6d]	1800	1			T4	6		T9	2		T250	2
valid_sources[0x6e]	965	1			T7	1		T1	1		T4	6
valid_sources[0x6f]	1135	1			T27	128		T6	16		T9	2
valid_sources[0x70]	1185	1			T1	4		T27	128		T9	4
valid_sources[0x71]	1047	1			T27	128		T4	14		T6	29
valid_sources[0x72]	949	1			T1	1		T6	10		T9	2
valid_sources[0x73]	1090	1			T2	9		T250	12		T11	5
valid_sources[0x74]	1245	1			T6	4		T11	7		T285	4
valid_sources[0x75]	955	1			T29	7		T4	3		T6	47
valid_sources[0x76]	1212	1			T2	20		T6	16		T9	2
valid_sources[0x77]	1139	1			T4	15		T6	9		T9	8
valid_sources[0x78]	981	1			T4	6		T6	49		T11	2
valid_sources[0x79]	1159	1			T1	1		T3	10		T4	2
valid_sources[0x7a]	1212	1			T7	1		T4	7		T6	39
valid_sources[0x7b]	1848	1			T4	7		T6	3		T9	4
valid_sources[0x7c]	1106	1			T4	14		T6	36		T9	3
valid_sources[0x7d]	1108	1			T1	1		T29	4		T4	1
valid_sources[0x7e]	1021	1			T1	6		T4	3		T9	1
valid_sources[0x7f]	871	1			T4	1		T6	18		T9	4
valid_sources[0x80]	2227	1			T1	1		T3	2		T27	128

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

69470

1

T7

4

T8

27

T1

68

values[0x0]

all_enables

biggest_size

35118

1

T7

1

T8

11

T1

36

values[0x1]

all_enables

biggest_size

24918

1

T7

2

T8

11

T1

26