Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T19,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T19,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T21
1	0	Covered	T41,T13,T30
1	1	Covered	T14,T19,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T43
0	1	Covered	T14,T43,T45
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T21,T43
1	-	Covered	T14,T43,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T19,T21
0	1	Covered	T14,T19,T21
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T21,T43
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T19,T21
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T21,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T47,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T19,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T21,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T43,T45
StableSt	-	-	-	-	-	-	0	Covered	T14,T21,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	76	0	0
CntIncr_A	8198376	124903	0	0
CntNoWrap_A	8198376	7499379	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	42617	0	0
DetectedPulseOut_A	8198376	36	0	0
DisabledIdleSt_A	8198376	7122623	0	0
DisabledNoDetection_A	8198376	7124981	0	0
EnterDebounceSt_A	8198376	40	0	0
EnterDetectSt_A	8198376	36	0	0
EnterStableSt_A	8198376	36	0	0
PulseIsPulse_A	8198376	36	0	0
StayInStableSt	8198376	42561	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	76	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	4	0	0
T47	0	3	0	0
T52	0	2	0	0
T53	0	2	0	0
T57	503	0	0	0
T70	0	2	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	124903	0	0
T14	19815	11	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	14	0	0
T21	0	25	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	68	0	0
T45	0	182	0	0
T47	0	69962	0	0
T52	0	63	0	0
T53	0	60	0	0
T57	503	0	0	0
T70	0	58	0	0
T133	0	59	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499379	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	42617	0	0
T14	19815	137	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	46	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	42	0	0
T45	0	80	0	0
T47	0	40	0	0
T52	0	48	0	0
T53	0	54	0	0
T57	503	0	0	0
T70	0	43	0	0
T133	0	37	0	0
T144	0	40162	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T133	0	1	0	0
T144	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7122623	0	0
T13	11076	10667	0	0
T14	19815	6802	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7124981	0	0
T13	11076	10669	0	0
T14	19815	6836	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	40	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T133	0	1	0	0
T144	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T133	0	1	0	0
T144	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T133	0	1	0	0
T144	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	42561	0	0
T14	19815	136	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	44	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	41	0	0
T45	0	78	0	0
T47	0	39	0	0
T52	0	47	0	0
T53	0	52	0	0
T57	503	0	0	0
T70	0	42	0	0
T133	0	35	0	0
T144	0	40159	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	15	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T21,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T21,T46
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T21,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T46
0	1	Covered	T47,T133
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T46
0	1	Covered	T14,T21,T46
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T21,T46
1	-	Covered	T14,T21,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T21,T46
0	1	Covered	T14,T21,T46
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T21,T46
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T21,T46
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T21,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T148,T149,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T21,T46
DetectSt	-	-	-	-	1	-	-	Covered	T47,T133
DetectSt	-	-	-	-	0	1	-	Covered	T14,T21,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T21,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T21,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	128	0	0
CntIncr_A	8198376	108047	0	0
CntNoWrap_A	8198376	7499327	0	0
DetectStDropOut_A	8198376	2	0	0
DetectedOut_A	8198376	9241	0	0
DetectedPulseOut_A	8198376	60	0	0
DisabledIdleSt_A	8198376	7307600	0	0
DisabledNoDetection_A	8198376	7309969	0	0
EnterDebounceSt_A	8198376	66	0	0
EnterDetectSt_A	8198376	62	0	0
EnterStableSt_A	8198376	60	0	0
PulseIsPulse_A	8198376	60	0	0
StayInStableSt	8198376	9156	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	3091	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	128	0	0
T14	19815	4	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	4	0	0
T46	0	2	0	0
T47	0	6	0	0
T52	0	4	0	0
T56	0	2	0	0
T57	503	0	0	0
T133	0	4	0	0
T135	0	4	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	108047	0	0
T14	19815	22	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	25	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	136	0	0
T46	0	81	0	0
T47	0	104943	0	0
T52	0	126	0	0
T56	0	18	0	0
T57	503	0	0	0
T133	0	72	0	0
T135	0	38	0	0
T140	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499327	0	0
T13	11076	10667	0	0
T14	19815	7024	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2	0	0
T47	176197	1	0	0
T133	6332	1	0	0
T151	422	0	0	0
T152	448	0	0	0
T153	39539	0	0	0
T154	409	0	0	0
T155	403	0	0	0
T156	836	0	0	0
T157	755	0	0	0
T158	494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	9241	0	0
T14	19815	48	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	80	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	86	0	0
T46	0	41	0	0
T47	0	4049	0	0
T52	0	297	0	0
T56	0	72	0	0
T57	503	0	0	0
T133	0	96	0	0
T135	0	150	0	0
T140	0	64	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	60	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T52	0	2	0	0
T56	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7307600	0	0
T13	11076	10667	0	0
T14	19815	6719	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7309969	0	0
T13	11076	10669	0	0
T14	19815	6752	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	66	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T52	0	2	0	0
T56	0	1	0	0
T57	503	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	62	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	3	0	0
T52	0	2	0	0
T56	0	1	0	0
T57	503	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	60	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T52	0	2	0	0
T56	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	60	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T52	0	2	0	0
T56	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	9156	0	0
T14	19815	45	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	79	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	83	0	0
T46	0	40	0	0
T47	0	4046	0	0
T52	0	294	0	0
T56	0	71	0	0
T57	503	0	0	0
T133	0	94	0	0
T135	0	147	0	0
T140	0	62	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	3091	0	0
T13	11076	0	0	0
T14	19815	93	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	0	9	0	0
T30	405	0	0	0
T31	502	6	0	0
T32	665	0	0	0
T33	497	5	0	0
T34	422	2	0	0
T41	2031	4	0	0
T57	0	4	0	0
T59	0	5	0	0
T85	0	3	0	0
T86	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	34	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	503	0	0	0
T95	0	2	0	0
T110	0	1	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T17,T19,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T17,T19,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T17,T19,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T19
1	0	Covered	T13,T14,T15
1	1	Covered	T17,T19,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T21
0	1	Covered	T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T21
0	1	Covered	T21,T46,T43
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T19,T21
1	-	Covered	T21,T46,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T19,T21
0	1	Covered	T17,T19,T21
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T21
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T19,T21
IdleSt	0	-	-	-	-	-	-	Covered	T13,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T19,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T109,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T19,T21
DetectSt	-	-	-	-	1	-	-	Covered	T72
DetectSt	-	-	-	-	0	1	-	Covered	T17,T19,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T21,T46,T43
StableSt	-	-	-	-	-	-	0	Covered	T17,T19,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	151	0	0
CntIncr_A	8198376	74474	0	0
CntNoWrap_A	8198376	7499304	0	0
DetectStDropOut_A	8198376	1	0	0
DetectedOut_A	8198376	65996	0	0
DetectedPulseOut_A	8198376	73	0	0
DisabledIdleSt_A	8198376	7302060	0	0
DisabledNoDetection_A	8198376	7304418	0	0
EnterDebounceSt_A	8198376	77	0	0
EnterDetectSt_A	8198376	74	0	0
EnterStableSt_A	8198376	73	0	0
PulseIsPulse_A	8198376	73	0	0
StayInStableSt	8198376	65892	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	151	0	0
T17	36108	2	0	0
T18	830	0	0	0
T19	555	2	0	0
T21	21341	4	0	0
T43	0	4	0	0
T46	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	2	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T109	0	1	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	74474	0	0
T17	36108	95	0	0
T18	830	0	0	0
T19	555	14	0	0
T21	21341	50	0	0
T43	0	161	0	0
T46	0	81	0	0
T52	0	63	0	0
T53	0	60	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	67	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T109	0	92	0	0
T133	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499304	0	0
T13	11076	10667	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1	0	0
T72	30158	1	0	0
T137	551	0	0	0
T138	993	0	0	0
T160	524	0	0	0
T161	5416	0	0	0
T162	496	0	0	0
T163	1235	0	0	0
T164	9684	0	0	0
T165	504	0	0	0
T166	448	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	65996	0	0
T17	36108	452	0	0
T18	830	0	0	0
T19	555	132	0	0
T21	21341	84	0	0
T43	0	314	0	0
T46	0	66	0	0
T52	0	473	0	0
T53	0	44	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	38	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T133	0	41	0	0
T167	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	73	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	1	0	0
T21	21341	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	1	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T133	0	1	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7302060	0	0
T13	11076	10667	0	0
T14	19815	6945	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7304418	0	0
T13	11076	10669	0	0
T14	19815	6979	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	77	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	1	0	0
T21	21341	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	1	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T109	0	1	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	74	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	1	0	0
T21	21341	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	1	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T133	0	1	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	73	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	1	0	0
T21	21341	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	1	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T133	0	1	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	73	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	1	0	0
T21	21341	2	0	0
T43	0	2	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	1	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T133	0	1	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	65892	0	0
T17	36108	450	0	0
T18	830	0	0	0
T19	555	130	0	0
T21	21341	81	0	0
T43	0	311	0	0
T46	0	65	0	0
T52	0	471	0	0
T53	0	43	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T84	0	36	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T133	0	39	0	0
T167	0	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	41	0	0
T21	21341	1	0	0
T22	10161	0	0	0
T43	0	1	0	0
T46	0	1	0	0
T48	32402	0	0	0
T53	0	1	0	0
T70	0	1	0	0
T80	763	0	0	0
T111	0	1	0	0
T134	0	1	0	0
T135	0	2	0	0
T141	0	1	0	0
T168	0	2	0	0
T169	505	0	0	0
T170	675	0	0	0
T171	445	0	0	0
T172	516	0	0	0
T173	410	0	0	0
T174	497	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T46,T43,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T46,T43,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T46,T43,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T46,T43
1	0	Covered	T41,T13,T14
1	1	Covered	T46,T43,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T46,T43,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T46,T43,T47
0	1	Covered	T134,T175,T144
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T46,T43,T47
1	-	Covered	T134,T175,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T46,T43,T47
0	1	Covered	T46,T43,T47
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T43,T47
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T46,T43,T47
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T46,T43,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T138
DebounceSt	-	0	0	-	-	-	-	Covered	T46,T43,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T46,T43,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T134,T175,T144
StableSt	-	-	-	-	-	-	0	Covered	T46,T43,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	78	0	0
CntIncr_A	8198376	80704	0	0
CntNoWrap_A	8198376	7499377	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	87787	0	0
DetectedPulseOut_A	8198376	38	0	0
DisabledIdleSt_A	8198376	7124971	0	0
DisabledNoDetection_A	8198376	7127344	0	0
EnterDebounceSt_A	8198376	40	0	0
EnterDetectSt_A	8198376	38	0	0
EnterStableSt_A	8198376	38	0	0
PulseIsPulse_A	8198376	38	0	0
StayInStableSt	8198376	87722	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	6875	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	78	0	0
T43	24553	2	0	0
T45	1104	0	0	0
T46	3468	2	0	0
T47	0	2	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	2	0	0
T101	4144	0	0	0
T109	0	2	0	0
T111	0	2	0	0
T134	0	2	0	0
T141	0	2	0	0
T159	0	2	0	0
T176	0	2	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	80704	0	0
T43	24553	68	0	0
T45	1104	0	0	0
T46	3468	81	0	0
T47	0	34981	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	18	0	0
T101	4144	0	0	0
T109	0	92	0	0
T111	0	81	0	0
T134	0	36	0	0
T141	0	26	0	0
T159	0	17491	0	0
T176	0	39	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499377	0	0
T13	11076	10667	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	87787	0	0
T43	24553	43	0	0
T45	1104	0	0	0
T46	3468	279	0	0
T47	0	70803	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	61	0	0
T101	4144	0	0	0
T109	0	41	0	0
T111	0	261	0	0
T134	0	7	0	0
T141	0	39	0	0
T159	0	47	0	0
T176	0	39	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	38	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T46	3468	1	0	0
T47	0	1	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	1	0	0
T101	4144	0	0	0
T109	0	1	0	0
T111	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T159	0	1	0	0
T176	0	1	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7124971	0	0
T13	11076	10667	0	0
T14	19815	6945	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7127344	0	0
T13	11076	10669	0	0
T14	19815	6979	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	40	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T46	3468	1	0	0
T47	0	1	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	1	0	0
T101	4144	0	0	0
T109	0	1	0	0
T111	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T159	0	1	0	0
T176	0	1	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	38	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T46	3468	1	0	0
T47	0	1	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	1	0	0
T101	4144	0	0	0
T109	0	1	0	0
T111	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T159	0	1	0	0
T176	0	1	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	38	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T46	3468	1	0	0
T47	0	1	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	1	0	0
T101	4144	0	0	0
T109	0	1	0	0
T111	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T159	0	1	0	0
T176	0	1	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	38	0	0
T43	24553	1	0	0
T45	1104	0	0	0
T46	3468	1	0	0
T47	0	1	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	1	0	0
T101	4144	0	0	0
T109	0	1	0	0
T111	0	1	0	0
T134	0	1	0	0
T141	0	1	0	0
T159	0	1	0	0
T176	0	1	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	87722	0	0
T43	24553	41	0	0
T45	1104	0	0	0
T46	3468	277	0	0
T47	0	70801	0	0
T50	3275	0	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	59	0	0
T101	4144	0	0	0
T109	0	39	0	0
T111	0	259	0	0
T134	0	6	0	0
T141	0	37	0	0
T159	0	45	0	0
T176	0	37	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6875	0	0
T13	11076	19	0	0
T14	19815	90	0	0
T15	12035	12	0	0
T16	8305	33	0	0
T17	0	16	0	0
T30	405	0	0	0
T31	502	7	0	0
T32	665	0	0	0
T33	497	8	0	0
T34	422	2	0	0
T35	10465	24	0	0
T57	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	10	0	0
T72	0	1	0	0
T134	618	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0
T175	1151	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	638	0	0	0
T184	425	0	0	0
T185	411	0	0	0
T186	10679	0	0	0
T187	794	0	0	0
T188	431	0	0	0
T189	482	0	0	0
T190	522	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T21,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T21,T46
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T21,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T46
0	1	Covered	T70,T191,T192
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T46
0	1	Covered	T46,T50,T142
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T21,T46
1	-	Covered	T46,T50,T142

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T21,T46
0	1	Covered	T14,T21,T46
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T21,T46
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T21,T46
IdleSt	0	-	-	-	-	-	-	Covered	T13,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T21,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T134,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T21,T46
DetectSt	-	-	-	-	1	-	-	Covered	T70,T191,T192
DetectSt	-	-	-	-	0	1	-	Covered	T14,T21,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T50,T142
StableSt	-	-	-	-	-	-	0	Covered	T14,T21,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	143	0	0
CntIncr_A	8198376	82916	0	0
CntNoWrap_A	8198376	7499312	0	0
DetectStDropOut_A	8198376	3	0	0
DetectedOut_A	8198376	5384	0	0
DetectedPulseOut_A	8198376	66	0	0
DisabledIdleSt_A	8198376	7323631	0	0
DisabledNoDetection_A	8198376	7325995	0	0
EnterDebounceSt_A	8198376	75	0	0
EnterDetectSt_A	8198376	69	0	0
EnterStableSt_A	8198376	66	0	0
PulseIsPulse_A	8198376	66	0	0
StayInStableSt	8198376	5286	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	143	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	4	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T46	0	4	0	0
T50	0	4	0	0
T57	503	0	0	0
T70	0	6	0	0
T133	0	2	0	0
T134	0	3	0	0
T142	0	4	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	82916	0	0
T14	19815	17	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	181	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	93	0	0
T46	0	162	0	0
T50	0	146	0	0
T57	503	0	0	0
T70	0	174	0	0
T133	0	36	0	0
T134	0	72	0	0
T142	0	132	0	0
T167	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499312	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	3	0	0
T70	40271	1	0	0
T134	618	0	0	0
T183	638	0	0	0
T184	425	0	0	0
T185	411	0	0	0
T186	10679	0	0	0
T191	612	1	0	0
T192	0	1	0	0
T193	404	0	0	0
T194	427	0	0	0
T195	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	5384	0	0
T14	19815	61	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	173	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T46	0	105	0	0
T50	0	90	0	0
T56	0	108	0	0
T57	503	0	0	0
T70	0	64	0	0
T133	0	41	0	0
T134	0	9	0	0
T142	0	153	0	0
T167	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	66	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T46	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T57	503	0	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T142	0	2	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7323631	0	0
T13	11076	10667	0	0
T14	19815	6945	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7325995	0	0
T13	11076	10669	0	0
T14	19815	6979	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	75	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T46	0	2	0	0
T50	0	2	0	0
T57	503	0	0	0
T70	0	3	0	0
T133	0	1	0	0
T134	0	2	0	0
T142	0	2	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	69	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T46	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T57	503	0	0	0
T70	0	3	0	0
T133	0	1	0	0
T134	0	1	0	0
T142	0	2	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	66	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T46	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T57	503	0	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T142	0	2	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	66	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T46	0	2	0	0
T50	0	2	0	0
T56	0	3	0	0
T57	503	0	0	0
T70	0	2	0	0
T133	0	1	0	0
T134	0	1	0	0
T142	0	2	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	5286	0	0
T14	19815	59	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	169	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T46	0	102	0	0
T50	0	87	0	0
T56	0	104	0	0
T57	503	0	0	0
T70	0	61	0	0
T133	0	39	0	0
T134	0	8	0	0
T142	0	150	0	0
T167	0	49	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	33	0	0
T43	24553	0	0	0
T45	1104	0	0	0
T46	3468	1	0	0
T50	3275	1	0	0
T51	9693	0	0	0
T52	23803	0	0	0
T56	0	2	0	0
T70	0	1	0	0
T71	0	1	0	0
T101	4144	0	0	0
T110	0	1	0	0
T134	0	1	0	0
T136	0	1	0	0
T142	0	1	0	0
T144	0	2	0	0
T177	502	0	0	0
T178	831	0	0	0
T179	503	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T19,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T19,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T19,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T19,T50
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T19,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T45
0	1	Covered	T196
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T19,T45
0	1	Covered	T45,T141,T71
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T19,T45
1	-	Covered	T45,T141,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T19,T50
0	1	Covered	T14,T19,T50
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T19,T45
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T19,T50
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T19,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T19,T50
DetectSt	-	-	-	-	1	-	-	Covered	T196
DetectSt	-	-	-	-	0	1	-	Covered	T14,T19,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T141,T71
StableSt	-	-	-	-	-	-	0	Covered	T14,T19,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	99	0	0
CntIncr_A	8198376	55247	0	0
CntNoWrap_A	8198376	7499356	0	0
DetectStDropOut_A	8198376	1	0	0
DetectedOut_A	8198376	16535	0	0
DetectedPulseOut_A	8198376	47	0	0
DisabledIdleSt_A	8198376	7321555	0	0
DisabledNoDetection_A	8198376	7323916	0	0
EnterDebounceSt_A	8198376	51	0	0
EnterDetectSt_A	8198376	48	0	0
EnterStableSt_A	8198376	47	0	0
PulseIsPulse_A	8198376	47	0	0
StayInStableSt	8198376	16462	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	6528	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	99	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	4	0	0
T50	0	1	0	0
T57	503	0	0	0
T71	0	4	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T140	0	2	0	0
T141	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	55247	0	0
T14	19815	11	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	14	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	182	0	0
T50	0	73	0	0
T57	503	0	0	0
T71	0	20	0	0
T109	0	92	0	0
T110	0	47	0	0
T111	0	81	0	0
T140	0	65	0	0
T141	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499356	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1	0	0
T68	16730	0	0	0
T196	560	1	0	0
T198	10376	0	0	0
T199	990	0	0	0
T200	2509	0	0	0
T201	403	0	0	0
T202	493	0	0	0
T203	504	0	0	0
T204	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	16535	0	0
T14	19815	45	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	53	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	210	0	0
T57	503	0	0	0
T71	0	90	0	0
T109	0	41	0	0
T110	0	198	0	0
T111	0	139	0	0
T140	0	41	0	0
T141	0	78	0	0
T175	0	56	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	47	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T57	503	0	0	0
T71	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T175	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7321555	0	0
T13	11076	10667	0	0
T14	19815	6802	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7323916	0	0
T13	11076	10669	0	0
T14	19815	6836	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	51	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T50	0	1	0	0
T57	503	0	0	0
T71	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	48	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T57	503	0	0	0
T71	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T175	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	47	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T57	503	0	0	0
T71	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T175	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	47	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T57	503	0	0	0
T71	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T175	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	16462	0	0
T14	19815	43	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T19	0	51	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	208	0	0
T57	503	0	0	0
T71	0	87	0	0
T109	0	39	0	0
T110	0	197	0	0
T111	0	137	0	0
T140	0	39	0	0
T141	0	75	0	0
T175	0	55	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6528	0	0
T13	11076	23	0	0
T14	19815	79	0	0
T15	12035	11	0	0
T16	8305	28	0	0
T17	0	17	0	0
T30	405	0	0	0
T31	502	4	0	0
T32	665	0	0	0
T33	497	7	0	0
T34	422	2	0	0
T35	10465	30	0	0
T57	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	20	0	0
T44	23959	0	0	0
T45	1104	2	0	0
T52	23803	0	0	0
T53	3296	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T101	4144	0	0	0
T102	522	0	0	0
T103	488	0	0	0
T104	507	0	0	0
T105	402	0	0	0
T106	9206	0	0	0
T110	0	1	0	0
T132	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T141	0	1	0	0
T144	0	2	0	0
T175	0	1	0	0