Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T17,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T21
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T17,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T21
0	1	Covered	T70,T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T21
0	1	Covered	T14,T21,T46
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T21
1	-	Covered	T14,T21,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T21
0	1	Covered	T14,T17,T21
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T21
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T21
IdleSt	0	-	-	-	-	-	-	Covered	T13,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T133,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T21
DetectSt	-	-	-	-	1	-	-	Covered	T70,T71
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T21,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	167	0	0
CntIncr_A	8198376	48425	0	0
CntNoWrap_A	8198376	7499288	0	0
DetectStDropOut_A	8198376	2	0	0
DetectedOut_A	8198376	13391	0	0
DetectedPulseOut_A	8198376	78	0	0
DisabledIdleSt_A	8198376	7295264	0	0
DisabledNoDetection_A	8198376	7297618	0	0
EnterDebounceSt_A	8198376	87	0	0
EnterDetectSt_A	8198376	80	0	0
EnterStableSt_A	8198376	78	0	0
PulseIsPulse_A	8198376	78	0	0
StayInStableSt	8198376	13275	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	167	0	0
T14	19815	4	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	3	0	0
T21	0	4	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T46	0	4	0	0
T52	0	4	0	0
T57	503	0	0	0
T133	0	5	0	0
T140	0	2	0	0
T141	0	2	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	48425	0	0
T14	19815	22	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	190	0	0
T21	0	121	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	91	0	0
T46	0	162	0	0
T52	0	126	0	0
T57	503	0	0	0
T133	0	134	0	0
T140	0	65	0	0
T141	0	26	0	0
T176	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499288	0	0
T13	11076	10667	0	0
T14	19815	7024	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2	0	0
T70	40271	1	0	0
T71	22165	1	0	0
T76	4573	0	0	0
T134	618	0	0	0
T183	638	0	0	0
T184	425	0	0	0
T185	411	0	0	0
T186	10679	0	0	0
T205	548	0	0	0
T206	508	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	13391	0	0
T14	19815	106	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	38	0	0
T21	0	173	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	471	0	0
T46	0	223	0	0
T52	0	296	0	0
T57	503	0	0	0
T133	0	59	0	0
T140	0	65	0	0
T141	0	237	0	0
T176	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	78	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	2	0	0
T57	503	0	0	0
T133	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7295264	0	0
T13	11076	10667	0	0
T14	19815	6802	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7297618	0	0
T13	11076	10669	0	0
T14	19815	6836	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	87	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	2	0	0
T57	503	0	0	0
T133	0	3	0	0
T140	0	1	0	0
T141	0	1	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	80	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	2	0	0
T57	503	0	0	0
T133	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	78	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	2	0	0
T57	503	0	0	0
T133	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	78	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	2	0	0
T57	503	0	0	0
T133	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	13275	0	0
T14	19815	103	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	36	0	0
T21	0	170	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	470	0	0
T46	0	220	0	0
T52	0	293	0	0
T57	503	0	0	0
T133	0	56	0	0
T140	0	63	0	0
T141	0	235	0	0
T176	0	114	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	39	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T56	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T133	0	1	0	0
T142	0	1	0	0
T168	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T19
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T19
1	-	Covered	T14,T17,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T19
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T196,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T19
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	74	0	0
CntIncr_A	8198376	28360	0	0
CntNoWrap_A	8198376	7499381	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	29532	0	0
DetectedPulseOut_A	8198376	35	0	0
DisabledIdleSt_A	8198376	7323569	0	0
DisabledNoDetection_A	8198376	7325934	0	0
EnterDebounceSt_A	8198376	39	0	0
EnterDetectSt_A	8198376	35	0	0
EnterStableSt_A	8198376	35	0	0
PulseIsPulse_A	8198376	35	0	0
StayInStableSt	8198376	29477	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	6432	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	74	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T52	0	2	0	0
T57	503	0	0	0
T70	0	4	0	0
T111	0	4	0	0
T133	0	4	0	0
T142	0	2	0	0
T207	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	28360	0	0
T14	19815	11	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	95	0	0
T19	0	14	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	68	0	0
T52	0	63	0	0
T57	503	0	0	0
T70	0	116	0	0
T111	0	162	0	0
T133	0	72	0	0
T142	0	66	0	0
T207	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499381	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	29532	0	0
T14	19815	62	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	222	0	0
T19	0	59	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	155	0	0
T52	0	49	0	0
T57	503	0	0	0
T70	0	226	0	0
T111	0	86	0	0
T133	0	85	0	0
T142	0	106	0	0
T207	0	173	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	35	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	2	0	0
T111	0	2	0	0
T133	0	2	0	0
T142	0	1	0	0
T207	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7323569	0	0
T13	11076	10667	0	0
T14	19815	6719	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7325934	0	0
T13	11076	10669	0	0
T14	19815	6752	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	39	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	2	0	0
T111	0	2	0	0
T133	0	2	0	0
T142	0	1	0	0
T207	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	35	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	2	0	0
T111	0	2	0	0
T133	0	2	0	0
T142	0	1	0	0
T207	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	35	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	2	0	0
T111	0	2	0	0
T133	0	2	0	0
T142	0	1	0	0
T207	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	35	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	2	0	0
T111	0	2	0	0
T133	0	2	0	0
T142	0	1	0	0
T207	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	29477	0	0
T14	19815	61	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	221	0	0
T19	0	58	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	154	0	0
T52	0	48	0	0
T57	503	0	0	0
T70	0	223	0	0
T111	0	83	0	0
T133	0	82	0	0
T142	0	104	0	0
T207	0	171	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6432	0	0
T13	11076	31	0	0
T14	19815	82	0	0
T15	12035	13	0	0
T16	8305	34	0	0
T17	0	21	0	0
T30	405	0	0	0
T31	502	3	0	0
T32	665	0	0	0
T33	497	7	0	0
T34	422	2	0	0
T35	10465	33	0	0
T57	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	14	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T111	0	1	0	0
T132	0	1	0	0
T133	0	1	0	0
T135	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T13,T14,T15
1	1	Covered	T13,T14,T15

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T17,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T21
1	0	Covered	T13,T14,T15
1	1	Covered	T14,T17,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T21
0	1	Covered	T132
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T21
0	1	Covered	T14,T21,T46
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T21
1	-	Covered	T14,T21,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T21
0	1	Covered	T14,T17,T21
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T21
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T21
IdleSt	0	-	-	-	-	-	-	Covered	T13,T14,T15
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T50,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T21
DetectSt	-	-	-	-	1	-	-	Covered	T132
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T21,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	145	0	0
CntIncr_A	8198376	38841	0	0
CntNoWrap_A	8198376	7499310	0	0
DetectStDropOut_A	8198376	1	0	0
DetectedOut_A	8198376	9442	0	0
DetectedPulseOut_A	8198376	70	0	0
DisabledIdleSt_A	8198376	7305544	0	0
DisabledNoDetection_A	8198376	7307908	0	0
EnterDebounceSt_A	8198376	74	0	0
EnterDetectSt_A	8198376	71	0	0
EnterStableSt_A	8198376	70	0	0
PulseIsPulse_A	8198376	70	0	0
StayInStableSt	8198376	9337	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	145	0	0
T14	19815	6	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T21	0	6	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T50	0	3	0	0
T57	503	0	0	0
T109	0	2	0	0
T133	0	4	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	38841	0	0
T14	19815	39	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	95	0	0
T21	0	146	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	91	0	0
T46	0	162	0	0
T47	0	34981	0	0
T50	0	146	0	0
T57	503	0	0	0
T109	0	92	0	0
T133	0	98	0	0
T167	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499310	0	0
T13	11076	10667	0	0
T14	19815	7022	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1	0	0
T132	3293	1	0	0
T145	5540	0	0	0
T146	12328	0	0	0
T208	1816	0	0	0
T209	502	0	0	0
T210	517	0	0	0
T211	417	0	0	0
T212	33695	0	0	0
T213	502	0	0	0
T214	15349	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	9442	0	0
T14	19815	182	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	37	0	0
T21	0	226	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	43	0	0
T46	0	226	0	0
T47	0	4006	0	0
T50	0	123	0	0
T57	503	0	0	0
T109	0	76	0	0
T133	0	236	0	0
T167	0	143	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	3	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	2	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7305544	0	0
T13	11076	10667	0	0
T14	19815	6719	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7307908	0	0
T13	11076	10669	0	0
T14	19815	6752	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	74	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	3	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	2	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	2	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	71	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	3	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	2	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	3	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	2	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	70	0	0
T14	19815	3	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T21	0	3	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T50	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	2	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	9337	0	0
T14	19815	177	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	35	0	0
T21	0	221	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	42	0	0
T46	0	223	0	0
T47	0	4005	0	0
T50	0	121	0	0
T57	503	0	0	0
T109	0	75	0	0
T133	0	233	0	0
T167	0	141	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	34	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T133	0	1	0	0
T141	0	2	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T21,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T21,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T21,T43
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T21,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T21,T43
0	1	Covered	T14,T21,T43
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T21,T43
1	-	Covered	T14,T21,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T21,T43
0	1	Covered	T14,T21,T43
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T21,T43
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T21,T43
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T21,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T175
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T21,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T21,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T21,T43
StableSt	-	-	-	-	-	-	0	Covered	T14,T21,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	74	0	0
CntIncr_A	8198376	2207	0	0
CntNoWrap_A	8198376	7499381	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	2348	0	0
DetectedPulseOut_A	8198376	36	0	0
DisabledIdleSt_A	8198376	7453025	0	0
DisabledNoDetection_A	8198376	7455395	0	0
EnterDebounceSt_A	8198376	38	0	0
EnterDetectSt_A	8198376	36	0	0
EnterStableSt_A	8198376	36	0	0
PulseIsPulse_A	8198376	36	0	0
StayInStableSt	8198376	2297	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	6569	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	74	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T52	0	4	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	2	0	0
T111	0	4	0	0
T133	0	2	0	0
T141	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2207	0	0
T14	19815	11	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	25	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	68	0	0
T45	0	91	0	0
T52	0	126	0	0
T53	0	60	0	0
T57	503	0	0	0
T109	0	92	0	0
T111	0	162	0	0
T133	0	62	0	0
T141	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499381	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2348	0	0
T14	19815	64	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	15	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	154	0	0
T45	0	301	0	0
T52	0	81	0	0
T53	0	54	0	0
T57	503	0	0	0
T109	0	40	0	0
T111	0	139	0	0
T133	0	41	0	0
T141	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T133	0	1	0	0
T141	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7453025	0	0
T13	11076	10667	0	0
T14	19815	6802	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7455395	0	0
T13	11076	10669	0	0
T14	19815	6836	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	38	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T133	0	1	0	0
T141	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T133	0	1	0	0
T141	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T133	0	1	0	0
T141	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	36	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T111	0	2	0	0
T133	0	1	0	0
T141	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2297	0	0
T14	19815	63	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	14	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	153	0	0
T45	0	299	0	0
T52	0	79	0	0
T53	0	52	0	0
T57	503	0	0	0
T109	0	38	0	0
T111	0	136	0	0
T133	0	39	0	0
T141	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6569	0	0
T13	11076	29	0	0
T14	19815	88	0	0
T15	12035	14	0	0
T16	8305	26	0	0
T17	0	18	0	0
T30	405	0	0	0
T31	502	4	0	0
T32	665	0	0	0
T33	497	6	0	0
T34	422	3	0	0
T35	10465	32	0	0
T57	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	20	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T52	0	2	0	0
T57	503	0	0	0
T111	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T41,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T30
1	0	Covered	T41,T13,T14
1	1	Covered	T41,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T19
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T19
1	-	Covered	T14,T17,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T19
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T159,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T17,T19
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	132	0	0
CntIncr_A	8198376	143741	0	0
CntNoWrap_A	8198376	7499323	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	79241	0	0
DetectedPulseOut_A	8198376	63	0	0
DisabledIdleSt_A	8198376	7121845	0	0
DisabledNoDetection_A	8198376	7124207	0	0
EnterDebounceSt_A	8198376	69	0	0
EnterDetectSt_A	8198376	63	0	0
EnterStableSt_A	8198376	63	0	0
PulseIsPulse_A	8198376	63	0	0
StayInStableSt	8198376	79157	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	41	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	132	0	0
T14	19815	4	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	4	0	0
T19	0	2	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	2	0	0
T47	0	4	0	0
T53	0	2	0	0
T57	503	0	0	0
T109	0	2	0	0
T133	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	143741	0	0
T14	19815	28	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	190	0	0
T19	0	14	0	0
T21	0	25	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	93	0	0
T45	0	91	0	0
T47	0	69962	0	0
T53	0	60	0	0
T57	503	0	0	0
T109	0	92	0	0
T133	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499323	0	0
T13	11076	10667	0	0
T14	19815	7024	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	79241	0	0
T14	19815	9	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	173	0	0
T19	0	4	0	0
T21	0	90	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	41	0	0
T47	0	66831	0	0
T53	0	164	0	0
T57	503	0	0	0
T109	0	44	0	0
T133	0	40	0	0
T176	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	63	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7121845	0	0
T13	11076	10667	0	0
T14	19815	6719	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7124207	0	0
T13	11076	10669	0	0
T14	19815	6752	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	69	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	63	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	63	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	63	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T109	0	1	0	0
T133	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	79157	0	0
T14	19815	7	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	170	0	0
T19	0	3	0	0
T21	0	89	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	40	0	0
T47	0	66829	0	0
T53	0	163	0	0
T57	503	0	0	0
T109	0	43	0	0
T133	0	38	0	0
T176	0	113	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	41	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T70	0	1	0	0
T109	0	1	0	0
T141	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T41,T13,T14
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T41,T13,T14
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T17,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T17,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T17,T19
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T17,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T19
0	1	Covered	T17,T56,T144
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T19
1	-	Covered	T17,T56,T144

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T19
0	1	Covered	T14,T17,T19
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T19
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T19
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T135,T138
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T56,T144
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	91	0	0
CntIncr_A	8198376	142407	0	0
CntNoWrap_A	8198376	7499364	0	0
DetectStDropOut_A	8198376	0	0	0
DetectedOut_A	8198376	43448	0	0
DetectedPulseOut_A	8198376	43	0	0
DisabledIdleSt_A	8198376	7130020	0	0
DisabledNoDetection_A	8198376	7132383	0	0
EnterDebounceSt_A	8198376	48	0	0
EnterDetectSt_A	8198376	43	0	0
EnterStableSt_A	8198376	43	0	0
PulseIsPulse_A	8198376	43	0	0
StayInStableSt	8198376	43374	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8198376	7192	0	0
gen_low_level_sva.LowLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	91	0	0
T14	19815	2	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	2	0	0
T19	0	2	0	0
T21	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	3	0	0
T53	0	2	0	0
T57	503	0	0	0
T133	0	2	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	142407	0	0
T14	19815	11	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	95	0	0
T19	0	14	0	0
T21	0	25	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	91	0	0
T46	0	81	0	0
T47	0	69962	0	0
T53	0	60	0	0
T57	503	0	0	0
T133	0	36	0	0
T140	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7499364	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	43448	0	0
T14	19815	120	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	87	0	0
T19	0	112	0	0
T21	0	86	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	436	0	0
T46	0	279	0	0
T47	0	43	0	0
T53	0	53	0	0
T57	503	0	0	0
T133	0	41	0	0
T140	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	43	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7130020	0	0
T13	11076	10667	0	0
T14	19815	6802	0	0
T15	12035	11615	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7132383	0	0
T13	11076	10669	0	0
T14	19815	6836	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	48	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T53	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	43	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	43	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	43	0	0
T14	19815	1	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	1	0	0
T19	0	1	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	503	0	0	0
T133	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	43374	0	0
T14	19815	118	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T17	36108	86	0	0
T19	0	110	0	0
T21	0	84	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T45	0	434	0	0
T46	0	277	0	0
T47	0	41	0	0
T53	0	51	0	0
T57	503	0	0	0
T133	0	39	0	0
T140	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7192	0	0
T13	11076	35	0	0
T14	19815	106	0	0
T15	12035	12	0	0
T16	8305	28	0	0
T30	405	0	0	0
T31	502	6	0	0
T32	665	3	0	0
T33	497	8	0	0
T34	422	2	0	0
T35	0	23	0	0
T41	2031	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	11	0	0
T17	36108	1	0	0
T18	830	0	0	0
T19	555	0	0	0
T56	12734	1	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T97	0	1	0	0
T129	0	2	0	0
T136	0	1	0	0
T138	0	1	0	0
T144	0	1	0	0
T197	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0