Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T35
1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T35
1	0	Covered	T13,T16,T35
1	1	Covered	T13,T16,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T35
0	1	Covered	T16,T79,T81
1	0	Covered	T16,T81,T82

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T35,T20
0	1	Covered	T13,T35,T20
1	0	Covered	T67

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T35,T20
1	-	Covered	T13,T35,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T35
0	1	Covered	T13,T16,T35
0	0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T35
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T35
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T63,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T35
DetectSt	-	-	-	-	1	-	-	Covered	T16,T79,T81
DetectSt	-	-	-	-	0	1	-	Covered	T13,T35,T20
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T35
StableSt	-	-	-	-	-	-	1	Covered	T13,T35,T20
StableSt	-	-	-	-	-	-	0	Covered	T13,T35,T20
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	3206	0	0
CntIncr_A	8198376	124134	0	0
CntNoWrap_A	8198376	7496249	0	0
DetectStDropOut_A	8198376	451	0	0
DetectedOut_A	8198376	83290	0	0
DetectedPulseOut_A	8198376	917	0	0
DisabledIdleSt_A	8198376	6977644	0	0
DisabledNoDetection_A	8198376	6979874	0	0
EnterDebounceSt_A	8198376	1609	0	0
EnterDetectSt_A	8198376	1597	0	0
EnterStableSt_A	8198376	917	0	0
PulseIsPulse_A	8198376	917	0	0
StayInStableSt	8198376	82276	0	0
gen_high_event_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	797	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	3206	0	0
T13	11076	38	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	32	0	0
T20	0	20	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	28	0	0
T48	0	62	0	0
T78	0	46	0	0
T79	0	30	0	0
T81	0	46	0	0
T82	0	8	0	0
T100	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	124134	0	0
T13	11076	1748	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	755	0	0
T20	0	450	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	840	0	0
T48	0	2697	0	0
T78	0	1426	0	0
T79	0	1019	0	0
T81	0	2704	0	0
T82	0	132	0	0
T100	0	1152	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7496249	0	0
T13	11076	10629	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7864	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	451	0	0
T16	8305	10	0	0
T17	36108	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T51	0	7	0	0
T57	503	0	0	0
T65	2235	0	0	0
T79	0	15	0	0
T81	0	8	0	0
T82	0	1	0	0
T85	660	0	0	0
T86	504	0	0	0
T88	0	25	0	0
T89	0	26	0	0
T90	0	6	0	0
T186	0	8	0	0
T218	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	83290	0	0
T13	11076	1719	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T20	0	788	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	354	0	0
T48	0	2725	0	0
T78	0	1362	0	0
T100	0	1016	0	0
T106	0	1462	0	0
T107	0	2198	0	0
T108	0	1589	0	0
T219	0	1566	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	917	0	0
T13	11076	19	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T20	0	10	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	14	0	0
T48	0	31	0	0
T78	0	23	0	0
T100	0	24	0	0
T106	0	19	0	0
T107	0	24	0	0
T108	0	13	0	0
T219	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6977644	0	0
T13	11076	4099	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	5339	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6979874	0	0
T13	11076	4099	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	5340	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1609	0	0
T13	11076	19	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	16	0	0
T20	0	10	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	14	0	0
T48	0	31	0	0
T78	0	23	0	0
T79	0	15	0	0
T81	0	23	0	0
T82	0	4	0	0
T100	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1597	0	0
T13	11076	19	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	16	0	0
T20	0	10	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	14	0	0
T48	0	31	0	0
T78	0	23	0	0
T79	0	15	0	0
T81	0	23	0	0
T82	0	4	0	0
T100	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	917	0	0
T13	11076	19	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T20	0	10	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	14	0	0
T48	0	31	0	0
T78	0	23	0	0
T100	0	24	0	0
T106	0	19	0	0
T107	0	24	0	0
T108	0	13	0	0
T219	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	917	0	0
T13	11076	19	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T20	0	10	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	14	0	0
T48	0	31	0	0
T78	0	23	0	0
T100	0	24	0	0
T106	0	19	0	0
T107	0	24	0	0
T108	0	13	0	0
T219	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	82276	0	0
T13	11076	1699	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T20	0	777	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	340	0	0
T48	0	2683	0	0
T78	0	1338	0	0
T100	0	991	0	0
T106	0	1443	0	0
T107	0	2171	0	0
T108	0	1573	0	0
T219	0	1540	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	797	0	0
T13	11076	18	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T20	0	9	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	14	0	0
T48	0	20	0	0
T78	0	22	0	0
T100	0	23	0	0
T106	0	19	0	0
T107	0	21	0	0
T108	0	10	0	0
T219	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T13,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T14
1	1	Covered	T13,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T62,T44,T91
1	0	Covered	T63,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T63,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T15
1	-	Covered	T13,T14,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T65,T20
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T62,T44,T91
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	0	0	-	Covered	T13,T14,T15
StableSt	-	-	-	-	-	-	1	Covered	T13,T14,T15
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	950	0	0
CntIncr_A	8198376	48811	0	0
CntNoWrap_A	8198376	7498505	0	0
DetectStDropOut_A	8198376	65	0	0
DetectedOut_A	8198376	15197	0	0
DetectedPulseOut_A	8198376	366	0	0
DisabledIdleSt_A	8198376	7101189	0	0
DisabledNoDetection_A	8198376	7102863	0	0
EnterDebounceSt_A	8198376	516	0	0
EnterDetectSt_A	8198376	436	0	0
EnterStableSt_A	8198376	366	0	0
PulseIsPulse_A	8198376	366	0	0
StayInStableSt	8198376	14796	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	327	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	950	0	0
T13	11076	2	0	0
T14	19815	4	0	0
T15	12035	6	0	0
T16	8305	0	0	0
T17	0	15	0	0
T20	0	3	0	0
T21	0	6	0	0
T22	0	5	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	18	0	0
T65	0	1	0	0
T78	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	48811	0	0
T13	11076	93	0	0
T14	19815	123	0	0
T15	12035	279	0	0
T16	8305	0	0	0
T17	0	556	0	0
T20	0	71	0	0
T21	0	90	0	0
T22	0	194	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	504	0	0
T65	0	20	0	0
T78	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7498505	0	0
T13	11076	10665	0	0
T14	19815	7024	0	0
T15	12035	11609	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	65	0	0
T42	29850	0	0	0
T44	23959	1	0	0
T56	0	1	0	0
T62	14704	1	0	0
T81	23686	0	0	0
T82	11966	0	0	0
T91	0	1	0	0
T92	0	5	0	0
T93	0	2	0	0
T94	0	1	0	0
T95	0	2	0	0
T96	0	4	0	0
T98	0	12	0	0
T99	1158	0	0	0
T100	8236	0	0	0
T103	488	0	0	0
T104	507	0	0	0
T105	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	15197	0	0
T13	11076	54	0	0
T14	19815	50	0	0
T15	12035	69	0	0
T16	8305	0	0	0
T17	0	486	0	0
T20	0	87	0	0
T21	0	7	0	0
T22	0	121	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	291	0	0
T78	0	36	0	0
T100	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	366	0	0
T13	11076	1	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	7	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	9	0	0
T78	0	1	0	0
T100	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7101189	0	0
T13	11076	8949	0	0
T14	19815	6538	0	0
T15	12035	8056	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7102863	0	0
T13	11076	8950	0	0
T14	19815	6571	0	0
T15	12035	8056	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	516	0	0
T13	11076	1	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	8	0	0
T20	0	2	0	0
T21	0	4	0	0
T22	0	3	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	9	0	0
T65	0	1	0	0
T78	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	436	0	0
T13	11076	1	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	7	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	9	0	0
T62	0	1	0	0
T78	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	366	0	0
T13	11076	1	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	7	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	9	0	0
T78	0	1	0	0
T100	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	366	0	0
T13	11076	1	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	7	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	9	0	0
T78	0	1	0	0
T100	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	14796	0	0
T13	11076	53	0	0
T14	19815	48	0	0
T15	12035	66	0	0
T16	8305	0	0	0
T17	0	479	0	0
T20	0	86	0	0
T21	0	5	0	0
T22	0	119	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	273	0	0
T78	0	34	0	0
T100	0	20	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	327	0	0
T13	11076	1	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	7	0	0
T20	0	1	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	3	0	0
T44	0	1	0	0
T106	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T35
1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T35
1	0	Covered	T13,T16,T35
1	1	Covered	T13,T16,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T35
0	1	Covered	T35,T78,T79
1	0	Covered	T35,T20,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T48
0	1	Covered	T13,T16,T48
1	0	Covered	T66,T220

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T16,T48
1	-	Covered	T13,T16,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T35
0	1	Covered	T13,T16,T35
0	0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T35
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T35
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T63,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35,T20,T78
DetectSt	-	-	-	-	0	1	-	Covered	T13,T16,T48
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T35
StableSt	-	-	-	-	-	-	1	Covered	T13,T16,T48
StableSt	-	-	-	-	-	-	0	Covered	T13,T16,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	2993	0	0
CntIncr_A	8198376	111814	0	0
CntNoWrap_A	8198376	7496462	0	0
DetectStDropOut_A	8198376	363	0	0
DetectedOut_A	8198376	92237	0	0
DetectedPulseOut_A	8198376	932	0	0
DisabledIdleSt_A	8198376	6971747	0	0
DisabledNoDetection_A	8198376	6973968	0	0
EnterDebounceSt_A	8198376	1501	0	0
EnterDetectSt_A	8198376	1492	0	0
EnterStableSt_A	8198376	932	0	0
PulseIsPulse_A	8198376	932	0	0
StayInStableSt	8198376	91200	0	0
gen_high_event_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	804	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	2993	0	0
T13	11076	12	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	52	0	0
T20	0	16	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	52	0	0
T48	0	32	0	0
T78	0	14	0	0
T79	0	20	0	0
T81	0	56	0	0
T82	0	18	0	0
T100	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	111814	0	0
T13	11076	480	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	858	0	0
T20	0	429	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	2177	0	0
T48	0	896	0	0
T78	0	453	0	0
T79	0	672	0	0
T81	0	3284	0	0
T82	0	288	0	0
T100	0	273	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7496462	0	0
T13	11076	10655	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7844	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	363	0	0
T17	36108	0	0	0
T18	830	0	0	0
T19	555	0	0	0
T35	10465	7	0	0
T57	503	0	0	0
T59	497	0	0	0
T65	2235	0	0	0
T66	0	9	0	0
T78	0	5	0	0
T79	0	10	0	0
T81	0	15	0	0
T85	660	0	0	0
T86	504	0	0	0
T87	427	0	0	0
T88	0	25	0	0
T89	0	30	0	0
T90	0	12	0	0
T186	0	16	0	0
T218	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	92237	0	0
T13	11076	249	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	1658	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	1631	0	0
T51	0	494	0	0
T82	0	143	0	0
T100	0	120	0	0
T106	0	1253	0	0
T107	0	199	0	0
T108	0	3258	0	0
T219	0	385	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	932	0	0
T13	11076	6	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	26	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	16	0	0
T51	0	10	0	0
T82	0	9	0	0
T100	0	7	0	0
T106	0	19	0	0
T107	0	6	0	0
T108	0	27	0	0
T219	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6971747	0	0
T13	11076	5638	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	4029	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6973968	0	0
T13	11076	5638	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	4029	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1501	0	0
T13	11076	6	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	26	0	0
T20	0	8	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	26	0	0
T48	0	16	0	0
T78	0	7	0	0
T79	0	10	0	0
T81	0	28	0	0
T82	0	9	0	0
T100	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1492	0	0
T13	11076	6	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	26	0	0
T20	0	8	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	26	0	0
T48	0	16	0	0
T78	0	7	0	0
T79	0	10	0	0
T81	0	28	0	0
T82	0	9	0	0
T100	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	932	0	0
T13	11076	6	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	26	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	16	0	0
T51	0	10	0	0
T82	0	9	0	0
T100	0	7	0	0
T106	0	19	0	0
T107	0	6	0	0
T108	0	27	0	0
T219	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	932	0	0
T13	11076	6	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	26	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	16	0	0
T51	0	10	0	0
T82	0	9	0	0
T100	0	7	0	0
T106	0	19	0	0
T107	0	6	0	0
T108	0	27	0	0
T219	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	91200	0	0
T13	11076	242	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	1631	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	1609	0	0
T51	0	484	0	0
T82	0	134	0	0
T100	0	113	0	0
T106	0	1234	0	0
T107	0	193	0	0
T108	0	3223	0	0
T219	0	373	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	804	0	0
T13	11076	5	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	25	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T48	0	10	0	0
T51	0	10	0	0
T82	0	9	0	0
T100	0	7	0	0
T106	0	19	0	0
T107	0	6	0	0
T108	0	19	0	0
T219	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T13,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T14
1	1	Covered	T13,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T16
0	1	Covered	T15,T21,T221
1	0	Covered	T63,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T17
0	1	Covered	T13,T16,T17
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T16,T17
1	-	Covered	T13,T16,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T16
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T22,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T15,T21,T221
DetectSt	-	-	-	-	0	1	-	Covered	T13,T16,T17
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T16
StableSt	-	-	-	-	-	-	1	Covered	T13,T16,T17
StableSt	-	-	-	-	-	-	0	Covered	T13,T16,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	858	0	0
CntIncr_A	8198376	48621	0	0
CntNoWrap_A	8198376	7498597	0	0
DetectStDropOut_A	8198376	65	0	0
DetectedOut_A	8198376	15983	0	0
DetectedPulseOut_A	8198376	337	0	0
DisabledIdleSt_A	8198376	7096912	0	0
DisabledNoDetection_A	8198376	7098641	0	0
EnterDebounceSt_A	8198376	452	0	0
EnterDetectSt_A	8198376	407	0	0
EnterStableSt_A	8198376	337	0	0
PulseIsPulse_A	8198376	337	0	0
StayInStableSt	8198376	15611	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	300	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	858	0	0
T13	11076	2	0	0
T14	19815	0	0	0
T15	12035	6	0	0
T16	8305	4	0	0
T17	0	23	0	0
T21	0	3	0	0
T22	0	5	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	2	0	0
T44	0	19	0	0
T48	0	8	0	0
T52	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	48621	0	0
T13	11076	79	0	0
T14	19815	0	0	0
T15	12035	348	0	0
T16	8305	100	0	0
T17	0	1527	0	0
T21	0	702	0	0
T22	0	250	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	138	0	0
T44	0	818	0	0
T48	0	236	0	0
T52	0	420	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7498597	0	0
T13	11076	10665	0	0
T14	19815	7028	0	0
T15	12035	11609	0	0
T16	8305	7892	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	65	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	36108	0	0	0
T21	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T57	503	0	0	0
T70	0	2	0	0
T85	660	0	0	0
T92	0	3	0	0
T94	0	4	0	0
T116	0	2	0	0
T215	0	1	0	0
T221	0	4	0	0
T222	0	7	0	0
T223	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	15983	0	0
T13	11076	68	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	113	0	0
T17	0	47	0	0
T22	0	64	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	16	0	0
T44	0	368	0	0
T48	0	119	0	0
T52	0	97	0	0
T106	0	507	0	0
T108	0	253	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	337	0	0
T13	11076	1	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	2	0	0
T17	0	10	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T44	0	9	0	0
T48	0	4	0	0
T52	0	3	0	0
T106	0	7	0	0
T108	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7096912	0	0
T13	11076	10419	0	0
T14	19815	6617	0	0
T15	12035	8056	0	0
T16	8305	6239	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7098641	0	0
T13	11076	10420	0	0
T14	19815	6651	0	0
T15	12035	8056	0	0
T16	8305	6240	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	452	0	0
T13	11076	1	0	0
T14	19815	0	0	0
T15	12035	3	0	0
T16	8305	2	0	0
T17	0	13	0	0
T21	0	2	0	0
T22	0	3	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T44	0	10	0	0
T48	0	4	0	0
T52	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	407	0	0
T13	11076	1	0	0
T14	19815	0	0	0
T15	12035	3	0	0
T16	8305	2	0	0
T17	0	10	0	0
T21	0	2	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T44	0	9	0	0
T48	0	4	0	0
T52	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	337	0	0
T13	11076	1	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	2	0	0
T17	0	10	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T44	0	9	0	0
T48	0	4	0	0
T52	0	3	0	0
T106	0	7	0	0
T108	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	337	0	0
T13	11076	1	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	2	0	0
T17	0	10	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T44	0	9	0	0
T48	0	4	0	0
T52	0	3	0	0
T106	0	7	0	0
T108	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	15611	0	0
T13	11076	67	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	111	0	0
T17	0	37	0	0
T22	0	62	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	15	0	0
T44	0	359	0	0
T48	0	111	0	0
T52	0	94	0	0
T106	0	500	0	0
T108	0	247	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	300	0	0
T13	11076	1	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	2	0	0
T17	0	10	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T44	0	9	0	0
T52	0	3	0	0
T106	0	7	0	0
T108	0	6	0	0
T153	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T35
1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T35
1	0	Covered	T13,T16,T35
1	1	Covered	T13,T16,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T35
0	1	Covered	T78,T79,T48
1	0	Covered	T78,T48,T224

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T35
0	1	Covered	T13,T16,T35
1	0	Covered	T67,T68,T225

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T16,T35
1	-	Covered	T13,T16,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T35
0	1	Covered	T13,T16,T35
0	0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T35
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T35
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T63,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T35
DetectSt	-	-	-	-	1	-	-	Covered	T78,T79,T48
DetectSt	-	-	-	-	0	1	-	Covered	T13,T16,T35
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T35
StableSt	-	-	-	-	-	-	1	Covered	T13,T16,T35
StableSt	-	-	-	-	-	-	0	Covered	T13,T16,T35
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	3383	0	0
CntIncr_A	8198376	126614	0	0
CntNoWrap_A	8198376	7496072	0	0
DetectStDropOut_A	8198376	417	0	0
DetectedOut_A	8198376	97420	0	0
DetectedPulseOut_A	8198376	1111	0	0
DisabledIdleSt_A	8198376	6969396	0	0
DisabledNoDetection_A	8198376	6971611	0	0
EnterDebounceSt_A	8198376	1696	0	0
EnterDetectSt_A	8198376	1687	0	0
EnterStableSt_A	8198376	1111	0	0
PulseIsPulse_A	8198376	1111	0	0
StayInStableSt	8198376	96198	0	0
gen_high_event_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	969	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	3383	0	0
T13	11076	62	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	20	0	0
T20	0	30	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	48	0	0
T48	0	50	0	0
T78	0	50	0	0
T79	0	26	0	0
T81	0	32	0	0
T82	0	56	0	0
T100	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	126614	0	0
T13	11076	2573	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	250	0	0
T20	0	780	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1512	0	0
T48	0	2772	0	0
T78	0	1637	0	0
T79	0	877	0	0
T81	0	1680	0	0
T82	0	812	0	0
T100	0	714	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7496072	0	0
T13	11076	10605	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7876	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	417	0	0
T21	21341	0	0	0
T22	10161	0	0	0
T48	32402	11	0	0
T78	9197	15	0	0
T79	6020	13	0	0
T80	763	0	0	0
T88	0	12	0	0
T89	0	9	0	0
T90	0	21	0	0
T169	505	0	0	0
T170	675	0	0	0
T171	445	0	0	0
T172	516	0	0	0
T186	0	16	0	0
T218	0	14	0	0
T224	0	4	0	0
T226	0	33	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	97420	0	0
T13	11076	565	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	360	0	0
T20	0	1691	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	2091	0	0
T51	0	635	0	0
T81	0	3229	0	0
T82	0	1657	0	0
T100	0	442	0	0
T106	0	165	0	0
T107	0	1207	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1111	0	0
T13	11076	31	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	10	0	0
T20	0	15	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	24	0	0
T51	0	10	0	0
T81	0	16	0	0
T82	0	28	0	0
T100	0	14	0	0
T106	0	27	0	0
T107	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6969396	0	0
T13	11076	5547	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	5189	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	6971611	0	0
T13	11076	5547	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	5189	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1696	0	0
T13	11076	31	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	10	0	0
T20	0	15	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	24	0	0
T48	0	25	0	0
T78	0	25	0	0
T79	0	13	0	0
T81	0	16	0	0
T82	0	28	0	0
T100	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1687	0	0
T13	11076	31	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	10	0	0
T20	0	15	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	24	0	0
T48	0	25	0	0
T78	0	25	0	0
T79	0	13	0	0
T81	0	16	0	0
T82	0	28	0	0
T100	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1111	0	0
T13	11076	31	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	10	0	0
T20	0	15	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	24	0	0
T51	0	10	0	0
T81	0	16	0	0
T82	0	28	0	0
T100	0	14	0	0
T106	0	27	0	0
T107	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1111	0	0
T13	11076	31	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	10	0	0
T20	0	15	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	24	0	0
T51	0	10	0	0
T81	0	16	0	0
T82	0	28	0	0
T100	0	14	0	0
T106	0	27	0	0
T107	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	96198	0	0
T13	11076	533	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	349	0	0
T20	0	1674	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	2066	0	0
T51	0	625	0	0
T81	0	3207	0	0
T82	0	1626	0	0
T100	0	428	0	0
T106	0	138	0	0
T107	0	1187	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	969	0	0
T13	11076	30	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	9	0	0
T20	0	13	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	23	0	0
T51	0	10	0	0
T81	0	10	0	0
T82	0	25	0	0
T100	0	14	0	0
T106	0	27	0	0
T107	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T14,T15,T16

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T14
1	1	Covered	T14,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T222,T223,T116
1	0	Covered	T63,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T15,T16
1	-	Covered	T14,T15,T16

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T15,T16
0	1	Covered	T14,T15,T16
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T15,T16
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T15,T16
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T20,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T222,T223,T116
DetectSt	-	-	-	-	0	1	-	Covered	T14,T15,T16
DetectSt	-	-	-	-	0	0	-	Covered	T14,T15,T16
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T16
StableSt	-	-	-	-	-	-	0	Covered	T14,T15,T16
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	897	0	0
CntIncr_A	8198376	49242	0	0
CntNoWrap_A	8198376	7498558	0	0
DetectStDropOut_A	8198376	59	0	0
DetectedOut_A	8198376	15484	0	0
DetectedPulseOut_A	8198376	360	0	0
DisabledIdleSt_A	8198376	7086037	0	0
DisabledNoDetection_A	8198376	7087759	0	0
EnterDebounceSt_A	8198376	476	0	0
EnterDetectSt_A	8198376	423	0	0
EnterStableSt_A	8198376	360	0	0
PulseIsPulse_A	8198376	360	0	0
StayInStableSt	8198376	15075	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	308	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	897	0	0
T14	19815	2	0	0
T15	12035	11	0	0
T16	8305	2	0	0
T17	36108	2	0	0
T20	0	6	0	0
T21	0	6	0	0
T22	0	3	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	2	0	0
T57	503	0	0	0
T62	0	10	0	0
T81	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	49242	0	0
T14	19815	111	0	0
T15	12035	642	0	0
T16	8305	37	0	0
T17	36108	80	0	0
T20	0	192	0	0
T21	0	981	0	0
T22	0	121	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	47	0	0
T57	503	0	0	0
T62	0	355	0	0
T81	0	690	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7498558	0	0
T13	11076	10667	0	0
T14	19815	7026	0	0
T15	12035	11604	0	0
T16	8305	7894	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	59	0	0
T116	0	6	0	0
T212	0	2	0	0
T222	16365	5	0	0
T223	5510	2	0	0
T227	0	2	0	0
T228	0	3	0	0
T229	0	3	0	0
T230	0	2	0	0
T231	0	6	0	0
T232	0	5	0	0
T233	504	0	0	0
T234	494	0	0	0
T235	18625	0	0	0
T236	928	0	0	0
T237	422	0	0	0
T238	1738	0	0	0
T239	422	0	0	0
T240	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	15484	0	0
T14	19815	34	0	0
T15	12035	60	0	0
T16	8305	70	0	0
T17	36108	59	0	0
T20	0	123	0	0
T21	0	77	0	0
T22	0	62	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	89	0	0
T57	503	0	0	0
T62	0	66	0	0
T81	0	412	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	360	0	0
T14	19815	1	0	0
T15	12035	4	0	0
T16	8305	1	0	0
T17	36108	1	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1	0	0
T57	503	0	0	0
T62	0	5	0	0
T81	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7086037	0	0
T13	11076	10103	0	0
T14	19815	6617	0	0
T15	12035	8056	0	0
T16	8305	7537	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7087759	0	0
T13	11076	10104	0	0
T14	19815	6651	0	0
T15	12035	8056	0	0
T16	8305	7538	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	476	0	0
T14	19815	1	0	0
T15	12035	7	0	0
T16	8305	1	0	0
T17	36108	1	0	0
T20	0	4	0	0
T21	0	3	0	0
T22	0	2	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1	0	0
T57	503	0	0	0
T62	0	5	0	0
T81	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	423	0	0
T14	19815	1	0	0
T15	12035	4	0	0
T16	8305	1	0	0
T17	36108	1	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1	0	0
T57	503	0	0	0
T62	0	5	0	0
T81	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	360	0	0
T14	19815	1	0	0
T15	12035	4	0	0
T16	8305	1	0	0
T17	36108	1	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1	0	0
T57	503	0	0	0
T62	0	5	0	0
T81	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	360	0	0
T14	19815	1	0	0
T15	12035	4	0	0
T16	8305	1	0	0
T17	36108	1	0	0
T20	0	2	0	0
T21	0	3	0	0
T22	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1	0	0
T57	503	0	0	0
T62	0	5	0	0
T81	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	15075	0	0
T14	19815	33	0	0
T15	12035	56	0	0
T16	8305	69	0	0
T17	36108	58	0	0
T20	0	121	0	0
T21	0	73	0	0
T22	0	61	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	87	0	0
T57	503	0	0	0
T62	0	61	0	0
T81	0	400	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	308	0	0
T14	19815	1	0	0
T15	12035	4	0	0
T16	8305	1	0	0
T17	36108	1	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	0	1	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T43	0	1	0	0
T51	0	2	0	0
T57	503	0	0	0
T62	0	5	0	0