Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T16,T35
1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T16,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T35
1	0	Covered	T13,T16,T35
1	1	Covered	T13,T16,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T35
0	1	Covered	T16,T20,T78
1	0	Covered	T16,T20,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T35,T48
0	1	Covered	T13,T35,T48
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T35,T48
1	-	Covered	T13,T35,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T16,T35
0	1	Covered	T13,T16,T35
0	0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T35
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T35
IdleSt	0	-	-	-	-	-	-	Covered	T13,T16,T35
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T63,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T35
DetectSt	-	-	-	-	1	-	-	Covered	T16,T20,T78
DetectSt	-	-	-	-	0	1	-	Covered	T13,T35,T48
DetectSt	-	-	-	-	0	0	-	Covered	T13,T16,T35
StableSt	-	-	-	-	-	-	1	Covered	T13,T35,T48
StableSt	-	-	-	-	-	-	0	Covered	T13,T35,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	3363	0	0
CntIncr_A	8198376	121178	0	0
CntNoWrap_A	8198376	7496092	0	0
DetectStDropOut_A	8198376	491	0	0
DetectedOut_A	8198376	58966	0	0
DetectedPulseOut_A	8198376	897	0	0
DisabledIdleSt_A	8198376	7000204	0	0
DisabledNoDetection_A	8198376	7002460	0	0
EnterDebounceSt_A	8198376	1687	0	0
EnterDetectSt_A	8198376	1676	0	0
EnterStableSt_A	8198376	897	0	0
PulseIsPulse_A	8198376	897	0	0
StayInStableSt	8198376	57998	0	0
gen_high_event_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	825	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	3363	0	0
T13	11076	36	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	30	0	0
T20	0	42	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	40	0	0
T48	0	26	0	0
T78	0	50	0	0
T79	0	28	0	0
T81	0	18	0	0
T82	0	66	0	0
T100	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	121178	0	0
T13	11076	1548	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	712	0	0
T20	0	1123	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	1480	0	0
T48	0	1053	0	0
T78	0	1637	0	0
T79	0	947	0	0
T81	0	909	0	0
T82	0	1108	0	0
T100	0	1465	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7496092	0	0
T13	11076	10631	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	7866	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	491	0	0
T16	8305	5	0	0
T17	36108	0	0	0
T20	0	11	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T57	503	0	0	0
T65	2235	0	0	0
T78	0	15	0	0
T79	0	14	0	0
T82	0	15	0	0
T85	660	0	0	0
T86	504	0	0	0
T88	0	14	0	0
T89	0	21	0	0
T90	0	15	0	0
T100	0	14	0	0
T224	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	58966	0	0
T13	11076	330	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	238	0	0
T48	0	865	0	0
T51	0	2476	0	0
T67	0	3272	0	0
T81	0	168	0	0
T106	0	988	0	0
T107	0	112	0	0
T186	0	1530	0	0
T219	0	505	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	897	0	0
T13	11076	18	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	20	0	0
T48	0	13	0	0
T51	0	34	0	0
T67	0	17	0	0
T81	0	9	0	0
T106	0	26	0	0
T107	0	9	0	0
T186	0	13	0	0
T219	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7000204	0	0
T13	11076	5600	0	0
T14	19815	7028	0	0
T15	12035	11615	0	0
T16	8305	5344	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7002460	0	0
T13	11076	5600	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	5345	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1687	0	0
T13	11076	18	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	15	0	0
T20	0	21	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	20	0	0
T48	0	13	0	0
T78	0	25	0	0
T79	0	14	0	0
T81	0	9	0	0
T82	0	33	0	0
T100	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	1676	0	0
T13	11076	18	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	15	0	0
T20	0	21	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	20	0	0
T48	0	13	0	0
T78	0	25	0	0
T79	0	14	0	0
T81	0	9	0	0
T82	0	33	0	0
T100	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	897	0	0
T13	11076	18	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	20	0	0
T48	0	13	0	0
T51	0	34	0	0
T67	0	17	0	0
T81	0	9	0	0
T106	0	26	0	0
T107	0	9	0	0
T186	0	13	0	0
T219	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	897	0	0
T13	11076	18	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	20	0	0
T48	0	13	0	0
T51	0	34	0	0
T67	0	17	0	0
T81	0	9	0	0
T106	0	26	0	0
T107	0	9	0	0
T186	0	13	0	0
T219	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	57998	0	0
T13	11076	311	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	218	0	0
T48	0	849	0	0
T51	0	2442	0	0
T67	0	3253	0	0
T81	0	159	0	0
T106	0	961	0	0
T107	0	103	0	0
T186	0	1515	0	0
T219	0	493	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	825	0	0
T13	11076	17	0	0
T14	19815	0	0	0
T15	12035	0	0	0
T16	8305	0	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	20	0	0
T48	0	10	0	0
T51	0	34	0	0
T67	0	15	0	0
T81	0	9	0	0
T106	0	25	0	0
T107	0	9	0	0
T186	0	11	0	0
T219	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T41,T13,T30

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T30
1	1	Covered	T41,T13,T30

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T41,T13,T30	VC_COV_UNR
1	Covered	T13,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T41,T13,T30
1	Covered	T13,T14,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T41,T13,T14
1	1	Covered	T13,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T109,T241,T223
1	0	Covered	T63,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T15
1	-	Covered	T13,T14,T15

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7
DetectSt	168	Covered	T7
IdleSt	163	Covered	T7
StableSt	191	Covered	T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7
DebounceSt->IdleSt	163	Covered	T7
DetectSt->IdleSt	186	Covered	T7
DetectSt->StableSt	191	Covered	T7
IdleSt->DebounceSt	148	Covered	T7
StableSt->IdleSt	206	Covered	T7

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
0	0	Excluded	T41,T13,T30	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T41,T13,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T63,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T17,T44
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T109,T241,T223
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	0	0	-	Covered	T13,T14,T15
StableSt	-	-	-	-	-	-	1	Covered	T13,T14,T15
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T41,T13,T30
0	Covered	T41,T13,T30

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8198376	783	0	0
CntIncr_A	8198376	45036	0	0
CntNoWrap_A	8198376	7498672	0	0
DetectStDropOut_A	8198376	54	0	0
DetectedOut_A	8198376	12862	0	0
DetectedPulseOut_A	8198376	318	0	0
DisabledIdleSt_A	8198376	7115688	0	0
DisabledNoDetection_A	8198376	7117438	0	0
EnterDebounceSt_A	8198376	407	0	0
EnterDetectSt_A	8198376	376	0	0
EnterStableSt_A	8198376	318	0	0
PulseIsPulse_A	8198376	318	0	0
StayInStableSt	8198376	12526	0	0
gen_high_level_sva.HighLevelEvent_A	8198376	7501877	0	0
gen_not_sticky_sva.StableStDropOut_A	8198376	298	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	783	0	0
T13	11076	2	0	0
T14	19815	2	0	0
T15	12035	3	0	0
T16	8305	0	0	0
T17	0	11	0	0
T22	0	2	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	11	0	0
T48	0	2	0	0
T62	0	2	0	0
T106	0	2	0	0
T242	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	45036	0	0
T13	11076	57	0	0
T14	19815	74	0	0
T15	12035	189	0	0
T16	8305	0	0	0
T17	0	564	0	0
T22	0	117	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	426	0	0
T48	0	51	0	0
T62	0	79	0	0
T106	0	65	0	0
T242	0	1651	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7498672	0	0
T13	11076	10665	0	0
T14	19815	7026	0	0
T15	12035	11612	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	54	0	0
T98	0	2	0	0
T109	24732	2	0	0
T116	0	4	0	0
T133	6332	0	0	0
T149	0	2	0	0
T154	409	0	0	0
T155	403	0	0	0
T156	836	0	0	0
T212	0	4	0	0
T219	18484	0	0	0
T223	0	1	0	0
T241	0	7	0	0
T243	0	1	0	0
T244	0	11	0	0
T245	0	2	0	0
T246	513	0	0	0
T247	404	0	0	0
T248	158538	0	0	0
T249	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	12862	0	0
T13	11076	90	0	0
T14	19815	72	0	0
T15	12035	5	0	0
T16	8305	0	0	0
T17	0	191	0	0
T22	0	15	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	53	0	0
T48	0	38	0	0
T62	0	5	0	0
T106	0	49	0	0
T242	0	864	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	318	0	0
T13	11076	1	0	0
T14	19815	1	0	0
T15	12035	1	0	0
T16	8305	0	0	0
T17	0	5	0	0
T22	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	5	0	0
T48	0	1	0	0
T62	0	1	0	0
T106	0	1	0	0
T242	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7115688	0	0
T13	11076	10338	0	0
T14	19815	6617	0	0
T15	12035	8056	0	0
T16	8305	7896	0	0
T30	405	4	0	0
T31	502	101	0	0
T32	665	264	0	0
T33	497	96	0	0
T34	422	21	0	0
T41	2031	829	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7117438	0	0
T13	11076	10339	0	0
T14	19815	6651	0	0
T15	12035	8056	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	407	0	0
T13	11076	1	0	0
T14	19815	1	0	0
T15	12035	2	0	0
T16	8305	0	0	0
T17	0	6	0	0
T22	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	6	0	0
T48	0	1	0	0
T62	0	1	0	0
T106	0	1	0	0
T242	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	376	0	0
T13	11076	1	0	0
T14	19815	1	0	0
T15	12035	1	0	0
T16	8305	0	0	0
T17	0	5	0	0
T22	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	5	0	0
T48	0	1	0	0
T62	0	1	0	0
T106	0	1	0	0
T242	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	318	0	0
T13	11076	1	0	0
T14	19815	1	0	0
T15	12035	1	0	0
T16	8305	0	0	0
T17	0	5	0	0
T22	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	5	0	0
T48	0	1	0	0
T62	0	1	0	0
T106	0	1	0	0
T242	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	318	0	0
T13	11076	1	0	0
T14	19815	1	0	0
T15	12035	1	0	0
T16	8305	0	0	0
T17	0	5	0	0
T22	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	5	0	0
T48	0	1	0	0
T62	0	1	0	0
T106	0	1	0	0
T242	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	12526	0	0
T13	11076	89	0	0
T14	19815	71	0	0
T15	12035	4	0	0
T16	8305	0	0	0
T17	0	186	0	0
T22	0	14	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	48	0	0
T48	0	36	0	0
T62	0	4	0	0
T106	0	47	0	0
T242	0	851	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	7501877	0	0
T13	11076	10669	0	0
T14	19815	7063	0	0
T15	12035	11619	0	0
T16	8305	7898	0	0
T30	405	5	0	0
T31	502	102	0	0
T32	665	265	0	0
T33	497	97	0	0
T34	422	22	0	0
T41	2031	831	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8198376	298	0	0
T13	11076	1	0	0
T14	19815	1	0	0
T15	12035	1	0	0
T16	8305	0	0	0
T17	0	5	0	0
T22	0	1	0	0
T30	405	0	0	0
T31	502	0	0	0
T32	665	0	0	0
T33	497	0	0	0
T34	422	0	0	0
T35	10465	0	0	0
T44	0	5	0	0
T62	0	1	0	0
T91	0	2	0	0
T221	0	5	0	0
T242	0	13	0	0