Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1088100268	12106	0	0
auto_block_debounce_ctl_rd_A	1088100268	1821	0	0
auto_block_out_ctl_rd_A	1088100268	2325	0	0
com_det_ctl_0_rd_A	1088100268	3994	0	0
com_det_ctl_1_rd_A	1088100268	3668	0	0
com_det_ctl_2_rd_A	1088100268	3658	0	0
com_det_ctl_3_rd_A	1088100268	3934	0	0
com_out_ctl_0_rd_A	1088100268	4045	0	0
com_out_ctl_1_rd_A	1088100268	4304	0	0
com_out_ctl_2_rd_A	1088100268	4405	0	0
com_out_ctl_3_rd_A	1088100268	4301	0	0
com_pre_det_ctl_0_rd_A	1088100268	1520	0	0
com_pre_det_ctl_1_rd_A	1088100268	1651	0	0
com_pre_det_ctl_2_rd_A	1088100268	1486	0	0
com_pre_det_ctl_3_rd_A	1088100268	1603	0	0
com_pre_sel_ctl_0_rd_A	1088100268	4472	0	0
com_pre_sel_ctl_1_rd_A	1088100268	4297	0	0
com_pre_sel_ctl_2_rd_A	1088100268	4490	0	0
com_pre_sel_ctl_3_rd_A	1088100268	4479	0	0
com_sel_ctl_0_rd_A	1088100268	4179	0	0
com_sel_ctl_1_rd_A	1088100268	4443	0	0
com_sel_ctl_2_rd_A	1088100268	4244	0	0
com_sel_ctl_3_rd_A	1088100268	4414	0	0
ec_rst_ctl_rd_A	1088100268	2235	0	0
intr_enable_rd_A	1088100268	1987	0	0
key_intr_ctl_rd_A	1088100268	3766	0	0
key_intr_debounce_ctl_rd_A	1088100268	1474	0	0
key_invert_ctl_rd_A	1088100268	4860	0	0
pin_allowed_ctl_rd_A	1088100268	5649	0	0
pin_out_ctl_rd_A	1088100268	4214	0	0
pin_out_value_rd_A	1088100268	4134	0	0
regwen_rd_A	1088100268	1525	0	0
ulp_ac_debounce_ctl_rd_A	1088100268	1547	0	0
ulp_ctl_rd_A	1088100268	1686	0	0
ulp_lid_debounce_ctl_rd_A	1088100268	1709	0	0
ulp_pwrb_debounce_ctl_rd_A	1088100268	1577	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	12106	0	0
T1	87998	8	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	3	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	101442	0	0	0
T37	0	5	0	0
T40	0	5	0	0
T49	0	5	0	0
T250	0	1074	0	0
T254	0	248	0	0
T255	0	203	0	0
T261	0	3	0	0
T276	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1821	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	49	0	0
T5	0	10	0	0
T8	58415	8	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	9	0	0
T37	0	60	0	0
T40	0	48	0	0
T250	0	18	0	0
T277	0	461	0	0
T278	0	6	0	0
T279	0	59	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	2325	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	90	0	0
T5	0	21	0	0
T8	58415	9	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	3	0	0
T37	0	117	0	0
T40	0	111	0	0
T250	0	28	0	0
T277	0	393	0	0
T278	0	9	0	0
T280	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	3994	0	0
T4	111698	45	0	0
T5	50704	0	0	0
T6	143739	0	0	0
T9	962982	0	0	0
T10	791523	0	0	0
T29	101442	1	0	0
T37	0	27	0	0
T38	0	1	0	0
T39	59115	0	0	0
T40	0	27	0	0
T49	211150	0	0	0
T250	66063	30	0	0
T277	0	427	0	0
T278	0	59	0	0
T279	0	54	0	0
T280	0	2	0	0
T281	199884	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	3668	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	37	0	0
T5	0	11	0	0
T8	58415	5	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	1	0	0
T37	0	39	0	0
T40	0	41	0	0
T250	0	5	0	0
T277	0	393	0	0
T278	0	54	0	0
T280	0	4	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	3658	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	26	0	0
T5	0	5	0	0
T8	58415	6	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	2	0	0
T37	0	31	0	0
T40	0	31	0	0
T250	0	7	0	0
T277	0	427	0	0
T278	0	30	0	0
T279	0	23	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	3934	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	45	0	0
T5	0	10	0	0
T8	58415	2	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	2	0	0
T37	0	58	0	0
T40	0	23	0	0
T250	0	22	0	0
T277	0	441	0	0
T278	0	50	0	0
T280	0	7	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4045	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	63	0	0
T5	0	18	0	0
T8	58415	4	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	79	0	0
T38	0	5	0	0
T40	0	119	0	0
T250	0	19	0	0
T277	0	431	0	0
T278	0	47	0	0
T280	0	25	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4304	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	76	0	0
T5	0	33	0	0
T8	58415	3	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	93	0	0
T38	0	13	0	0
T40	0	143	0	0
T250	0	28	0	0
T277	0	445	0	0
T278	0	29	0	0
T280	0	6	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4405	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	77	0	0
T5	0	11	0	0
T8	58415	4	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	101	0	0
T38	0	9	0	0
T40	0	102	0	0
T250	0	3	0	0
T277	0	458	0	0
T278	0	33	0	0
T280	0	12	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4301	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	59	0	0
T5	0	19	0	0
T8	58415	4	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	9	0	0
T37	0	139	0	0
T38	0	4	0	0
T40	0	120	0	0
T250	0	17	0	0
T277	0	417	0	0
T278	0	48	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1520	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	40	0	0
T5	0	8	0	0
T8	58415	4	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	5	0	0
T37	0	53	0	0
T38	0	4	0	0
T40	0	50	0	0
T250	0	20	0	0
T277	0	440	0	0
T278	0	45	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1651	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	47	0	0
T5	0	13	0	0
T8	58415	2	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	1	0	0
T37	0	48	0	0
T40	0	32	0	0
T250	0	50	0	0
T277	0	422	0	0
T278	0	25	0	0
T279	0	79	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1486	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	42	0	0
T5	0	5	0	0
T8	58415	3	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	22	0	0
T38	0	4	0	0
T40	0	35	0	0
T250	0	9	0	0
T277	0	460	0	0
T278	0	24	0	0
T280	0	6	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1603	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	37	0	0
T5	0	8	0	0
T8	58415	4	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	46	0	0
T38	0	5	0	0
T40	0	52	0	0
T250	0	7	0	0
T277	0	378	0	0
T278	0	55	0	0
T280	0	2	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4472	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	85	0	0
T5	0	45	0	0
T8	58415	3	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	5	0	0
T37	0	122	0	0
T38	0	10	0	0
T40	0	146	0	0
T250	0	14	0	0
T277	0	390	0	0
T278	0	21	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4297	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	98	0	0
T5	0	1	0	0
T8	58415	1	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	6	0	0
T37	0	108	0	0
T38	0	7	0	0
T40	0	138	0	0
T250	0	21	0	0
T277	0	419	0	0
T278	0	99	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4490	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	136	0	0
T5	0	24	0	0
T8	58415	7	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	2	0	0
T37	0	70	0	0
T40	0	180	0	0
T250	0	4	0	0
T277	0	461	0	0
T278	0	39	0	0
T280	0	10	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4479	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	140	0	0
T5	0	9	0	0
T8	58415	3	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	5	0	0
T37	0	70	0	0
T38	0	14	0	0
T40	0	109	0	0
T250	0	29	0	0
T277	0	437	0	0
T278	0	27	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4179	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	115	0	0
T5	0	19	0	0
T8	58415	9	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	3	0	0
T37	0	81	0	0
T38	0	6	0	0
T40	0	89	0	0
T250	0	33	0	0
T277	0	433	0	0
T278	0	87	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4443	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	96	0	0
T5	0	19	0	0
T8	58415	1	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	5	0	0
T37	0	64	0	0
T38	0	7	0	0
T40	0	90	0	0
T250	0	14	0	0
T277	0	444	0	0
T278	0	27	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4244	0	0
T4	111698	85	0	0
T5	50704	29	0	0
T6	143739	0	0	0
T9	962982	0	0	0
T10	791523	0	0	0
T11	255931	0	0	0
T37	0	147	0	0
T38	0	3	0	0
T39	59115	0	0	0
T40	0	123	0	0
T49	211150	0	0	0
T250	66063	29	0	0
T277	0	372	0	0
T278	0	58	0	0
T279	0	59	0	0
T280	0	4	0	0
T281	199884	0	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4414	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	109	0	0
T5	0	9	0	0
T8	58415	4	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	1	0	0
T37	0	88	0	0
T38	0	4	0	0
T40	0	112	0	0
T250	0	29	0	0
T277	0	395	0	0
T278	0	30	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	2235	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	33	0	0
T5	0	1	0	0
T8	58415	5	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	1	0	0
T37	0	31	0	0
T38	0	6	0	0
T40	0	41	0	0
T250	0	2	0	0
T277	0	384	0	0
T278	0	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1987	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	41	0	0
T5	0	8	0	0
T8	58415	2	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	23	0	0
T29	0	1	0	0
T37	0	38	0	0
T40	0	29	0	0
T250	0	9	0	0
T281	0	3	0	0
T282	0	16	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	3766	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	249	0	0
T5	0	78	0	0
T8	58415	6	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	318	0	0
T38	0	33	0	0
T40	0	322	0	0
T250	0	4	0	0
T277	0	462	0	0
T278	0	44	0	0
T280	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1474	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	40	0	0
T5	0	4	0	0
T8	58415	5	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	6	0	0
T37	0	43	0	0
T38	0	5	0	0
T40	0	37	0	0
T250	0	13	0	0
T277	0	374	0	0
T278	0	34	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4860	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	236	0	0
T5	0	5	0	0
T8	58415	5	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	305	0	0
T38	0	4	0	0
T40	0	173	0	0
T250	0	11	0	0
T277	0	375	0	0
T278	0	32	0	0
T280	0	28	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	5649	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	336	0	0
T5	0	77	0	0
T8	58415	2	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	1	0	0
T37	0	358	0	0
T38	0	51	0	0
T40	0	222	0	0
T250	0	19	0	0
T277	0	413	0	0
T278	0	41	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4214	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	175	0	0
T5	0	24	0	0
T8	58415	2	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	119	0	0
T38	0	19	0	0
T40	0	144	0	0
T250	0	19	0	0
T277	0	423	0	0
T278	0	6	0	0
T279	0	46	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	4134	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	98	0	0
T5	0	61	0	0
T8	58415	9	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	4	0	0
T37	0	149	0	0
T38	0	3	0	0
T40	0	185	0	0
T250	0	12	0	0
T277	0	457	0	0
T278	0	57	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1525	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	29	0	0
T5	0	9	0	0
T8	58415	9	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T37	0	38	0	0
T40	0	29	0	0
T250	0	8	0	0
T277	0	434	0	0
T278	0	44	0	0
T279	0	9	0	0
T280	0	4	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1547	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	23	0	0
T5	0	5	0	0
T8	58415	6	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	2	0	0
T37	0	41	0	0
T38	0	5	0	0
T40	0	36	0	0
T250	0	34	0	0
T277	0	398	0	0
T278	0	5	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1686	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	44	0	0
T5	0	3	0	0
T8	58415	9	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	7	0	0
T37	0	41	0	0
T40	0	69	0	0
T250	0	5	0	0
T277	0	393	0	0
T278	0	57	0	0
T280	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1709	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	27	0	0
T5	0	10	0	0
T8	58415	1	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	2	0	0
T37	0	41	0	0
T38	0	8	0	0
T40	0	41	0	0
T250	0	30	0	0
T277	0	455	0	0
T278	0	29	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1088100268	1577	0	0
T1	87998	0	0	0
T2	146096	0	0	0
T3	47041	0	0	0
T4	0	57	0	0
T5	0	7	0	0
T8	58415	7	0	0
T23	99191	0	0	0
T24	99164	0	0	0
T25	199262	0	0	0
T26	192958	0	0	0
T27	187506	0	0	0
T28	50910	0	0	0
T29	0	2	0	0
T37	0	44	0	0
T40	0	34	0	0
T250	0	9	0	0
T277	0	396	0	0
T278	0	49	0	0
T280	0	11	0	0