Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1927

1

T14

28

T15

5

T16

17

auto[1]

600

1

T14

8

T15

2

T17

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1970

1

T14

32

T16

10

T17

21

auto[1]

557

1

T14

4

T15

7

T16

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2004

1

T14

29

T15

5

T16

10

auto[1]

523

1

T14

7

T15

2

T16

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1883

1

T14

21

T15

7

T17

24

auto[1]

644

1

T14

15

T16

17

T18

10

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2329

1

T14

25

T15

7

T16

17

auto[1]

198

1

T14

11

T17

1

T51

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2337

1

T14

28

T15

7

T16

17

auto[1]

190

1

T14

8

T17

3

T50

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2316

1

T14

36

T15

7

T16

17

auto[1]

211

1

T50

6

T68

19

T234

10

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2360

1

T14

32

T15

7

T16

17

auto[1]

167

1

T14

4

T17

2

T50

6

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2408

1

T14

36

T15

7

T16

17

auto[1]

119

1

T17

3

T62

3

T79

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1834

1

T14

32

T15

3

T16

14

auto[1]

693

1

T14

4

T15

4

T16

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	976	1			T15	7		T16	17		T18	12
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	79	1			T14	7		T51	2		T235	14
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	37	1			T62	3		T226	1		T143	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T17	1		T327	1		T323	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	49	1			T50	4		T235	8		T227	7
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	26	1			T14	4		T198	4		T321	7
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T236	1		T328	3		-	-
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T329	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	98	1			T50	2		T68	11		T234	8
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	26	1			T326	2		T198	20		T330	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	14	1			T331	2		T324	9		T332	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T333	4		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	23	1			T68	8		T326	4		T334	4
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	4	1			T335	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	78	1			T14	8		T17	3		T50	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	17	1			T235	4		T77	2		T336	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	19	1			T77	4		T337	8		T330	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T234	1		T333	3		T338	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	19	1			T240	1		T337	7		T339	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T340	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T341	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T337	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	17	1			T198	6		T331	3		T322	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T234	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

140

1

T17

3

T22

6

T23

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

104

1

T22

13

T73

7

T173

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

99

1

T89

7

T68

11

T73

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

144

1

T16

10

T22

10

T342

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

51

1

T14

8

T70

3

T317

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

88

1

T23

7

T343

3

T318

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T331

3

T344

3

T345

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

75

1

T50

4

T234

1

T346

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T48

6

T347

4

T236

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

103

1

T23

8

T50

2

T45

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T41

2

T45

1

T54

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

74

1

T14

7

T342

5

T348

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T54

4

T83

1

T315

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

11

1

T18

4

T50

2

T103

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T319

1

T86

1

T349

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

102

1

T15

3

T17

1

T50

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

48

1

T348

2

T350

3

T102

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

98

1

T14

4

T54

6

T111

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T15

2

T18

2

T316

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T18

4

T48

8

T72

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

48

1

T62

3

T72

4

T45

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T89

4

T235

7

T351

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T100

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

28

1

T51

2

T41

1

T173

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T41

1

T342

2

T316

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T15

2

T347

2

T343

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T70

1

T350

3

T253

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

19

1

T16

4

T173

1

T343

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T89

1

T111

2

T200

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T16

3

T235

7

T101

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T18

2

T89

1

T159

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded