Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T40

10

T94

12

T15

11

auto[1]

1132

1

T40

10

T94

8

T15

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

561

1

T40

5

T94

5

T15

3

from_0to1

552

1

T40

5

T94

5

T15

2

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T40

6

T94

10

T15

14

auto[1]

1142

1

T40

14

T94

10

T15

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T40

13

T94

9

T15

11

auto[1]

1106

1

T40

7

T94

11

T15

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T40

1

T94

1

T15

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T15

1

T230

1

T41

3

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T40

1

T94

2

T42

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T41

1

T44

4

T53

3

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T40

1

T18

1

T19

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T94

2

T59

1

T42

1

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T40

1

T94

2

T18

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T94

1

T19

2

T230

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T94

1

T18

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T40

1

T19

1

T207

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T40

2

T94

1

T19

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T18

2

T19

1

T207

2

auto[1]

from_0to1

auto[0]

auto[0]

85

1

T15

1

T18

1

T230

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T40

2

T207

2

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T40

1

T15

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T18

1

T19

1

T230

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T40

10

T94

7

T15

7

auto[1]

1125

1

T40

10

T94

13

T15

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T40

5

T94

7

T15

6

from_0to1

545

1

T40

5

T94

7

T15

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T40

10

T94

7

T15

12

auto[1]

1146

1

T40

10

T94

13

T15

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1125

1

T40

11

T94

8

T15

10

auto[1]

1142

1

T40

9

T94

12

T15

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T40

1

T94

1

T15

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T40

1

T94

1

T15

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T94

1

T18

1

T207

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T40

1

T94

1

T18

3

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T40

1

T15

1

T18

2

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T19

1

T230

1

T41

2

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T40

1

T207

1

T230

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T40

1

T94

2

T15

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T19

3

T42

1

T44

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T94

1

T15

3

T19

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T40

1

T94

2

T15

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T40

1

T18

1

T19

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T94

1

T15

2

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T94

2

T207

1

T230

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T40

1

T94

1

T15

2

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T40

1

T94

1

T15

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1137

1

T40

9

T94

11

T15

8

auto[1]

1130

1

T40

11

T94

9

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

544

1

T40

3

T94

4

T15

6

from_0to1

553

1

T40

4

T94

5

T15

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T40

12

T94

12

T15

13

auto[1]

1105

1

T40

8

T94

8

T15

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T40

11

T94

8

T15

11

auto[1]

1136

1

T40

9

T94

12

T15

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T40

1

T15

1

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T94

1

T15

1

T18

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T19

1

T207

2

T230

3

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T94

1

T15

1

T207

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T18

2

T19

1

T207

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T40

2

T94

1

T15

2

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T94

1

T230

1

T59

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T94

1

T18

1

T19

1

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T40

1

T15

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T94

1

T18

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T94

1

T15

1

T18

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T40

1

T15

1

T18

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T94

1

T15

1

T18

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T40

1

T94

1

T18

1

auto[1]

from_0to1

auto[1]

auto[0]

71

1

T40

1

T15

2

T207

2

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T15

1

T207

1

T44

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T40

12

T94

10

T15

11

auto[1]

1147

1

T40

8

T94

10

T15

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

534

1

T40

4

T94

4

T15

5

from_0to1

544

1

T40

4

T94

4

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T40

12

T94

12

T15

13

auto[1]

1102

1

T40

8

T94

8

T15

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T40

11

T94

14

T15

12

auto[1]

1139

1

T40

9

T94

6

T15

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T40

1

T94

1

T15

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T40

2

T94

1

T15

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T94

2

T15

2

T19

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T230

1

T41

1

T42

3

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T40

2

T94

2

T15

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T15

1

T18

1

T19

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T18

2

T230

2

T41

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T18

1

T19

2

T41

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T19

1

T207

1

T230

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T40

1

T207

3

T230

2

auto[1]

from_1to0

auto[1]

auto[0]

77

1

T18

1

T19

1

T230

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T18

1

T19

1

T42

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T94

1

T41

1

T42

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T15

1

T230

1

T41

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T40

2

T19

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T94

1

T15

2

T207

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T40

14

T94

10

T15

13

auto[1]

1127

1

T40

6

T94

10

T15

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

571

1

T40

7

T94

4

T15

5

from_0to1

579

1

T40

6

T94

3

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T40

11

T94

15

T15

6

auto[1]

1114

1

T40

9

T94

5

T15

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T40

7

T94

12

T15

9

auto[1]

1117

1

T40

13

T94

8

T15

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

80

1

T40

1

T94

2

T207

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T40

2

T230

2

T41

2

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T15

1

T18

1

T19

2

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T40

3

T15

2

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T40

1

T94

1

T19

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T40

1

T94

1

T15

1

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T15

2

T18

2

T19

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T40

1

T18

1

T207

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T207

1

T230

2

T41

2

auto[1]

from_1to0

auto[0]

auto[1]

76

1

T40

1

T94

1

T15

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T19

1

T44

2

T116

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T94

1

T15

1

T18

2

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T40

3

T41

3

T42

2

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T94

1

T18

1

T19

1

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T15

2

T207

2

T230

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T18

1

T59

1

T42

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1150

1

T40

9

T94

12

T15

11

auto[1]

1117

1

T40

11

T94

8

T15

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T40

6

T94

4

T15

6

from_0to1

529

1

T40

5

T94

5

T15

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1149

1

T40

13

T94

11

T15

11

auto[1]

1118

1

T40

7

T94

9

T15

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T40

6

T94

9

T15

8

auto[1]

1128

1

T40

14

T94

11

T15

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T94

1

T15

1

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T40

3

T94

1

T15

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T40

1

T94

1

T15

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T18

1

T41

2

T59

1

auto[0]

from_0to1

auto[0]

auto[0]

56

1

T15

2

T18

1

T230

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T40

1

T94

2

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T18

1

T19

1

T230

1

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T40

2

T94

2

T18

1

auto[1]

from_1to0

auto[0]

auto[0]

79

1

T40

1

T18

2

T207

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T40

1

T19

1

T207

1

auto[1]

from_1to0

auto[1]

auto[0]

52

1

T94

1

T15

2

T19

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T19

2

T207

1

T230

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T19

1

T41

2

T42

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T94

1

T15

3

T207

2

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T40

1

T18

1

T207

3

auto[1]

from_0to1

auto[1]

auto[1]

79

1

T40

1

T15

1

T19

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T40

8

T94

10

T15

11

auto[1]

1212

1

T40

12

T94

10

T15

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T40

2

T94

5

T15

7

from_0to1

546

1

T40

2

T94

5

T15

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T40

12

T94

8

T15

8

auto[1]

1160

1

T40

8

T94

12

T15

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1136

1

T40

8

T94

8

T15

12

auto[1]

1131

1

T40

12

T94

12

T15

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T15

2

T19

2

T207

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T94

1

T15

1

T19

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T94

1

T15

2

T18

1

auto[0]

from_1to0

auto[1]

auto[1]

52

1

T40

1

T94

1

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T94

2

T207

2

T41

2

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T18

3

T19

1

T41

4

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T15

1

T207

1

T230

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T40

1

T94

1

T15

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T18

1

T19

1

T207

1

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T40

1

T94

2

T18

2

auto[1]

from_1to0

auto[1]

auto[0]

85

1

T15

2

T19

1

T41

2

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T19

1

T230

2

T41

3

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T15

1

T18

1

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T40

1

T15

1

T41

2

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T15

1

T18

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

80

1

T94

2

T15

1

T59

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T40

13

T94

11

T15

8

auto[1]

1141

1

T40

7

T94

9

T15

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

566

1

T40

5

T94

4

T15

5

from_0to1

563

1

T40

4

T94

4

T15

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1106

1

T40

6

T94

15

T15

10

auto[1]

1161

1

T40

14

T94

5

T15

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T40

14

T94

10

T15

14

auto[1]

1114

1

T40

6

T94

10

T15

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T40

1

T18

1

T41

2

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T94

1

T230

3

T59

2

auto[0]

from_1to0

auto[1]

auto[0]

83

1

T40

3

T94

1

T15

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T15

1

T18

1

T19

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T94

1

T15

1

T18

3

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T94

1

T15

1

T18

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T40

1

T94

1

T15

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T18

1

T19

1

T207

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T40

1

T94

2

T15

2

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T19

1

T230

1

T41

1

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T15

1

T18

1

T19

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T18

1

T207

1

T230

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T40

1

T230

1

T41

2

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T94

1

T15

1

T19

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T15

1

T230

2

T59

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T40

2

T207

1

T230

1