Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142855	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

110350

1

T7

11

T1

301

T2

67

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	130712	1			T7	20		T1	778		T2	83
values[0x0]	61002	1			T7	11		T1	202		T2	39
values[0x1]	61491	1			T7	8		T1	203		T2	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116322	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

136883

1

T7

17

T1

553

T2

87

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	857	1			T1	5		T24	13		T3	1
valid_sources[0x01]	810	1			T7	1		T1	2		T24	23
valid_sources[0x02]	1124	1			T1	8		T24	14		T3	2
valid_sources[0x03]	741	1			T1	5		T24	19		T3	2
valid_sources[0x04]	971	1			T1	8		T24	13		T3	1
valid_sources[0x05]	783	1			T1	4		T24	17		T4	11
valid_sources[0x06]	890	1			T1	4		T2	1		T24	18
valid_sources[0x07]	925	1			T1	1		T24	19		T3	1
valid_sources[0x08]	858	1			T1	3		T24	9		T4	7
valid_sources[0x09]	823	1			T1	6		T2	1		T24	12
valid_sources[0x0a]	824	1			T1	3		T24	6		T3	1
valid_sources[0x0b]	813	1			T1	2		T24	18		T3	2
valid_sources[0x0c]	935	1			T1	5		T2	4		T24	13
valid_sources[0x0d]	997	1			T1	7		T2	1		T24	25
valid_sources[0x0e]	1374	1			T1	5		T2	6		T24	17
valid_sources[0x0f]	1560	1			T1	4		T24	23		T3	1
valid_sources[0x10]	835	1			T1	6		T24	31		T4	15
valid_sources[0x11]	715	1			T1	3		T2	5		T24	27
valid_sources[0x12]	753	1			T1	7		T24	16		T3	1
valid_sources[0x13]	1178	1			T1	4		T24	11		T3	1
valid_sources[0x14]	816	1			T1	7		T24	12		T4	8
valid_sources[0x15]	862	1			T1	3		T24	16		T3	4
valid_sources[0x16]	1917	1			T1	5		T24	26		T3	2
valid_sources[0x17]	2188	1			T1	6		T24	31		T3	2
valid_sources[0x18]	1181	1			T1	5		T24	20		T3	3
valid_sources[0x19]	784	1			T1	4		T2	3		T24	21
valid_sources[0x1a]	862	1			T1	7		T24	19		T4	16
valid_sources[0x1b]	852	1			T1	3		T24	13		T3	2
valid_sources[0x1c]	853	1			T1	4		T24	14		T4	21
valid_sources[0x1d]	874	1			T7	1		T1	6		T2	1
valid_sources[0x1e]	810	1			T1	3		T2	1		T24	15
valid_sources[0x1f]	941	1			T1	2		T24	27		T4	8
valid_sources[0x20]	1126	1			T1	5		T24	10		T3	3
valid_sources[0x21]	1301	1			T1	2		T2	3		T24	20
valid_sources[0x22]	849	1			T1	1		T2	1		T24	19
valid_sources[0x23]	803	1			T1	3		T24	12		T4	10
valid_sources[0x24]	1002	1			T1	5		T24	24		T3	3
valid_sources[0x25]	938	1			T1	3		T2	1		T24	21
valid_sources[0x26]	817	1			T1	1		T24	5		T3	1
valid_sources[0x27]	766	1			T1	4		T2	4		T24	19
valid_sources[0x28]	854	1			T7	1		T1	5		T2	1
valid_sources[0x29]	1665	1			T1	5		T24	23		T3	1
valid_sources[0x2a]	809	1			T1	5		T24	18		T3	2
valid_sources[0x2b]	849	1			T1	7		T24	20		T3	3
valid_sources[0x2c]	945	1			T1	5		T2	1		T24	28
valid_sources[0x2d]	1190	1			T1	8		T24	15		T4	17
valid_sources[0x2e]	1131	1			T1	5		T24	18		T3	2
valid_sources[0x2f]	1209	1			T7	2		T1	2		T24	13
valid_sources[0x30]	850	1			T1	3		T24	22		T3	1
valid_sources[0x31]	1309	1			T1	2		T2	2		T24	20
valid_sources[0x32]	908	1			T1	3		T2	2		T24	19
valid_sources[0x33]	799	1			T1	7		T2	1		T24	16
valid_sources[0x34]	866	1			T1	4		T24	28		T3	2
valid_sources[0x35]	701	1			T1	4		T24	18		T3	1
valid_sources[0x36]	1488	1			T1	4		T2	1		T24	19
valid_sources[0x37]	1106	1			T7	1		T1	6		T24	17
valid_sources[0x38]	1002	1			T1	4		T24	9		T3	3
valid_sources[0x39]	811	1			T1	4		T24	16		T3	2
valid_sources[0x3a]	771	1			T1	5		T2	1		T24	22
valid_sources[0x3b]	733	1			T1	3		T24	14		T3	5
valid_sources[0x3c]	937	1			T1	6		T24	16		T3	1
valid_sources[0x3d]	1582	1			T1	7		T2	2		T24	12
valid_sources[0x3e]	1055	1			T1	5		T24	23		T4	7
valid_sources[0x3f]	804	1			T1	6		T24	24		T3	1
valid_sources[0x40]	837	1			T1	5		T24	9		T3	1
valid_sources[0x41]	1237	1			T7	1		T1	6		T24	24
valid_sources[0x42]	887	1			T1	3		T24	17		T3	1
valid_sources[0x43]	961	1			T2	1		T24	18		T3	2
valid_sources[0x44]	1711	1			T7	1		T1	4		T24	19
valid_sources[0x45]	1344	1			T1	6		T24	19		T3	2
valid_sources[0x46]	1724	1			T7	1		T1	2		T24	17
valid_sources[0x47]	860	1			T1	4		T24	27		T3	4
valid_sources[0x48]	836	1			T1	4		T2	3		T24	16
valid_sources[0x49]	832	1			T7	2		T1	3		T2	2
valid_sources[0x4a]	935	1			T1	6		T24	18		T3	3
valid_sources[0x4b]	783	1			T1	3		T24	26		T3	3
valid_sources[0x4c]	716	1			T1	6		T2	2		T24	13
valid_sources[0x4d]	863	1			T1	3		T24	23		T3	1
valid_sources[0x4e]	808	1			T1	3		T24	9		T3	2
valid_sources[0x4f]	1400	1			T1	2		T24	13		T3	4
valid_sources[0x50]	854	1			T7	2		T1	3		T24	13
valid_sources[0x51]	906	1			T1	4		T24	16		T4	17
valid_sources[0x52]	1560	1			T1	8		T2	2		T24	13
valid_sources[0x53]	901	1			T1	3		T2	2		T24	25
valid_sources[0x54]	955	1			T1	2		T24	18		T4	17
valid_sources[0x55]	1522	1			T1	3		T2	1		T24	13
valid_sources[0x56]	787	1			T7	1		T1	7		T24	33
valid_sources[0x57]	761	1			T1	4		T2	1		T24	16
valid_sources[0x58]	805	1			T1	7		T24	17		T3	2
valid_sources[0x59]	847	1			T1	2		T24	20		T3	2
valid_sources[0x5a]	820	1			T1	4		T2	4		T24	21
valid_sources[0x5b]	860	1			T7	1		T1	3		T24	18
valid_sources[0x5c]	770	1			T7	1		T24	21		T3	2
valid_sources[0x5d]	930	1			T1	3		T24	17		T3	5
valid_sources[0x5e]	1138	1			T1	6		T24	23		T3	2
valid_sources[0x5f]	868	1			T1	7		T24	12		T3	3
valid_sources[0x60]	1060	1			T1	3		T24	16		T3	1
valid_sources[0x61]	1541	1			T1	7		T2	1		T24	15
valid_sources[0x62]	847	1			T1	5		T24	24		T3	9
valid_sources[0x63]	924	1			T1	5		T2	2		T24	19
valid_sources[0x64]	1138	1			T1	10		T24	10		T3	3
valid_sources[0x65]	932	1			T7	1		T1	4		T2	5
valid_sources[0x66]	2226	1			T1	5		T24	25		T3	1
valid_sources[0x67]	804	1			T1	7		T24	30		T3	7
valid_sources[0x68]	767	1			T1	6		T24	12		T4	17
valid_sources[0x69]	932	1			T1	4		T24	15		T4	14
valid_sources[0x6a]	774	1			T1	7		T24	20		T3	3
valid_sources[0x6b]	779	1			T1	3		T24	22		T4	13
valid_sources[0x6c]	686	1			T1	5		T24	22		T3	2
valid_sources[0x6d]	1213	1			T1	8		T2	3		T24	14
valid_sources[0x6e]	1043	1			T1	5		T24	19		T3	3
valid_sources[0x6f]	1032	1			T1	4		T24	15		T3	1
valid_sources[0x70]	885	1			T1	6		T24	11		T3	1
valid_sources[0x71]	699	1			T1	5		T2	2		T24	14
valid_sources[0x72]	1328	1			T1	6		T24	13		T4	13
valid_sources[0x73]	780	1			T1	7		T2	1		T24	25
valid_sources[0x74]	1063	1			T1	6		T24	21		T3	6
valid_sources[0x75]	1057	1			T1	5		T2	2		T24	21
valid_sources[0x76]	788	1			T1	6		T2	3		T24	22
valid_sources[0x77]	730	1			T1	3		T24	11		T4	10
valid_sources[0x78]	1142	1			T1	4		T24	16		T4	10
valid_sources[0x79]	775	1			T7	2		T1	11		T24	9
valid_sources[0x7a]	868	1			T2	3		T24	18		T3	2
valid_sources[0x7b]	3289	1			T1	1		T24	23		T4	4
valid_sources[0x7c]	837	1			T1	2		T24	4		T3	6
valid_sources[0x7d]	842	1			T1	8		T2	1		T24	33
valid_sources[0x7e]	813	1			T1	7		T24	18		T3	2
valid_sources[0x7f]	833	1			T1	3		T24	23		T3	2
valid_sources[0x80]	697	1			T1	5		T2	4		T24	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60986

1

T7

8

T1

118

T2

31

values[0x0]

all_enables

biggest_size

29250

1

T7

2

T1

110

T2

22

values[0x1]

all_enables

biggest_size

20114

1

T7

1

T1

73

T2

14