Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1193150571	8298	0	0
auto_block_debounce_ctl_rd_A	1193150571	1394	0	0
auto_block_out_ctl_rd_A	1193150571	1857	0	0
com_det_ctl_0_rd_A	1193150571	3740	0	0
com_det_ctl_1_rd_A	1193150571	3825	0	0
com_det_ctl_2_rd_A	1193150571	3619	0	0
com_det_ctl_3_rd_A	1193150571	3661	0	0
com_out_ctl_0_rd_A	1193150571	4108	0	0
com_out_ctl_1_rd_A	1193150571	4058	0	0
com_out_ctl_2_rd_A	1193150571	4278	0	0
com_out_ctl_3_rd_A	1193150571	4135	0	0
com_pre_det_ctl_0_rd_A	1193150571	1005	0	0
com_pre_det_ctl_1_rd_A	1193150571	995	0	0
com_pre_det_ctl_2_rd_A	1193150571	917	0	0
com_pre_det_ctl_3_rd_A	1193150571	1017	0	0
com_pre_sel_ctl_0_rd_A	1193150571	4258	0	0
com_pre_sel_ctl_1_rd_A	1193150571	4186	0	0
com_pre_sel_ctl_2_rd_A	1193150571	4312	0	0
com_pre_sel_ctl_3_rd_A	1193150571	4108	0	0
com_sel_ctl_0_rd_A	1193150571	4228	0	0
com_sel_ctl_1_rd_A	1193150571	4282	0	0
com_sel_ctl_2_rd_A	1193150571	4049	0	0
com_sel_ctl_3_rd_A	1193150571	4114	0	0
ec_rst_ctl_rd_A	1193150571	2140	0	0
intr_enable_rd_A	1193150571	1262	0	0
key_intr_ctl_rd_A	1193150571	2855	0	0
key_intr_debounce_ctl_rd_A	1193150571	889	0	0
key_invert_ctl_rd_A	1193150571	3948	0	0
pin_allowed_ctl_rd_A	1193150571	5000	0	0
pin_out_ctl_rd_A	1193150571	3994	0	0
pin_out_value_rd_A	1193150571	3789	0	0
regwen_rd_A	1193150571	881	0	0
ulp_ac_debounce_ctl_rd_A	1193150571	1040	0	0
ulp_ctl_rd_A	1193150571	1054	0	0
ulp_lid_debounce_ctl_rd_A	1193150571	1166	0	0
ulp_pwrb_debounce_ctl_rd_A	1193150571	1205	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	8298	0	0
T1	210898	3	0	0
T2	147866	5	0	0
T3	528040	0	0	0
T4	304024	0	0	0
T5	316359	0	0	0
T6	597125	0	0	0
T8	406937	5	0	0
T12	0	8	0	0
T24	384886	0	0	0
T25	197288	0	0	0
T26	191311	0	0	0
T34	0	4	0	0
T37	0	566	0	0
T260	0	603	0	0
T264	0	509	0	0
T279	0	1	0	0
T280	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1394	0	0
T11	108539	0	0	0
T12	52295	8	0	0
T13	472355	17	0	0
T34	107378	90	0	0
T260	55530	13	0	0
T264	203686	0	0	0
T279	101376	13	0	0
T281	0	3	0	0
T282	0	7	0	0
T283	0	2	0	0
T284	0	36	0	0
T285	0	4	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1857	0	0
T11	108539	0	0	0
T12	52295	2	0	0
T13	472355	29	0	0
T34	107378	257	0	0
T260	55530	2	0	0
T264	203686	0	0	0
T265	0	8	0	0
T279	101376	6	0	0
T281	0	9	0	0
T282	0	4	0	0
T283	0	6	0	0
T284	0	110	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3740	0	0
T34	107378	56	0	0
T35	204324	0	0	0
T279	101376	4	0	0
T280	180136	0	0	0
T281	0	4	0	0
T283	0	2	0	0
T284	0	27	0	0
T285	0	3	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	82	0	0
T290	0	8	0	0
T291	0	10	0	0
T292	0	2	0	0
T293	205641	0	0	0
T294	96976	0	0	0
T295	183043	0	0	0
T296	100757	0	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3825	0	0
T11	108539	0	0	0
T12	52295	3	0	0
T13	472355	29	0	0
T34	107378	76	0	0
T260	55530	8	0	0
T264	203686	0	0	0
T265	0	7	0	0
T279	101376	12	0	0
T282	0	9	0	0
T283	0	7	0	0
T284	0	14	0	0
T285	0	3	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3619	0	0
T11	108539	0	0	0
T12	52295	8	0	0
T13	472355	16	0	0
T34	107378	82	0	0
T260	55530	7	0	0
T264	203686	0	0	0
T265	0	5	0	0
T279	101376	8	0	0
T281	0	3	0	0
T282	0	6	0	0
T284	0	24	0	0
T285	0	2	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3661	0	0
T11	108539	0	0	0
T12	52295	4	0	0
T13	472355	27	0	0
T34	107378	61	0	0
T260	55530	16	0	0
T264	203686	0	0	0
T265	0	1	0	0
T279	101376	7	0	0
T281	0	1	0	0
T282	0	1	0	0
T283	0	2	0	0
T284	0	32	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4108	0	0
T11	108539	0	0	0
T12	52295	4	0	0
T13	472355	4	0	0
T34	107378	192	0	0
T260	55530	11	0	0
T264	203686	0	0	0
T279	101376	7	0	0
T281	0	6	0	0
T282	0	19	0	0
T284	0	60	0	0
T285	0	1	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	227	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4058	0	0
T11	108539	0	0	0
T12	52295	6	0	0
T13	472355	16	0	0
T34	107378	187	0	0
T260	55530	22	0	0
T264	203686	0	0	0
T265	0	8	0	0
T279	101376	5	0	0
T281	0	1	0	0
T283	0	1	0	0
T284	0	52	0	0
T285	0	10	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4278	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T34	107378	227	0	0
T260	55530	19	0	0
T264	203686	0	0	0
T265	0	2	0	0
T279	101376	7	0	0
T281	0	5	0	0
T282	0	3	0	0
T283	0	7	0	0
T284	0	50	0	0
T285	0	23	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	190	0	0
T293	205641	0	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4135	0	0
T12	52295	2	0	0
T13	472355	7	0	0
T34	107378	142	0	0
T35	204324	0	0	0
T264	203686	0	0	0
T265	0	16	0	0
T279	101376	8	0	0
T281	0	5	0	0
T282	0	5	0	0
T283	0	1	0	0
T284	0	53	0	0
T285	0	6	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T293	205641	0	0	0
T294	96976	0	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1005	0	0
T12	52295	4	0	0
T13	472355	17	0	0
T34	107378	44	0	0
T35	204324	0	0	0
T264	203686	0	0	0
T265	0	8	0	0
T279	101376	12	0	0
T281	0	2	0	0
T282	0	7	0	0
T283	0	5	0	0
T284	0	15	0	0
T285	0	1	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T293	205641	0	0	0
T294	96976	0	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	995	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	7	0	0
T34	107378	47	0	0
T260	55530	13	0	0
T264	203686	0	0	0
T265	0	33	0	0
T279	101376	15	0	0
T281	0	2	0	0
T282	0	3	0	0
T283	0	2	0	0
T284	0	8	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	47	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	917	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	4	0	0
T34	107378	70	0	0
T260	55530	2	0	0
T264	203686	0	0	0
T265	0	26	0	0
T279	101376	9	0	0
T282	0	9	0	0
T283	0	4	0	0
T284	0	13	0	0
T285	0	4	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	53	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1017	0	0
T13	472355	5	0	0
T34	107378	59	0	0
T35	204324	0	0	0
T265	0	22	0	0
T279	101376	0	0	0
T280	180136	0	0	0
T281	0	7	0	0
T282	0	5	0	0
T283	0	4	0	0
T284	0	10	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	72	0	0
T290	0	20	0	0
T291	0	11	0	0
T293	205641	0	0	0
T294	96976	0	0	0
T295	183043	0	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4258	0	0
T11	108539	0	0	0
T12	52295	6	0	0
T13	472355	6	0	0
T34	107378	147	0	0
T260	55530	10	0	0
T264	203686	0	0	0
T265	0	7	0	0
T279	101376	11	0	0
T281	0	3	0	0
T282	0	2	0	0
T283	0	8	0	0
T284	0	51	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4186	0	0
T11	108539	0	0	0
T12	52295	10	0	0
T13	472355	19	0	0
T34	107378	237	0	0
T260	55530	11	0	0
T264	203686	0	0	0
T265	0	16	0	0
T279	101376	9	0	0
T281	0	1	0	0
T282	0	1	0	0
T283	0	6	0	0
T284	0	42	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4312	0	0
T12	52295	4	0	0
T13	472355	37	0	0
T34	107378	181	0	0
T35	204324	0	0	0
T264	203686	0	0	0
T265	0	22	0	0
T279	101376	15	0	0
T281	0	1	0	0
T282	0	16	0	0
T283	0	6	0	0
T284	0	67	0	0
T285	0	18	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T293	205641	0	0	0
T294	96976	0	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4108	0	0
T11	108539	0	0	0
T12	52295	5	0	0
T13	472355	6	0	0
T34	107378	158	0	0
T260	55530	6	0	0
T264	203686	0	0	0
T265	0	4	0	0
T279	101376	9	0	0
T281	0	4	0	0
T282	0	22	0	0
T283	0	9	0	0
T284	0	55	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4228	0	0
T12	52295	8	0	0
T13	472355	39	0	0
T34	107378	231	0	0
T35	204324	0	0	0
T264	203686	0	0	0
T265	0	9	0	0
T279	101376	12	0	0
T281	0	6	0	0
T282	0	3	0	0
T283	0	3	0	0
T284	0	89	0	0
T285	0	1	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T293	205641	0	0	0
T294	96976	0	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4282	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	14	0	0
T34	107378	201	0	0
T260	55530	10	0	0
T264	203686	0	0	0
T265	0	3	0	0
T279	101376	10	0	0
T281	0	4	0	0
T283	0	5	0	0
T284	0	67	0	0
T285	0	10	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	231	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4049	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	6	0	0
T34	107378	221	0	0
T260	55530	15	0	0
T264	203686	0	0	0
T265	0	9	0	0
T279	101376	6	0	0
T281	0	3	0	0
T282	0	25	0	0
T283	0	8	0	0
T284	0	51	0	0
T285	0	19	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	4114	0	0
T11	108539	0	0	0
T12	52295	4	0	0
T13	472355	23	0	0
T34	107378	152	0	0
T260	55530	15	0	0
T264	203686	0	0	0
T279	101376	2	0	0
T281	0	5	0	0
T282	0	4	0	0
T283	0	3	0	0
T284	0	82	0	0
T285	0	5	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	2140	0	0
T11	108539	0	0	0
T12	52295	10	0	0
T13	472355	25	0	0
T34	107378	60	0	0
T260	55530	2	0	0
T264	203686	0	0	0
T265	0	17	0	0
T279	101376	11	0	0
T282	0	4	0	0
T283	0	6	0	0
T284	0	10	0	0
T285	0	3	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1262	0	0
T1	210898	0	0	0
T2	147866	0	0	0
T3	528040	0	0	0
T4	304024	0	0	0
T5	316359	0	0	0
T6	597125	0	0	0
T7	201440	25	0	0
T8	406937	0	0	0
T13	0	32	0	0
T24	384886	0	0	0
T25	197288	0	0	0
T34	0	56	0	0
T260	0	29	0	0
T265	0	15	0	0
T279	0	1	0	0
T281	0	4	0	0
T282	0	1	0	0
T297	0	9	0	0
T298	0	8	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	2855	0	0
T13	472355	9	0	0
T34	107378	376	0	0
T35	204324	0	0	0
T265	0	4	0	0
T279	101376	9	0	0
T280	180136	0	0	0
T281	0	7	0	0
T282	0	2	0	0
T283	0	5	0	0
T284	0	176	0	0
T285	0	70	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	524	0	0
T293	205641	0	0	0
T294	96976	0	0	0
T295	183043	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	889	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	18	0	0
T34	107378	56	0	0
T260	55530	9	0	0
T264	203686	0	0	0
T279	101376	3	0	0
T281	0	2	0	0
T282	0	1	0	0
T283	0	9	0	0
T284	0	25	0	0
T285	0	1	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	63	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3948	0	0
T11	108539	0	0	0
T12	52295	10	0	0
T13	472355	8	0	0
T34	107378	466	0	0
T260	55530	2	0	0
T264	203686	0	0	0
T279	101376	12	0	0
T281	0	4	0	0
T282	0	45	0	0
T283	0	9	0	0
T284	0	137	0	0
T285	0	45	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	5000	0	0
T11	108539	0	0	0
T12	52295	5	0	0
T13	472355	21	0	0
T34	107378	671	0	0
T260	55530	9	0	0
T264	203686	0	0	0
T279	101376	11	0	0
T281	0	4	0	0
T282	0	56	0	0
T283	0	7	0	0
T284	0	237	0	0
T285	0	4	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3994	0	0
T11	108539	0	0	0
T12	52295	5	0	0
T13	472355	13	0	0
T34	107378	326	0	0
T260	55530	7	0	0
T264	203686	0	0	0
T265	0	8	0	0
T279	101376	8	0	0
T283	0	7	0	0
T284	0	74	0	0
T285	0	28	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	363	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	3789	0	0
T11	108539	0	0	0
T12	52295	7	0	0
T13	472355	10	0	0
T34	107378	299	0	0
T260	55530	5	0	0
T264	203686	0	0	0
T265	0	9	0	0
T279	101376	2	0	0
T281	0	9	0	0
T282	0	24	0	0
T283	0	4	0	0
T284	0	63	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	881	0	0
T11	108539	0	0	0
T12	52295	3	0	0
T13	472355	3	0	0
T34	107378	65	0	0
T260	55530	14	0	0
T264	203686	0	0	0
T265	0	11	0	0
T279	101376	3	0	0
T282	0	2	0	0
T284	0	17	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	62	0	0
T290	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1040	0	0
T12	52295	5	0	0
T13	472355	58	0	0
T34	107378	95	0	0
T35	204324	0	0	0
T264	203686	0	0	0
T265	0	7	0	0
T279	101376	10	0	0
T281	0	5	0	0
T282	0	9	0	0
T284	0	26	0	0
T285	0	6	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	71	0	0
T293	205641	0	0	0
T294	96976	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1054	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	31	0	0
T34	107378	66	0	0
T260	55530	8	0	0
T264	203686	0	0	0
T265	0	19	0	0
T279	101376	10	0	0
T281	0	3	0	0
T282	0	4	0	0
T284	0	22	0	0
T285	0	3	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	52	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1166	0	0
T11	108539	0	0	0
T12	52295	0	0	0
T13	472355	39	0	0
T34	107378	89	0	0
T260	55530	13	0	0
T264	203686	0	0	0
T279	101376	12	0	0
T281	0	1	0	0
T282	0	3	0	0
T283	0	8	0	0
T284	0	17	0	0
T285	0	4	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0
T289	0	58	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1193150571	1205	0	0
T11	108539	0	0	0
T12	52295	1	0	0
T13	472355	31	0	0
T34	107378	70	0	0
T260	55530	6	0	0
T264	203686	0	0	0
T265	0	8	0	0
T279	101376	8	0	0
T282	0	9	0	0
T283	0	5	0	0
T284	0	21	0	0
T285	0	6	0	0
T286	193153	0	0	0
T287	54953	0	0	0
T288	96886	0	0	0