Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1973

1

T53

8

T13

8

T15

32

auto[1]

601

1

T53

4

T13

15

T22

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1983

1

T53

10

T13

23

T15

22

auto[1]

591

1

T53

2

T15

10

T21

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1949

1

T53

10

T13

23

T15

32

auto[1]

625

1

T53

2

T22

1

T54

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T53

12

T13

12

T15

19

auto[1]

658

1

T13

11

T15

13

T22

1

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2367

1

T53

12

T13

23

T15

14

auto[1]

207

1

T15

18

T45

3

T56

10

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2316

1

T53

12

T13

23

T15

32

auto[1]

258

1

T45

6

T56

8

T143

3

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2384

1

T53

12

T13

23

T15

14

auto[1]

190

1

T15

18

T46

14

T45

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2342

1

T53

12

T13

23

T15

32

auto[1]

232

1

T46

18

T54

9

T45

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2431

1

T53

12

T13

23

T15

22

auto[1]

143

1

T15

10

T46

6

T55

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1952

1

T13

20

T15

24

T22

4

auto[1]

622

1

T53

12

T13

3

T15

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	986	1			T53	10		T13	15		T21	22
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	50	1			T47	2		T323	7		T324	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	31	1			T55	1		T56	4		T83	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T56	2		T259	3		-	-
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	111	1			T46	14		T54	9		T45	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	21	1			T325	7		T326	4		T318	10
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	19	1			T163	2		T316	1		T327	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T244	1		T328	4		T329	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	56	1			T46	7		T143	3		T330	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	38	1			T15	8		T143	3		T331	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	13	1			T46	6		T332	4		T249	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	12	1			T15	10		T333	1		T334	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	12	1			T55	1		T259	2		T250	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T259	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	140	1			T250	3		T260	22		T163	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	28	1			T56	5		T248	1		T163	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	10	1			T309	4		T335	3		T328	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	7	1			T143	3		T318	4		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	17	1			T268	1		T336	1		T328	6
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	3	1			T220	2		T337	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	3	1			T338	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	14	1			T45	3		T47	4		T248	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	9	1			T45	3		T56	3		T339	3
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T248	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T319	6		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	1	1			T335	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T340	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

130

1

T13

12

T58

3

T259

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

155

1

T53

8

T21

15

T46

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T46

7

T158

5

T341

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

139

1

T46

7

T56

3

T48

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

61

1

T254

8

T158

5

T342

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

64

1

T15

8

T45

3

T74

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

22

1

T13

3

T253

3

T145

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

154

1

T54

9

T56

5

T260

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

45

1

T145

4

T260

11

T266

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

62

1

T74

2

T163

4

T268

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T45

4

T47

3

T74

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

81

1

T56

4

T143

3

T145

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

47

1

T145

2

T105

5

T158

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T253

2

T48

1

T257

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T22

1

T108

1

T113

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

116

1

T15

5

T56

2

T248

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

57

1

T22

4

T58

2

T46

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T21

7

T259

2

T305

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T53

2

T22

2

T110

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

71

1

T15

5

T44

1

T55

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T306

1

T143

3

T265

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T205

5

T179

4

T314

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T253

1

T265

3

T263

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

30

1

T47

2

T205

3

T201

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T265

1

T109

3

T309

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T60

3

T74

2

T343

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T48

1

T74

1

T342

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T76

2

T304

2

T305

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T215

3

T257

1

T74

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T304

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T343

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded