Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1188

1

T86

10

T29

10

T16

24

auto[1]

1057

1

T86

10

T29

10

T16

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T86

3

T29

7

T16

11

from_0to1

536

1

T86

3

T29

8

T16

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1134

1

T86

10

T29

9

T16

19

auto[1]

1111

1

T86

10

T29

11

T16

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T86

11

T29

10

T16

17

auto[1]

1147

1

T86

9

T29

10

T16

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T16

2

T264

1

T352

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T86

1

T16

2

T44

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T86

1

T29

2

T44

1

auto[0]

from_1to0

auto[1]

auto[1]

80

1

T29

2

T16

3

T20

2

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T29

1

T16

1

T94

3

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T29

1

T16

2

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T29

2

T16

1

T94

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T16

3

T44

2

T192

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T16

1

T20

3

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T29

2

T16

1

T94

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T86

1

T29

1

T16

2

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T44

1

T192

1

T353

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T86

1

T16

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T86

2

T29

2

T20

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T29

1

T16

3

T20

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T29

1

T20

1

T94

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1132

1

T86

7

T29

8

T16

17

auto[1]

1113

1

T86

13

T29

12

T16

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

543

1

T86

5

T29

5

T16

10

from_0to1

540

1

T86

5

T29

5

T16

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T86

9

T29

6

T16

15

auto[1]

1118

1

T86

11

T29

14

T16

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T86

8

T29

10

T16

18

auto[1]

1137

1

T86

12

T29

10

T16

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

84

1

T86

1

T16

2

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T86

1

T44

1

T192

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T29

1

T16

1

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T29

1

T20

1

T44

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T44

2

T180

2

T72

2

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T86

1

T29

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

52

1

T16

2

T44

1

T354

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T86

1

T29

1

T16

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T86

1

T16

1

T44

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T86

1

T94

2

T44

2

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T29

3

T16

2

T20

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T86

1

T16

4

T94

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T86

1

T29

2

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T86

1

T29

1

T16

2

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T86

1

T16

1

T20

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T16

1

T20

1

T44

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T86

11

T29

9

T16

25

auto[1]

1106

1

T86

9

T29

11

T16

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T86

5

T29

6

T16

12

from_0to1

557

1

T86

5

T29

6

T16

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159

1

T86

12

T29

9

T16

17

auto[1]

1086

1

T86

8

T29

11

T16

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T86

11

T29

9

T16

21

auto[1]

1118

1

T86

9

T29

11

T16

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T86

1

T16

2

T44

2

auto[0]

from_1to0

auto[0]

auto[1]

78

1

T29

1

T16

1

T20

2

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T29

1

T16

2

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T29

1

T16

4

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T86

1

T29

1

T16

1

auto[0]

from_0to1

auto[0]

auto[1]

87

1

T86

2

T29

1

T16

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T16

2

T354

1

T353

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T29

1

T16

3

T44

1

auto[1]

from_1to0

auto[0]

auto[0]

78

1

T16

1

T94

1

T44

2

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T86

1

T29

1

T94

1

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T86

3

T29

2

T16

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T16

1

T180

1

T71

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T86

1

T29

2

T16

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T86

1

T20

1

T44

3

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T29

1

T16

1

T20

2

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T16

1

T20

1

T94

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1126

1

T86

12

T29

13

T16

24

auto[1]

1119

1

T86

8

T29

7

T16

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

542

1

T86

5

T29

3

T16

9

from_0to1

536

1

T86

4

T29

4

T16

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1119

1

T86

11

T29

10

T16

24

auto[1]

1126

1

T86

9

T29

10

T16

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T86

9

T29

4

T16

22

auto[1]

1125

1

T86

11

T29

16

T16

17

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T86

1

T16

1

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T86

1

T16

2

T20

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T29

1

T16

4

T44

2

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T86

1

T29

1

T16

1

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T16

1

T44

2

T354

3

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T86

2

T29

1

T16

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T16

1

T44

2

T180

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T86

1

T29

2

T16

3

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T86

1

T16

1

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T44

2

T354

2

T353

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T86

1

T192

2

T353

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T29

1

T20

1

T264

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T86

1

T44

1

T180

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T29

1

T16

2

T352

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T16

1

T20

2

T94

2

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T16

1

T44

3

T354

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T86

9

T29

11

T16

21

auto[1]

1123

1

T86

11

T29

9

T16

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

531

1

T86

5

T29

4

T16

8

from_0to1

534

1

T86

5

T29

5

T16

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T86

10

T29

9

T16

18

auto[1]

1107

1

T86

10

T29

11

T16

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1116

1

T86

12

T29

10

T16

18

auto[1]

1129

1

T86

8

T29

10

T16

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T86

1

T94

1

T44

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T86

2

T20

1

T94

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T44

1

T354

2

T192

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T29

2

T16

1

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T86

1

T29

1

T16

3

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T16

1

T354

1

T353

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T16

2

T20

1

T94

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T29

1

T20

1

T44

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T29

1

T16

1

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T29

1

T16

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T20

1

T44

3

T354

1

auto[1]

from_1to0

auto[1]

auto[1]

79

1

T86

2

T16

5

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T29

1

T20

1

T354

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T29

1

T16

1

T20

1

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T86

3

T94

1

T44

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T86

1

T29

1

T16

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1120

1

T86

9

T29

7

T16

20

auto[1]

1125

1

T86

11

T29

13

T16

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

566

1

T86

5

T29

7

T16

10

from_0to1

572

1

T86

5

T29

7

T16

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147

1

T86

10

T29

11

T16

22

auto[1]

1098

1

T86

10

T29

9

T16

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1123

1

T86

11

T29

8

T16

16

auto[1]

1122

1

T86

9

T29

12

T16

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T86

1

T44

1

T354

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T16

4

T44

1

T192

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T86

1

T16

1

T20

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T29

1

T16

3

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T86

1

T29

1

T20

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T29

1

T16

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T16

2

T44

1

T192

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T86

1

T20

2

T192

2

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T29

2

T94

3

T192

2

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T29

1

T16

1

T20

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T86

3

T29

1

T16

1

auto[1]

from_1to0

auto[1]

auto[1]

73

1

T29

2

T20

1

T44

1

auto[1]

from_0to1

auto[0]

auto[0]

75

1

T29

1

T16

2

T44

3

auto[1]

from_0to1

auto[0]

auto[1]

90

1

T86

1

T29

3

T16

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T16

2

T20

1

T94

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T86

2

T29

1

T16

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1098

1

T86

11

T29

9

T16

20

auto[1]

1147

1

T86

9

T29

11

T16

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T86

6

T29

5

T16

9

from_0to1

544

1

T86

5

T29

5

T16

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T86

8

T29

8

T16

18

auto[1]

1130

1

T86

12

T29

12

T16

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1157

1

T86

18

T29

12

T16

19

auto[1]

1088

1

T86

2

T29

8

T16

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

79

1

T86

1

T20

1

T192

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T29

1

T16

2

T20

2

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T86

2

T29

2

T16

3

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T86

1

T16

1

T94

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T86

1

T20

1

T94

1

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T29

1

T16

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T86

1

T16

2

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T29

1

T16

2

T94

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T29

1

T20

1

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T16

1

T20

1

T44

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T86

2

T16

1

T20

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T29

1

T16

1

T354

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T86

1

T16

2

T354

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T16

1

T20

1

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

85

1

T86

2

T29

3

T16

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T20

1

T94

1

T353

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1133

1

T86

7

T29

12

T16

17

auto[1]

1112

1

T86

13

T29

8

T16

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T86

5

T29

6

T16

8

from_0to1

544

1

T86

6

T29

7

T16

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T86

14

T29

13

T16

21

auto[1]

1127

1

T86

6

T29

7

T16

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T86

8

T29

12

T16

13

auto[1]

1114

1

T86

12

T29

8

T16

26

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

67

1

T86

1

T29

1

T16

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T29

2

T16

1

T94

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T44

3

T354

1

T180

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T16

2

T20

1

T44

2

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T29

1

T44

2

T180

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T86

2

T16

1

T20

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T29

2

T20

1

T44

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T29

2

T16

1

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T86

1

T29

3

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T86

1

T16

1

T20

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T86

2

T16

1

T20

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T16

2

T354

1

T353

1

auto[1]

from_0to1

auto[0]

auto[0]

83

1

T29

1

T16

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

76

1

T86

1

T29

1

T16

4

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T94

1

T44

1

T192

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T86

3

T16

2

T20

2