Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152025	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

118660

1

T1

302

T6

10

T7

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138052	1			T1	824		T6	16		T7	25
values[0x0]	65845	1			T1	174		T6	8		T7	10
values[0x1]	66788	1			T1	220		T6	3		T7	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123389	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147296

1

T1

547

T6

11

T7

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	945	1			T1	3		T23	1		T9	7
valid_sources[0x01]	1126	1			T1	3		T24	5		T9	14
valid_sources[0x02]	784	1			T1	5		T23	1		T9	4
valid_sources[0x03]	921	1			T1	4		T23	1		T9	15
valid_sources[0x04]	1044	1			T23	1		T4	16		T9	8
valid_sources[0x05]	773	1			T1	11		T6	4		T9	1
valid_sources[0x06]	1630	1			T1	3		T4	3		T9	9
valid_sources[0x07]	1716	1			T1	6		T9	15		T271	1
valid_sources[0x08]	2844	1			T1	1		T4	4		T10	8
valid_sources[0x09]	786	1			T1	8		T23	1		T9	11
valid_sources[0x0a]	1000	1			T1	3		T9	9		T39	1
valid_sources[0x0b]	916	1			T1	5		T9	10		T5	7
valid_sources[0x0c]	814	1			T1	5		T9	10		T39	1
valid_sources[0x0d]	1326	1			T1	8		T4	7		T9	4
valid_sources[0x0e]	1184	1			T1	9		T9	9		T10	2
valid_sources[0x0f]	934	1			T1	9		T9	16		T39	1
valid_sources[0x10]	940	1			T1	8		T3	67		T9	4
valid_sources[0x11]	1401	1			T1	5		T9	14		T10	10
valid_sources[0x12]	1650	1			T1	3		T9	3		T39	1
valid_sources[0x13]	841	1			T1	2		T9	3		T11	2
valid_sources[0x14]	1356	1			T1	3		T9	30		T5	1
valid_sources[0x15]	655	1			T1	4		T9	1		T5	1
valid_sources[0x16]	969	1			T1	3		T271	19		T10	2
valid_sources[0x17]	904	1			T1	7		T9	8		T5	2
valid_sources[0x18]	1439	1			T1	8		T9	8		T39	1
valid_sources[0x19]	775	1			T1	5		T4	8		T9	15
valid_sources[0x1a]	843	1			T1	1		T9	21		T39	1
valid_sources[0x1b]	787	1			T1	4		T9	32		T39	1
valid_sources[0x1c]	865	1			T1	10		T9	6		T5	1
valid_sources[0x1d]	995	1			T1	6		T24	12		T9	3
valid_sources[0x1e]	823	1			T1	7		T9	12		T5	3
valid_sources[0x1f]	890	1			T1	2		T23	2		T9	5
valid_sources[0x20]	960	1			T1	3		T4	8		T9	11
valid_sources[0x21]	892	1			T1	6		T9	15		T39	5
valid_sources[0x22]	1067	1			T1	5		T9	10		T10	1
valid_sources[0x23]	787	1			T1	8		T4	2		T9	5
valid_sources[0x24]	1148	1			T1	4		T2	81		T9	12
valid_sources[0x25]	1106	1			T1	11		T9	9		T10	7
valid_sources[0x26]	760	1			T1	4		T9	11		T5	2
valid_sources[0x27]	1691	1			T1	6		T9	6		T39	1
valid_sources[0x28]	903	1			T1	4		T9	22		T39	1
valid_sources[0x29]	668	1			T1	6		T4	2		T9	14
valid_sources[0x2a]	2000	1			T1	6		T9	7		T10	1
valid_sources[0x2b]	1370	1			T1	2		T9	2		T10	14
valid_sources[0x2c]	792	1			T1	3		T2	1		T39	2
valid_sources[0x2d]	837	1			T1	3		T9	10		T39	3
valid_sources[0x2e]	789	1			T1	5		T9	3		T5	1
valid_sources[0x2f]	866	1			T1	6		T9	13		T5	4
valid_sources[0x30]	990	1			T1	6		T10	9		T12	5
valid_sources[0x31]	1090	1			T1	2		T9	13		T5	1
valid_sources[0x32]	838	1			T1	3		T9	9		T10	2
valid_sources[0x33]	848	1			T1	8		T9	2		T10	6
valid_sources[0x34]	850	1			T1	4		T9	21		T11	3
valid_sources[0x35]	864	1			T1	6		T9	4		T10	4
valid_sources[0x36]	918	1			T1	1		T23	1		T9	2
valid_sources[0x37]	1226	1			T1	2		T6	2		T2	20
valid_sources[0x38]	982	1			T1	8		T9	10		T39	1
valid_sources[0x39]	2204	1			T1	5		T4	8		T9	23
valid_sources[0x3a]	783	1			T1	5		T9	8		T10	1
valid_sources[0x3b]	1143	1			T1	6		T9	27		T39	2
valid_sources[0x3c]	952	1			T1	4		T9	34		T271	7
valid_sources[0x3d]	939	1			T1	8		T2	2		T9	10
valid_sources[0x3e]	1075	1			T1	4		T23	1		T39	1
valid_sources[0x3f]	822	1			T1	3		T9	15		T10	11
valid_sources[0x40]	879	1			T7	45		T9	19		T5	1
valid_sources[0x41]	834	1			T1	9		T9	17		T5	2
valid_sources[0x42]	798	1			T1	5		T9	2		T39	1
valid_sources[0x43]	1515	1			T1	6		T9	3		T39	1
valid_sources[0x44]	886	1			T1	3		T9	6		T39	2
valid_sources[0x45]	1977	1			T1	3		T9	27		T57	128
valid_sources[0x46]	1271	1			T1	3		T8	65		T4	19
valid_sources[0x47]	867	1			T1	3		T9	5		T10	3
valid_sources[0x48]	789	1			T1	3		T4	9		T9	5
valid_sources[0x49]	848	1			T1	2		T9	8		T39	1
valid_sources[0x4a]	806	1			T1	1		T6	2		T2	1
valid_sources[0x4b]	905	1			T1	6		T9	23		T5	1
valid_sources[0x4c]	805	1			T1	7		T2	6		T10	4
valid_sources[0x4d]	1059	1			T1	7		T23	1		T9	8
valid_sources[0x4e]	824	1			T1	6		T9	1		T11	1
valid_sources[0x4f]	814	1			T1	1		T10	3		T11	1
valid_sources[0x50]	692	1			T1	6		T9	7		T5	1
valid_sources[0x51]	934	1			T1	2		T9	5		T5	1
valid_sources[0x52]	1075	1			T1	7		T4	24		T9	5
valid_sources[0x53]	2027	1			T1	7		T5	5		T11	1
valid_sources[0x54]	907	1			T1	2		T9	11		T5	1
valid_sources[0x55]	770	1			T1	7		T9	15		T39	1
valid_sources[0x56]	2035	1			T1	14		T5	1		T271	2
valid_sources[0x57]	932	1			T1	4		T9	24		T10	2
valid_sources[0x58]	895	1			T1	5		T23	1		T9	14
valid_sources[0x59]	931	1			T1	2		T23	1		T9	3
valid_sources[0x5a]	709	1			T1	5		T9	7		T5	5
valid_sources[0x5b]	925	1			T1	4		T4	23		T9	3
valid_sources[0x5c]	776	1			T1	6		T9	4		T10	9
valid_sources[0x5d]	802	1			T1	3		T9	19		T11	1
valid_sources[0x5e]	924	1			T1	2		T9	13		T39	1
valid_sources[0x5f]	1187	1			T1	6		T9	10		T39	1
valid_sources[0x60]	758	1			T1	7		T9	3		T39	2
valid_sources[0x61]	836	1			T1	4		T23	1		T4	12
valid_sources[0x62]	1078	1			T1	7		T9	7		T10	4
valid_sources[0x63]	856	1			T1	4		T9	14		T11	1
valid_sources[0x64]	894	1			T1	1		T4	16		T9	10
valid_sources[0x65]	2232	1			T1	5		T4	1		T9	6
valid_sources[0x66]	816	1			T1	5		T5	1		T271	3
valid_sources[0x67]	789	1			T1	4		T9	6		T39	1
valid_sources[0x68]	1218	1			T1	3		T6	1		T9	4
valid_sources[0x69]	824	1			T1	5		T9	16		T5	4
valid_sources[0x6a]	1318	1			T1	3		T4	17		T9	5
valid_sources[0x6b]	822	1			T1	7		T23	1		T3	70
valid_sources[0x6c]	997	1			T1	1		T9	5		T39	1
valid_sources[0x6d]	836	1			T1	5		T9	6		T39	1
valid_sources[0x6e]	837	1			T1	3		T9	10		T10	4
valid_sources[0x6f]	1838	1			T1	4		T57	128		T12	1
valid_sources[0x70]	1022	1			T1	5		T9	11		T39	1
valid_sources[0x71]	750	1			T1	8		T23	1		T9	7
valid_sources[0x72]	759	1			T1	1		T9	17		T5	1
valid_sources[0x73]	1025	1			T1	7		T4	7		T9	5
valid_sources[0x74]	1201	1			T1	7		T23	1		T9	8
valid_sources[0x75]	1090	1			T1	2		T23	1		T9	8
valid_sources[0x76]	861	1			T9	23		T39	2		T271	7
valid_sources[0x77]	1040	1			T1	5		T23	2		T9	22
valid_sources[0x78]	984	1			T1	6		T4	8		T9	1
valid_sources[0x79]	749	1			T1	10		T4	11		T9	12
valid_sources[0x7a]	736	1			T1	5		T9	2		T5	3
valid_sources[0x7b]	740	1			T1	3		T6	3		T23	1
valid_sources[0x7c]	840	1			T1	5		T9	14		T10	4
valid_sources[0x7d]	878	1			T1	5		T9	17		T10	5
valid_sources[0x7e]	822	1			T1	4		T9	4		T5	1
valid_sources[0x7f]	818	1			T9	26		T39	1		T10	7
valid_sources[0x80]	823	1			T1	5		T9	11		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63439

1

T1

116

T6

8

T7

11

values[0x0]

all_enables

biggest_size

32355

1

T1

98

T6

1

T7

3

values[0x1]

all_enables

biggest_size

22866

1

T1

88

T6

1

T7

3