Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1324626334	10634	0	0
auto_block_debounce_ctl_rd_A	1324626334	1947	0	0
auto_block_out_ctl_rd_A	1324626334	2742	0	0
com_det_ctl_0_rd_A	1324626334	4070	0	0
com_det_ctl_1_rd_A	1324626334	4081	0	0
com_det_ctl_2_rd_A	1324626334	4174	0	0
com_det_ctl_3_rd_A	1324626334	4039	0	0
com_out_ctl_0_rd_A	1324626334	4461	0	0
com_out_ctl_1_rd_A	1324626334	4862	0	0
com_out_ctl_2_rd_A	1324626334	4640	0	0
com_out_ctl_3_rd_A	1324626334	4814	0	0
com_pre_det_ctl_0_rd_A	1324626334	1424	0	0
com_pre_det_ctl_1_rd_A	1324626334	1379	0	0
com_pre_det_ctl_2_rd_A	1324626334	1279	0	0
com_pre_det_ctl_3_rd_A	1324626334	1401	0	0
com_pre_sel_ctl_0_rd_A	1324626334	4812	0	0
com_pre_sel_ctl_1_rd_A	1324626334	4703	0	0
com_pre_sel_ctl_2_rd_A	1324626334	5066	0	0
com_pre_sel_ctl_3_rd_A	1324626334	4570	0	0
com_sel_ctl_0_rd_A	1324626334	4619	0	0
com_sel_ctl_1_rd_A	1324626334	4820	0	0
com_sel_ctl_2_rd_A	1324626334	5027	0	0
com_sel_ctl_3_rd_A	1324626334	4915	0	0
ec_rst_ctl_rd_A	1324626334	2739	0	0
intr_enable_rd_A	1324626334	2050	0	0
key_intr_ctl_rd_A	1324626334	3938	0	0
key_intr_debounce_ctl_rd_A	1324626334	1406	0	0
key_invert_ctl_rd_A	1324626334	5705	0	0
pin_allowed_ctl_rd_A	1324626334	5961	0	0
pin_out_ctl_rd_A	1324626334	4904	0	0
pin_out_value_rd_A	1324626334	4652	0	0
regwen_rd_A	1324626334	1536	0	0
ulp_ac_debounce_ctl_rd_A	1324626334	1693	0	0
ulp_ctl_rd_A	1324626334	1550	0	0
ulp_lid_debounce_ctl_rd_A	1324626334	1649	0	0
ulp_pwrb_debounce_ctl_rd_A	1324626334	1572	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	10634	0	0
T1	109326	4	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	0	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	6	0	0
T12	0	4	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	5	0	0
T39	0	4	0	0
T271	0	377	0	0
T273	0	375	0	0
T274	0	665	0	0
T283	0	4	0	0
T287	0	4	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1947	0	0
T1	109326	52	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	15	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	130	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	112	0	0
T34	0	7	0	0
T36	0	25	0	0
T38	0	3	0	0
T39	0	6	0	0
T275	0	9	0	0
T288	0	8	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	2742	0	0
T1	109326	180	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	9	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	262	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	285	0	0
T34	0	37	0	0
T36	0	18	0	0
T38	0	29	0	0
T39	0	8	0	0
T275	0	13	0	0
T288	0	36	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4070	0	0
T1	109326	38	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	1	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	44	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	103	0	0
T34	0	7	0	0
T36	0	22	0	0
T38	0	9	0	0
T39	0	5	0	0
T275	0	4	0	0
T289	0	6	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4081	0	0
T1	109326	41	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	0	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	77	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	93	0	0
T34	0	6	0	0
T36	0	24	0	0
T38	0	7	0	0
T39	0	10	0	0
T288	0	2	0	0
T289	0	8	0	0
T290	0	1	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4174	0	0
T1	109326	44	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	10	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	77	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	70	0	0
T34	0	7	0	0
T36	0	14	0	0
T39	0	6	0	0
T275	0	13	0	0
T288	0	1	0	0
T289	0	3	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4039	0	0
T1	109326	38	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	13	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	74	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	68	0	0
T34	0	3	0	0
T36	0	13	0	0
T38	0	18	0	0
T39	0	1	0	0
T275	0	5	0	0
T289	0	1	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4461	0	0
T1	109326	55	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	6	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	149	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	178	0	0
T34	0	2	0	0
T36	0	20	0	0
T38	0	17	0	0
T39	0	7	0	0
T275	0	9	0	0
T288	0	6	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4862	0	0
T1	109326	109	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	27	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	203	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	250	0	0
T34	0	9	0	0
T36	0	61	0	0
T38	0	15	0	0
T39	0	11	0	0
T275	0	2	0	0
T288	0	5	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4640	0	0
T1	109326	111	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	13	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	122	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	230	0	0
T34	0	13	0	0
T36	0	50	0	0
T38	0	13	0	0
T39	0	3	0	0
T275	0	17	0	0
T288	0	14	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4814	0	0
T1	109326	77	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	3	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	193	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	199	0	0
T34	0	19	0	0
T36	0	2	0	0
T38	0	16	0	0
T39	0	14	0	0
T275	0	17	0	0
T288	0	17	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1424	0	0
T1	109326	44	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	8	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	65	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	84	0	0
T34	0	4	0	0
T36	0	36	0	0
T38	0	5	0	0
T39	0	10	0	0
T275	0	6	0	0
T288	0	7	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1379	0	0
T1	109326	52	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	14	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	103	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	86	0	0
T34	0	3	0	0
T36	0	9	0	0
T38	0	3	0	0
T39	0	6	0	0
T275	0	17	0	0
T288	0	10	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1279	0	0
T1	109326	42	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	1	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	55	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	90	0	0
T34	0	2	0	0
T36	0	9	0	0
T39	0	4	0	0
T288	0	2	0	0
T289	0	1	0	0
T290	0	6	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1401	0	0
T1	109326	45	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	22	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	76	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	85	0	0
T34	0	6	0	0
T36	0	43	0	0
T38	0	4	0	0
T39	0	2	0	0
T275	0	9	0	0
T288	0	5	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4812	0	0
T1	109326	147	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	6	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	189	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	235	0	0
T34	0	9	0	0
T36	0	17	0	0
T38	0	22	0	0
T39	0	12	0	0
T288	0	5	0	0
T289	0	6	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4703	0	0
T1	109326	124	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	22	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	187	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	172	0	0
T34	0	4	0	0
T36	0	38	0	0
T38	0	1	0	0
T275	0	6	0	0
T289	0	9	0	0
T290	0	28	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	5066	0	0
T1	109326	77	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	0	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	257	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	196	0	0
T34	0	18	0	0
T36	0	27	0	0
T38	0	1	0	0
T39	0	9	0	0
T275	0	3	0	0
T288	0	19	0	0
T289	0	8	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4570	0	0
T1	109326	101	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	4	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	221	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	175	0	0
T34	0	2	0	0
T36	0	30	0	0
T38	0	8	0	0
T39	0	8	0	0
T288	0	5	0	0
T290	0	5	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4619	0	0
T1	109326	73	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	0	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	228	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	197	0	0
T34	0	31	0	0
T36	0	14	0	0
T38	0	14	0	0
T39	0	3	0	0
T275	0	7	0	0
T288	0	20	0	0
T289	0	9	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4820	0	0
T1	109326	83	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	3	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	306	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	253	0	0
T34	0	3	0	0
T36	0	23	0	0
T38	0	10	0	0
T39	0	8	0	0
T288	0	9	0	0
T289	0	3	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	5027	0	0
T1	109326	94	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	16	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	235	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	217	0	0
T34	0	23	0	0
T36	0	10	0	0
T38	0	9	0	0
T39	0	11	0	0
T288	0	3	0	0
T289	0	1	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4915	0	0
T1	109326	132	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	13	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	179	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	248	0	0
T34	0	27	0	0
T36	0	25	0	0
T38	0	11	0	0
T39	0	11	0	0
T275	0	3	0	0
T288	0	14	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	2739	0	0
T1	109326	38	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	10	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	95	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	73	0	0
T34	0	5	0	0
T36	0	1	0	0
T38	0	11	0	0
T39	0	9	0	0
T275	0	7	0	0
T288	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	2050	0	0
T1	109326	34	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	30	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	62	0	0
T23	193603	0	0	0
T24	100912	17	0	0
T33	0	75	0	0
T36	0	39	0	0
T38	0	2	0	0
T39	0	8	0	0
T275	0	1	0	0
T291	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	3938	0	0
T1	109326	167	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	15	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	505	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	674	0	0
T34	0	56	0	0
T36	0	48	0	0
T38	0	13	0	0
T39	0	6	0	0
T275	0	10	0	0
T288	0	36	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1406	0	0
T1	109326	45	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	3	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	74	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	51	0	0
T36	0	26	0	0
T38	0	27	0	0
T39	0	2	0	0
T275	0	7	0	0
T288	0	4	0	0
T289	0	4	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	5705	0	0
T1	109326	193	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	14	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	511	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	540	0	0
T34	0	6	0	0
T38	0	1	0	0
T39	0	7	0	0
T275	0	11	0	0
T288	0	5	0	0
T289	0	1	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	5961	0	0
T1	109326	315	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	10	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	803	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	734	0	0
T34	0	68	0	0
T36	0	4	0	0
T38	0	8	0	0
T39	0	3	0	0
T275	0	4	0	0
T288	0	4	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4904	0	0
T1	109326	161	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	20	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	308	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	409	0	0
T34	0	7	0	0
T36	0	32	0	0
T39	0	7	0	0
T275	0	13	0	0
T288	0	2	0	0
T289	0	5	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	4652	0	0
T1	109326	177	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	21	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	333	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	330	0	0
T34	0	30	0	0
T36	0	24	0	0
T39	0	13	0	0
T288	0	31	0	0
T289	0	3	0	0
T290	0	3	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1536	0	0
T1	109326	50	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	5	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	77	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	70	0	0
T34	0	6	0	0
T36	0	43	0	0
T38	0	21	0	0
T39	0	9	0	0
T288	0	2	0	0
T289	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1693	0	0
T1	109326	36	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	10	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	83	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	68	0	0
T34	0	7	0	0
T36	0	12	0	0
T38	0	10	0	0
T39	0	10	0	0
T275	0	5	0	0
T288	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1550	0	0
T1	109326	33	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	19	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	62	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	61	0	0
T34	0	6	0	0
T36	0	15	0	0
T38	0	2	0	0
T39	0	11	0	0
T288	0	5	0	0
T289	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1649	0	0
T1	109326	39	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	11	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	67	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	86	0	0
T36	0	32	0	0
T38	0	15	0	0
T39	0	7	0	0
T275	0	4	0	0
T288	0	7	0	0
T289	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1324626334	1572	0	0
T1	109326	33	0	0
T2	49931	0	0	0
T3	81761	0	0	0
T4	138007	20	0	0
T6	201338	0	0	0
T7	42972	0	0	0
T8	197690	0	0	0
T9	412095	73	0	0
T23	193603	0	0	0
T24	100912	0	0	0
T33	0	81	0	0
T34	0	9	0	0
T36	0	13	0	0
T38	0	19	0	0
T39	0	3	0	0
T275	0	4	0	0
T288	0	5	0	0