Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2086

1

T31

3

T18

2

T38

3

auto[1]

608

1

T31

1

T16

7

T38

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2022

1

T31

4

T16

3

T38

4

auto[1]

672

1

T16

4

T18

2

T95

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2071

1

T31

3

T16

3

T18

2

auto[1]

623

1

T31

1

T16

4

T38

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1982

1

T31

3

T16

4

T38

3

auto[1]

712

1

T31

1

T16

3

T18

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2428

1

T31

3

T16

7

T18

2

auto[1]

266

1

T31

1

T41

5

T82

1

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2503

1

T31

4

T16

7

T18

2

auto[1]

191

1

T38

1

T41

4

T49

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2516

1

T31

3

T16

7

T18

2

auto[1]

178

1

T31

1

T41

6

T49

8

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2505

1

T31

4

T16

7

T18

2

auto[1]

189

1

T41

1

T49

6

T130

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2454

1

T31

4

T16

7

T18

2

auto[1]

240

1

T41

4

T49

8

T82

1

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2100

1

T31

2

T16

7

T18

2

auto[1]

594

1

T31

2

T39

11

T40

21

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	935	1			T16	4		T18	2		T95	6
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	103	1			T31	1		T41	5		T236	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	67	1			T237	1		T238	7		T330	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	41	1			T236	4		T256	12		T230	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	55	1			T130	2		T237	1		T250	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	24	1			T331	7		T324	5		T332	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	13	1			T49	3		T311	2		T319	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T202	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	56	1			T31	1		T41	6		T49	4
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	33	1			T333	3		T324	7		T334	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	14	1			T335	1		T336	2		T255	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	8	1			T82	1		T237	1		T85	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	30	1			T321	14		T337	5		T338	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	5	1			T83	1		T85	4		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T324	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	50	1			T38	1		T49	2		T339	3
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	23	1			T322	7		T340	2		T341	9
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	29	1			T41	3		T83	8		T238	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T236	1		T324	3		T342	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	25	1			T83	9		T321	12		T343	1
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T331	4		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	14	1			T41	1		T316	6		T330	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	12	1			T234	3		T344	4		T337	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T345	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T49	2		T85	1		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T335	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

117

1

T39

15

T49

4

T83

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

140

1

T74

7

T83

1

T310

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

67

1

T31

1

T39

11

T40

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

103

1

T42

9

T49

2

T240

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T52

4

T136

2

T74

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T154

5

T259

5

T240

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T49

2

T259

2

T232

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

97

1

T41

1

T259

8

T236

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

66

1

T238

1

T339

3

T163

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T87

3

T86

1

T331

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T154

2

T242

2

T346

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

79

1

T52

4

T41

5

T240

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T38

1

T41

3

T151

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

21

1

T31

1

T40

1

T154

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

22

1

T52

2

T347

2

T316

12

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

143

1

T154

6

T310

11

T153

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

39

1

T95

3

T42

4

T41

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T74

5

T237

1

T88

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T125

2

T309

2

T251

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

99

1

T18

2

T82

1

T256

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T95

2

T240

2

T310

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T125

1

T240

4

T309

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T309

1

T251

2

T347

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

77

1

T40

3

T49

3

T160

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T16

4

T95

1

T39

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

15

1

T151

2

T110

1

T158

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T244

2

T348

2

T121

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T65

1

T253

4

T349

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T125

1

T208

1

T314

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T74

1

T347

1

T310

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T253

2

T111

1

T350

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded