Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1257

1

T15

18

T235

6

T18

18

auto[1]

1243

1

T15

22

T235

14

T18

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T15

11

T235

3

T18

10

from_0to1

585

1

T15

11

T235

3

T18

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1294

1

T15

22

T235

10

T18

19

auto[1]

1206

1

T15

18

T235

10

T18

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1254

1

T15

22

T235

8

T18

24

auto[1]

1246

1

T15

18

T235

12

T18

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T15

1

T18

2

T364

2

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T15

2

T18

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T15

1

T18

1

T254

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T15

1

T235

2

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

78

1

T15

1

T18

2

T254

1

auto[0]

from_0to1

auto[0]

auto[1]

81

1

T15

1

T18

1

T364

2

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T15

2

T18

3

T364

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T215

1

T257

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

89

1

T15

2

T18

2

T254

1

auto[1]

from_1to0

auto[0]

auto[1]

74

1

T15

1

T235

1

T254

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T15

1

T18

2

T364

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T15

2

T18

1

T364

2

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T15

2

T235

1

T364

1

auto[1]

from_0to1

auto[0]

auto[1]

78

1

T15

2

T235

1

T18

2

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T15

3

T136

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T235

1

T18

2

T39

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1268

1

T15

19

T235

7

T18

20

auto[1]

1232

1

T15

21

T235

13

T18

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

598

1

T15

8

T235

4

T18

13

from_0to1

597

1

T15

9

T235

4

T18

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1244

1

T15

18

T235

11

T18

17

auto[1]

1256

1

T15

22

T235

9

T18

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1238

1

T15

20

T235

13

T18

22

auto[1]

1262

1

T15

20

T235

7

T18

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T15

2

T18

1

T254

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T18

1

T364

1

T39

1

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T15

1

T235

2

T18

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T15

1

T235

1

T18

2

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T18

2

T364

1

T136

2

auto[0]

from_0to1

auto[0]

auto[1]

89

1

T18

2

T254

2

T39

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T254

1

T39

2

T257

1

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T15

1

T235

1

T18

2

auto[1]

from_1to0

auto[0]

auto[0]

85

1

T18

1

T364

2

T39

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T15

3

T235

1

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

85

1

T15

1

T18

6

T254

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T39

1

T257

2

T136

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T15

2

T235

1

T18

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T15

2

T257

1

T65

4

auto[1]

from_0to1

auto[1]

auto[0]

86

1

T15

2

T235

2

T364

1

auto[1]

from_0to1

auto[1]

auto[1]

84

1

T15

2

T18

5

T364

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1217

1

T15

22

T235

10

T18

17

auto[1]

1283

1

T15

18

T235

10

T18

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

583

1

T15

10

T235

6

T18

11

from_0to1

587

1

T15

9

T235

6

T18

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1279

1

T15

20

T235

6

T18

17

auto[1]

1221

1

T15

20

T235

14

T18

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1253

1

T15

19

T235

8

T18

20

auto[1]

1247

1

T15

21

T235

12

T18

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T15

2

T18

1

T364

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T15

2

T235

1

T18

4

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T15

1

T235

1

T18

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T235

2

T18

1

T364

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T15

2

T254

1

T39

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T15

1

T235

1

T364

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T15

1

T364

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T15

1

T235

1

T18

3

auto[1]

from_1to0

auto[0]

auto[0]

83

1

T15

2

T39

2

T215

2

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T15

1

T235

1

T18

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T18

2

T254

1

T39

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T15

2

T235

1

T39

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T15

1

T18

2

T254

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T15

2

T18

1

T364

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T235

2

T18

3

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

96

1

T15

1

T235

2

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1263

1

T15

20

T235

7

T18

21

auto[1]

1237

1

T15

20

T235

13

T18

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

603

1

T15

11

T235

6

T18

9

from_0to1

608

1

T15

12

T235

6

T18

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1262

1

T15

18

T235

14

T18

22

auto[1]

1238

1

T15

22

T235

6

T18

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1272

1

T15

16

T235

7

T18

24

auto[1]

1228

1

T15

24

T235

13

T18

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T15

1

T235

1

T18

3

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T235

2

T39

1

T365

1

auto[0]

from_1to0

auto[1]

auto[0]

81

1

T15

2

T235

1

T39

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T254

2

T136

1

T247

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T15

1

T18

1

T364

1

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T15

2

T18

2

T254

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T15

1

T18

2

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

94

1

T15

2

T254

2

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

83

1

T15

1

T364

1

T254

1

auto[1]

from_1to0

auto[0]

auto[1]

89

1

T15

3

T235

1

T18

4

auto[1]

from_1to0

auto[1]

auto[0]

79

1

T235

1

T18

1

T254

1

auto[1]

from_1to0

auto[1]

auto[1]

85

1

T15

4

T18

1

T364

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T15

1

T235

1

T18

1

auto[1]

from_0to1

auto[0]

auto[1]

80

1

T15

1

T235

3

T364

2

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T15

1

T235

1

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T15

3

T235

1

T18

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1254

1

T15

18

T235

7

T18

14

auto[1]

1246

1

T15

22

T235

13

T18

26

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

613

1

T15

12

T235

5

T18

8

from_0to1

606

1

T15

11

T235

6

T18

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1245

1

T15

20

T235

9

T18

22

auto[1]

1255

1

T15

20

T235

11

T18

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1233

1

T15

20

T235

11

T18

14

auto[1]

1267

1

T15

20

T235

9

T18

26

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T15

1

T235

1

T18

1

auto[0]

from_1to0

auto[0]

auto[1]

83

1

T15

3

T18

1

T254

1

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T257

1

T136

1

T365

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T15

1

T235

2

T254

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T15

2

T18

1

T364

1

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T15

2

T235

1

T18

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T15

1

T235

1

T254

1

auto[0]

from_0to1

auto[1]

auto[1]

82

1

T15

1

T18

1

T254

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T15

1

T235

1

T254

1

auto[1]

from_1to0

auto[0]

auto[1]

85

1

T18

4

T364

1

T254

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T15

4

T235

1

T364

1

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T15

2

T18

2

T39

2

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T15

1

T215

2

T65

2

auto[1]

from_0to1

auto[0]

auto[1]

78

1

T15

1

T235

1

T18

1

auto[1]

from_0to1

auto[1]

auto[0]

81

1

T15

1

T235

3

T18

3

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T15

2

T18

1

T364

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1220

1

T15

21

T235

5

T18

16

auto[1]

1280

1

T15

19

T235

15

T18

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

578

1

T15

11

T235

5

T18

13

from_0to1

584

1

T15

11

T235

5

T18

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1255

1

T15

20

T235

7

T18

19

auto[1]

1245

1

T15

20

T235

13

T18

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T15

17

T235

13

T18

24

auto[1]

1231

1

T15

23

T235

7

T18

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T235

1

T254

3

T39

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T15

3

T18

2

T364

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T18

4

T364

1

T254

2

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T15

4

T235

1

T18

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T15

2

T18

2

T254

2

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T18

3

T39

2

T366

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T15

1

T254

1

T257

1

auto[0]

from_0to1

auto[1]

auto[1]

85

1

T15

1

T18

1

T39

2

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T18

1

T364

1

T39

1

auto[1]

from_1to0

auto[0]

auto[1]

80

1

T15

2

T235

1

T39

3

auto[1]

from_1to0

auto[1]

auto[0]

78

1

T15

2

T235

1

T18

3

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T235

1

T18

2

T39

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T15

2

T235

2

T18

3

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T15

2

T18

1

T364

1

auto[1]

from_0to1

auto[1]

auto[0]

78

1

T15

2

T235

2

T18

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T15

1

T235

1

T18

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1241

1

T15

18

T235

14

T18

18

auto[1]

1259

1

T15

22

T235

6

T18

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

617

1

T15

11

T235

4

T18

9

from_0to1

621

1

T15

11

T235

5

T18

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1223

1

T15

16

T235

13

T18

19

auto[1]

1277

1

T15

24

T235

7

T18

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T15

23

T235

10

T18

19

auto[1]

1231

1

T15

17

T235

10

T18

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

94

1

T15

1

T235

1

T18

3

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T15

2

T235

2

T254

2

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T15

2

T18

1

T364

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T235

1

T18

1

T364

2

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T15

2

T235

1

T18

1

auto[0]

from_0to1

auto[0]

auto[1]

73

1

T15

2

T235

2

T18

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T364

1

T254

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

86

1

T15

1

T18

1

T364

1

auto[1]

from_1to0

auto[0]

auto[0]

94

1

T18

2

T215

1

T365

2

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T18

2

T39

4

T365

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T15

3

T254

1

T257

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T15

3

T364

1

T254

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T235

2

T18

1

T364

1

auto[1]

from_0to1

auto[0]

auto[1]

87

1

T15

1

T254

1

T39

2

auto[1]

from_0to1

auto[1]

auto[0]

83

1

T15

2

T364

2

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

92

1

T15

3

T18

4

T39

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1245

1

T15

23

T235

5

T18

21

auto[1]

1255

1

T15

17

T235

15

T18

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

597

1

T15

8

T235

2

T18

7

from_0to1

593

1

T15

9

T235

2

T18

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1232

1

T15

16

T235

10

T18

21

auto[1]

1268

1

T15

24

T235

10

T18

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1223

1

T15

22

T235

12

T18

20

auto[1]

1277

1

T15

18

T235

8

T18

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T15

2

T254

3

T257

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T15

2

T18

1

T364

1

auto[0]

from_1to0

auto[1]

auto[0]

82

1

T18

1

T364

1

T39

3

auto[0]

from_1to0

auto[1]

auto[1]

95

1

T15

1

T215

2

T247

2

auto[0]

from_0to1

auto[0]

auto[0]

79

1

T15

1

T18

3

T254

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T18

3

T254

1

T39

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T15

1

T18

1

T39

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T15

2

T254

1

T39

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T15

1

T235

1

T18

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T18

1

T254

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T15

1

T235

1

T18

3

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T15

1

T364

1

T254

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T15

1

T254

1

T215

1

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T15

1

T235

1

T364

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T15

1

T364

2

T254

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T15

2

T235

1

T18

1