Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120255

1

T1

460

T2

630

T3

593

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142152	1			T1	242		T2	1687		T3	1618
values[0x0]	67126	1			T1	120		T2	406		T3	391
values[0x1]	68300	1			T1	99		T2	421		T3	416

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127380	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150198

1

T1

460

T2

1179

T3

1130

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1029	1			T1	2		T2	4		T3	2
valid_sources[0x01]	927	1			T1	3		T2	30		T3	10
valid_sources[0x02]	944	1			T1	2		T2	11		T3	10
valid_sources[0x03]	940	1			T2	14		T3	6		T264	1
valid_sources[0x04]	1443	1			T1	1		T3	6		T25	4
valid_sources[0x05]	1147	1			T1	2		T2	5		T3	3
valid_sources[0x06]	1251	1			T1	2		T2	16		T3	4
valid_sources[0x07]	797	1			T3	6		T4	20		T25	1
valid_sources[0x08]	1104	1			T2	32		T3	9		T22	4
valid_sources[0x09]	990	1			T1	4		T3	3		T4	4
valid_sources[0x0a]	1044	1			T1	4		T2	24		T3	13
valid_sources[0x0b]	970	1			T1	3		T2	25		T3	16
valid_sources[0x0c]	1044	1			T3	5		T22	1		T266	3
valid_sources[0x0d]	956	1			T1	1		T3	7		T25	1
valid_sources[0x0e]	848	1			T1	2		T3	9		T22	1
valid_sources[0x0f]	876	1			T1	7		T2	25		T3	11
valid_sources[0x10]	2688	1			T1	1		T3	10		T25	1
valid_sources[0x11]	866	1			T1	1		T2	10		T3	9
valid_sources[0x12]	973	1			T1	2		T3	9		T25	1
valid_sources[0x13]	835	1			T1	1		T3	16		T25	1
valid_sources[0x14]	883	1			T1	1		T3	18		T24	10
valid_sources[0x15]	1693	1			T1	2		T2	16		T3	13
valid_sources[0x16]	1185	1			T3	9		T25	1		T5	1
valid_sources[0x17]	937	1			T1	4		T2	13		T3	23
valid_sources[0x18]	968	1			T3	11		T4	35		T25	2
valid_sources[0x19]	1019	1			T1	3		T3	12		T22	1
valid_sources[0x1a]	996	1			T1	1		T2	28		T3	11
valid_sources[0x1b]	1553	1			T1	1		T3	5		T264	1
valid_sources[0x1c]	913	1			T2	5		T3	12		T22	2
valid_sources[0x1d]	1470	1			T1	1		T3	7		T22	2
valid_sources[0x1e]	1641	1			T1	2		T2	38		T3	10
valid_sources[0x1f]	943	1			T3	12		T22	1		T4	13
valid_sources[0x20]	744	1			T1	1		T2	1		T3	11
valid_sources[0x21]	1366	1			T1	5		T3	7		T25	1
valid_sources[0x22]	756	1			T1	1		T2	14		T3	14
valid_sources[0x23]	920	1			T1	3		T3	13		T4	11
valid_sources[0x24]	951	1			T1	2		T2	25		T3	5
valid_sources[0x25]	947	1			T2	4		T3	4		T25	1
valid_sources[0x26]	1076	1			T1	1		T3	9		T264	6
valid_sources[0x27]	1056	1			T1	1		T2	5		T3	11
valid_sources[0x28]	841	1			T1	3		T3	6		T5	3
valid_sources[0x29]	929	1			T1	1		T2	1		T3	7
valid_sources[0x2a]	915	1			T1	3		T3	17		T22	3
valid_sources[0x2b]	954	1			T1	2		T2	76		T3	3
valid_sources[0x2c]	1105	1			T1	5		T2	13		T3	10
valid_sources[0x2d]	924	1			T1	5		T2	11		T3	6
valid_sources[0x2e]	984	1			T3	12		T4	5		T25	1
valid_sources[0x2f]	1041	1			T1	2		T3	7		T22	1
valid_sources[0x30]	994	1			T1	1		T3	4		T22	1
valid_sources[0x31]	1127	1			T1	1		T3	8		T25	1
valid_sources[0x32]	1660	1			T1	5		T2	1		T3	15
valid_sources[0x33]	1037	1			T1	3		T2	8		T3	10
valid_sources[0x34]	976	1			T1	1		T2	41		T3	13
valid_sources[0x35]	930	1			T1	1		T2	5		T3	12
valid_sources[0x36]	1331	1			T1	2		T3	6		T25	4
valid_sources[0x37]	1609	1			T1	2		T3	11		T25	1
valid_sources[0x38]	979	1			T1	2		T2	21		T3	10
valid_sources[0x39]	959	1			T1	2		T3	3		T25	2
valid_sources[0x3a]	1317	1			T2	32		T3	6		T4	18
valid_sources[0x3b]	821	1			T1	2		T2	13		T3	4
valid_sources[0x3c]	994	1			T1	7		T2	3		T3	13
valid_sources[0x3d]	1057	1			T1	1		T3	17		T25	2
valid_sources[0x3e]	964	1			T2	19		T3	17		T25	4
valid_sources[0x3f]	990	1			T1	2		T2	8		T3	6
valid_sources[0x40]	872	1			T2	7		T3	14		T25	3
valid_sources[0x41]	898	1			T1	1		T2	54		T3	8
valid_sources[0x42]	1083	1			T1	1		T2	36		T3	6
valid_sources[0x43]	1025	1			T1	6		T2	26		T3	11
valid_sources[0x44]	792	1			T1	3		T3	6		T22	1
valid_sources[0x45]	1245	1			T1	5		T3	11		T5	3
valid_sources[0x46]	1239	1			T2	3		T3	6		T25	2
valid_sources[0x47]	917	1			T1	4		T2	1		T3	1
valid_sources[0x48]	795	1			T2	43		T3	2		T23	1
valid_sources[0x49]	949	1			T1	1		T2	47		T3	2
valid_sources[0x4a]	873	1			T1	2		T3	4		T25	1
valid_sources[0x4b]	834	1			T1	3		T3	6		T25	2
valid_sources[0x4c]	1590	1			T1	2		T2	50		T3	14
valid_sources[0x4d]	806	1			T1	1		T2	2		T3	5
valid_sources[0x4e]	887	1			T1	4		T3	10		T22	1
valid_sources[0x4f]	866	1			T1	3		T2	2		T3	5
valid_sources[0x50]	982	1			T1	2		T3	17		T4	4
valid_sources[0x51]	1176	1			T1	2		T3	6		T25	1
valid_sources[0x52]	1710	1			T1	1		T2	13		T3	8
valid_sources[0x53]	1813	1			T1	1		T2	21		T3	15
valid_sources[0x54]	1032	1			T1	4		T3	14		T4	9
valid_sources[0x55]	1727	1			T1	1		T3	6		T23	2
valid_sources[0x56]	981	1			T1	1		T2	35		T3	10
valid_sources[0x57]	1056	1			T1	4		T2	20		T3	8
valid_sources[0x58]	1136	1			T1	1		T3	7		T4	5
valid_sources[0x59]	866	1			T1	2		T3	14		T23	1
valid_sources[0x5a]	1108	1			T1	2		T3	6		T25	2
valid_sources[0x5b]	1373	1			T1	2		T3	13		T25	1
valid_sources[0x5c]	787	1			T1	1		T3	2		T4	5
valid_sources[0x5d]	1007	1			T1	4		T3	4		T22	2
valid_sources[0x5e]	1196	1			T1	1		T2	16		T3	12
valid_sources[0x5f]	2046	1			T1	1		T2	28		T3	14
valid_sources[0x60]	982	1			T1	5		T2	1		T3	8
valid_sources[0x61]	927	1			T1	1		T3	9		T5	1
valid_sources[0x62]	1036	1			T1	2		T2	18		T3	9
valid_sources[0x63]	743	1			T1	1		T3	8		T25	1
valid_sources[0x64]	893	1			T1	1		T3	4		T25	1
valid_sources[0x65]	867	1			T2	16		T3	7		T22	1
valid_sources[0x66]	1011	1			T1	2		T3	14		T25	1
valid_sources[0x67]	1592	1			T3	5		T25	1		T266	4
valid_sources[0x68]	787	1			T1	1		T2	6		T3	10
valid_sources[0x69]	1445	1			T1	1		T2	24		T3	12
valid_sources[0x6a]	1014	1			T1	3		T3	15		T5	2
valid_sources[0x6b]	997	1			T1	5		T2	11		T3	16
valid_sources[0x6c]	869	1			T1	2		T3	12		T22	1
valid_sources[0x6d]	1566	1			T1	1		T3	11		T4	4
valid_sources[0x6e]	1014	1			T1	1		T2	21		T3	15
valid_sources[0x6f]	956	1			T1	5		T3	5		T22	1
valid_sources[0x70]	949	1			T1	1		T2	9		T3	13
valid_sources[0x71]	961	1			T2	6		T3	16		T24	11
valid_sources[0x72]	1176	1			T1	2		T2	98		T3	5
valid_sources[0x73]	875	1			T1	1		T2	7		T3	9
valid_sources[0x74]	878	1			T1	1		T2	1		T3	6
valid_sources[0x75]	1464	1			T2	13		T3	9		T5	1
valid_sources[0x76]	1009	1			T1	2		T2	31		T3	9
valid_sources[0x77]	949	1			T1	1		T3	21		T25	1
valid_sources[0x78]	1030	1			T1	3		T3	13		T22	1
valid_sources[0x79]	1019	1			T2	22		T3	15		T25	1
valid_sources[0x7a]	859	1			T1	1		T3	14		T4	10
valid_sources[0x7b]	1694	1			T1	1		T2	16		T3	11
valid_sources[0x7c]	1390	1			T1	1		T2	4		T3	22
valid_sources[0x7d]	1070	1			T1	2		T2	16		T3	6
valid_sources[0x7e]	932	1			T1	1		T3	3		T25	1
valid_sources[0x7f]	941	1			T1	3		T2	11		T3	11
valid_sources[0x80]	862	1			T1	1		T3	6		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64410

1

T1

241

T2

243

T3

239

values[0x0]

all_enables

biggest_size

32506

1

T1

120

T2

222

T3

193

values[0x1]

all_enables

biggest_size

23339

1

T1

99

T2

165

T3

161