Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T15,T91,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T15,T91,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T15,T18,T66

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T91,T18
1	0	Covered	T11,T12,T27
1	1	Covered	T15,T91,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T66
0	1	Covered	T115,T116
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T66
0	1	Covered	T15,T18,T66
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T18,T66
1	-	Covered	T15,T18,T66

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T91,T18
0	1	Covered	T15,T91,T18
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T66
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T91,T18
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T18,T66
DebounceSt	-	0	1	0	-	-	-	Covered	T91,T140,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T91,T18
DetectSt	-	-	-	-	1	-	-	Covered	T115,T116
DetectSt	-	-	-	-	0	1	-	Covered	T15,T18,T66
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T15,T18,T66
StableSt	-	-	-	-	-	-	0	Covered	T15,T18,T66
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	302	0	0
CntIncr_A	7120944	96188	0	0
CntNoWrap_A	7120944	6421544	0	0
DetectStDropOut_A	7120944	2	0	0
DetectedOut_A	7120944	920	0	0
DetectedPulseOut_A	7120944	137	0	0
DisabledIdleSt_A	7120944	6318500	0	0
DisabledNoDetection_A	7120944	6321004	0	0
EnterDebounceSt_A	7120944	168	0	0
EnterDetectSt_A	7120944	139	0	0
EnterStableSt_A	7120944	137	0	0
PulseIsPulse_A	7120944	137	0	0
StayInStableSt	7120944	783	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	7248	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	137	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	302	0	0
T15	16806	8	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	8	0	0
T39	0	2	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	2	0	0
T91	0	1	0	0
T97	0	4	0	0
T98	0	4	0	0
T99	0	6	0	0
T100	0	2	0	0
T101	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	96188	0	0
T15	16806	132	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	269	0	0
T39	0	203	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	36	0	0
T91	0	77	0	0
T97	0	127	0	0
T98	0	187	0	0
T99	0	264	0	0
T100	0	40	0	0
T101	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421544	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7850	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	2	0	0
T115	654	1	0	0
T116	732	1	0	0
T117	488	0	0	0
T118	115984	0	0	0
T119	504	0	0	0
T120	497	0	0	0
T121	10146	0	0	0
T122	440	0	0	0
T123	510	0	0	0
T124	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	920	0	0
T15	16806	25	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	28	0	0
T39	0	10	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	2	0	0
T97	0	11	0	0
T98	0	10	0	0
T99	0	20	0	0
T100	0	7	0	0
T101	0	13	0	0
T126	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	137	0	0
T15	16806	4	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	4	0	0
T39	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T126	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6318500	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7552	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6321004	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7576	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	168	0	0
T15	16806	4	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	4	0	0
T39	0	2	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T91	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	139	0	0
T15	16806	4	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	4	0	0
T39	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T126	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	137	0	0
T15	16806	4	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	4	0	0
T39	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T126	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	137	0	0
T15	16806	4	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	4	0	0
T39	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T126	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	783	0	0
T15	16806	21	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	24	0	0
T39	0	9	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T97	0	9	0	0
T98	0	8	0	0
T99	0	17	0	0
T100	0	6	0	0
T101	0	11	0	0
T126	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	7248	0	0
T11	931	1	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	57	0	0
T16	0	10	0	0
T27	523	4	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	4	0	0
T31	8808	30	0	0
T55	0	1	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	137	0	0
T15	16806	4	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	4	0	0
T39	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T66	0	1	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T20,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T18,T20,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T37,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T37
1	0	Covered	T11,T12,T27
1	1	Covered	T18,T20,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T37,T53
0	1	Covered	T88,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T37,T53
0	1	Unreachable
1	0	Covered	T18,T37,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T20,T37
0	1	Covered	T18,T20,T37
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T37,T53
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T37
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T37,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T54,T94
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T37
DetectSt	-	-	-	-	1	-	-	Covered	T88,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T18,T37,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T37,T53
StableSt	-	-	-	-	-	-	0	Covered	T18,T37,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	149	0	0
CntIncr_A	7120944	75930	0	0
CntNoWrap_A	7120944	6421697	0	0
DetectStDropOut_A	7120944	10	0	0
DetectedOut_A	7120944	108258	0	0
DetectedPulseOut_A	7120944	49	0	0
DisabledIdleSt_A	7120944	5271261	0	0
DisabledNoDetection_A	7120944	5273816	0	0
EnterDebounceSt_A	7120944	90	0	0
EnterDetectSt_A	7120944	59	0	0
EnterStableSt_A	7120944	49	0	0
PulseIsPulse_A	7120944	49	0	0
StayInStableSt	7120944	108209	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	7248	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_sticky_sva.StableStDropOut_A	7120944	934023	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	149	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	3	0	0
T37	0	2	0	0
T43	106976	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	4	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	75930	0	0
T18	30837	77	0	0
T19	1313	0	0	0
T20	1345	297	0	0
T37	0	92	0	0
T43	106976	0	0	0
T53	0	30	0	0
T54	0	52	0	0
T61	0	84	0	0
T62	0	99	0	0
T63	0	146	0	0
T64	0	78	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421697	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	10	0	0
T88	26911	2	0	0
T89	50417	4	0	0
T90	0	2	0	0
T142	0	2	0	0
T143	691	0	0	0
T144	502	0	0	0
T145	410	0	0	0
T146	975	0	0	0
T147	410	0	0	0
T148	531	0	0	0
T149	512	0	0	0
T150	4403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	108258	0	0
T18	30837	18	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	515	0	0
T43	106976	0	0	0
T53	0	29	0	0
T61	0	294	0	0
T62	0	852	0	0
T63	0	577	0	0
T64	0	287	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	73	0	0
T133	0	156	0	0
T134	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	1	0	0
T43	106976	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5271261	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5273816	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	90	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	3	0	0
T37	0	1	0	0
T43	106976	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	59	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	1	0	0
T43	106976	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	1	0	0
T43	106976	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	1	0	0
T43	106976	0	0	0
T53	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T134	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	108209	0	0
T18	30837	17	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	514	0	0
T43	106976	0	0	0
T53	0	28	0	0
T61	0	293	0	0
T62	0	851	0	0
T63	0	575	0	0
T64	0	285	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	72	0	0
T133	0	155	0	0
T134	0	83	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	7248	0	0
T11	931	1	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	57	0	0
T16	0	10	0	0
T27	523	4	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	4	0	0
T31	8808	30	0	0
T55	0	1	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	934023	0	0
T18	30837	29	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T37	0	86	0	0
T43	106976	0	0	0
T53	0	85	0	0
T61	0	257	0	0
T62	0	153	0	0
T63	0	402	0	0
T64	0	691	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	9	0	0
T133	0	124	0	0
T134	0	363	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T20,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T18,T20,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T20,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T37
1	0	Covered	T11,T12,T13
1	1	Covered	T18,T20,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T37,T53,T54
0	1	Covered	T18,T20,T37
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T37,T53,T54
0	1	Unreachable
1	0	Covered	T37,T53,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T20,T37
0	1	Covered	T18,T20,T37
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T37
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T37
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T37,T134
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T37
DetectSt	-	-	-	-	1	-	-	Covered	T18,T20,T37
DetectSt	-	-	-	-	0	1	-	Covered	T37,T53,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T53,T54
StableSt	-	-	-	-	-	-	0	Covered	T37,T53,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	153	0	0
CntIncr_A	7120944	83603	0	0
CntNoWrap_A	7120944	6421693	0	0
DetectStDropOut_A	7120944	12	0	0
DetectedOut_A	7120944	318480	0	0
DetectedPulseOut_A	7120944	45	0	0
DisabledIdleSt_A	7120944	5271261	0	0
DisabledNoDetection_A	7120944	5273816	0	0
EnterDebounceSt_A	7120944	96	0	0
EnterDetectSt_A	7120944	57	0	0
EnterStableSt_A	7120944	45	0	0
PulseIsPulse_A	7120944	45	0	0
StayInStableSt	7120944	318435	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_sticky_sva.StableStDropOut_A	7120944	620670	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	153	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	5	0	0
T37	0	6	0	0
T43	106976	0	0	0
T53	0	2	0	0
T54	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	4	0	0
T64	0	8	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	83603	0	0
T18	30837	12	0	0
T19	1313	0	0	0
T20	1345	66	0	0
T37	0	388	0	0
T43	106976	0	0	0
T53	0	12	0	0
T54	0	24	0	0
T61	0	78	0	0
T62	0	42	0	0
T63	0	172	0	0
T64	0	363	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	62	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421693	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	12	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	2	0	0
T37	0	1	0	0
T43	106976	0	0	0
T64	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0
T118	0	1	0	0
T134	0	1	0	0
T151	0	1	0	0
T152	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	318480	0	0
T37	1149	1	0	0
T53	727	2	0	0
T54	692	49	0	0
T61	0	463	0	0
T62	0	284	0	0
T63	0	552	0	0
T64	0	542	0	0
T65	0	123	0	0
T74	28688	0	0	0
T130	14756	0	0	0
T132	0	8	0	0
T133	0	145	0	0
T135	446	0	0	0
T136	9476	0	0	0
T137	522	0	0	0
T138	2176	0	0	0
T139	516	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	45	0	0
T37	1149	1	0	0
T53	727	1	0	0
T54	692	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T74	28688	0	0	0
T130	14756	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T135	446	0	0	0
T136	9476	0	0	0
T137	522	0	0	0
T138	2176	0	0	0
T139	516	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5271261	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5273816	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	96	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	3	0	0
T37	0	4	0	0
T43	106976	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	4	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	57	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	2	0	0
T37	0	2	0	0
T43	106976	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	4	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	45	0	0
T37	1149	1	0	0
T53	727	1	0	0
T54	692	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T74	28688	0	0	0
T130	14756	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T135	446	0	0	0
T136	9476	0	0	0
T137	522	0	0	0
T138	2176	0	0	0
T139	516	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	45	0	0
T37	1149	1	0	0
T53	727	1	0	0
T54	692	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	2	0	0
T65	0	1	0	0
T74	28688	0	0	0
T130	14756	0	0	0
T132	0	1	0	0
T133	0	1	0	0
T135	446	0	0	0
T136	9476	0	0	0
T137	522	0	0	0
T138	2176	0	0	0
T139	516	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	318435	0	0
T53	727	1	0	0
T54	692	48	0	0
T61	0	462	0	0
T62	0	283	0	0
T63	0	550	0	0
T64	0	540	0	0
T65	0	122	0	0
T74	28688	0	0	0
T130	14756	0	0	0
T132	0	7	0	0
T133	0	144	0	0
T136	9476	0	0	0
T137	522	0	0	0
T138	2176	0	0	0
T139	516	0	0	0
T153	0	79	0	0
T154	28383	0	0	0
T155	576	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	620670	0	0
T37	1149	86	0	0
T53	727	131	0	0
T54	692	47	0	0
T61	0	87	0	0
T62	0	775	0	0
T63	0	408	0	0
T64	0	134	0	0
T65	0	110	0	0
T74	28688	0	0	0
T130	14756	0	0	0
T132	0	145	0	0
T133	0	125	0	0
T135	446	0	0	0
T136	9476	0	0	0
T137	522	0	0	0
T138	2176	0	0	0
T139	516	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T13,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T20,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T18,T20,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T20,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T37
1	0	Covered	T11,T13,T27
1	1	Covered	T18,T20,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T37
0	1	Covered	T54,T64,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T37
0	1	Unreachable
1	0	Covered	T18,T20,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T20,T37
0	1	Covered	T18,T20,T37
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T37
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T37
IdleSt	0	-	-	-	-	-	-	Covered	T11,T13,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T94,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T37
DetectSt	-	-	-	-	1	-	-	Covered	T54,T64,T86
DetectSt	-	-	-	-	0	1	-	Covered	T18,T20,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T37
StableSt	-	-	-	-	-	-	0	Covered	T18,T20,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	144	0	0
CntIncr_A	7120944	130240	0	0
CntNoWrap_A	7120944	6421702	0	0
DetectStDropOut_A	7120944	7	0	0
DetectedOut_A	7120944	449348	0	0
DetectedPulseOut_A	7120944	46	0	0
DisabledIdleSt_A	7120944	5271261	0	0
DisabledNoDetection_A	7120944	5273816	0	0
EnterDebounceSt_A	7120944	91	0	0
EnterDetectSt_A	7120944	53	0	0
EnterStableSt_A	7120944	46	0	0
PulseIsPulse_A	7120944	46	0	0
StayInStableSt	7120944	449302	0	0
gen_high_event_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_sticky_sva.StableStDropOut_A	7120944	396418	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	144	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	2	0	0
T37	0	2	0	0
T43	106976	0	0	0
T53	0	1	0	0
T54	0	4	0	0
T61	0	2	0	0
T62	0	5	0	0
T63	0	4	0	0
T64	0	10	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	130240	0	0
T18	30837	25	0	0
T19	1313	0	0	0
T20	1345	94	0	0
T37	0	87	0	0
T43	106976	0	0	0
T53	0	77	0	0
T54	0	34	0	0
T61	0	70	0	0
T62	0	465	0	0
T63	0	182	0	0
T64	0	198	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421702	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	7	0	0
T54	692	1	0	0
T64	258355	3	0	0
T74	28688	0	0	0
T86	0	2	0	0
T99	809	0	0	0
T118	0	1	0	0
T138	2176	0	0	0
T139	516	0	0	0
T154	28383	0	0	0
T155	576	0	0	0
T156	457	0	0	0
T157	981	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	449348	0	0
T18	30837	21	0	0
T19	1313	0	0	0
T20	1345	252	0	0
T37	0	284	0	0
T43	106976	0	0	0
T54	0	1	0	0
T61	0	277	0	0
T63	0	855	0	0
T64	0	137	0	0
T65	0	27	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	48	0	0
T134	0	314	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	1	0	0
T37	0	1	0	0
T43	106976	0	0	0
T54	0	1	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T134	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5271261	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5273816	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	91	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	1	0	0
T37	0	1	0	0
T43	106976	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T61	0	1	0	0
T62	0	5	0	0
T63	0	2	0	0
T64	0	6	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T94	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	1	0	0
T37	0	1	0	0
T43	106976	0	0	0
T54	0	2	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	4	0	0
T65	0	1	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T134	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	1	0	0
T37	0	1	0	0
T43	106976	0	0	0
T54	0	1	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T134	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	1	0	0
T37	0	1	0	0
T43	106976	0	0	0
T54	0	1	0	0
T61	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	1	0	0
T134	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	449302	0	0
T18	30837	20	0	0
T19	1313	0	0	0
T20	1345	251	0	0
T37	0	283	0	0
T43	106976	0	0	0
T61	0	276	0	0
T63	0	853	0	0
T64	0	136	0	0
T65	0	26	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	47	0	0
T134	0	312	0	0
T153	0	175	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	396418	0	0
T18	30837	91	0	0
T19	1313	0	0	0
T20	1345	199	0	0
T37	0	335	0	0
T43	106976	0	0	0
T54	0	61	0	0
T61	0	297	0	0
T63	0	105	0	0
T64	0	256	0	0
T65	0	268	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T132	0	64	0	0
T134	0	62	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T11,T14,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T14,T18
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T14,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T45
0	1	Covered	T146,T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T45
0	1	Covered	T11,T157,T65
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T14,T45
1	-	Covered	T11,T157,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T14,T45
0	1	Covered	T11,T14,T45
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T45
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T14,T45
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T14,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T151,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T14,T45
DetectSt	-	-	-	-	1	-	-	Covered	T146,T158
DetectSt	-	-	-	-	0	1	-	Covered	T11,T14,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T157,T65
StableSt	-	-	-	-	-	-	0	Covered	T11,T14,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	105	0	0
CntIncr_A	7120944	4528	0	0
CntNoWrap_A	7120944	6421741	0	0
DetectStDropOut_A	7120944	2	0	0
DetectedOut_A	7120944	7270	0	0
DetectedPulseOut_A	7120944	49	0	0
DisabledIdleSt_A	7120944	6278808	0	0
DisabledNoDetection_A	7120944	6281307	0	0
EnterDebounceSt_A	7120944	54	0	0
EnterDetectSt_A	7120944	51	0	0
EnterStableSt_A	7120944	49	0	0
PulseIsPulse_A	7120944	49	0	0
StayInStableSt	7120944	7200	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	105	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T62	0	2	0	0
T65	0	2	0	0
T87	0	4	0	0
T146	0	4	0	0
T157	0	4	0	0
T160	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	4528	0	0
T11	931	54	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	75	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	26	0	0
T45	0	58	0	0
T62	0	70	0	0
T65	0	13	0	0
T87	0	66	0	0
T146	0	128	0	0
T157	0	152	0	0
T160	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421741	0	0
T11	931	528	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	679	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	2	0	0
T146	975	1	0	0
T147	410	0	0	0
T148	531	0	0	0
T158	24704	1	0	0
T161	433	0	0	0
T162	708	0	0	0
T163	38833	0	0	0
T164	494	0	0	0
T165	14883	0	0	0
T166	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	7270	0	0
T11	931	234	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	43	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	39	0	0
T45	0	141	0	0
T62	0	40	0	0
T65	0	43	0	0
T87	0	84	0	0
T146	0	44	0	0
T157	0	159	0	0
T160	0	89	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T87	0	2	0	0
T146	0	1	0	0
T157	0	2	0	0
T160	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6278808	0	0
T11	931	3	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	3	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6281307	0	0
T11	931	3	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	3	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	54	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T87	0	2	0	0
T146	0	2	0	0
T157	0	2	0	0
T160	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	51	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T87	0	2	0	0
T146	0	2	0	0
T157	0	2	0	0
T160	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T87	0	2	0	0
T146	0	1	0	0
T157	0	2	0	0
T160	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T87	0	2	0	0
T146	0	1	0	0
T157	0	2	0	0
T160	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	7200	0	0
T11	931	233	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	41	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	37	0	0
T45	0	139	0	0
T62	0	38	0	0
T65	0	42	0	0
T87	0	81	0	0
T146	0	43	0	0
T157	0	156	0	0
T160	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	27	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T65	0	1	0	0
T87	0	1	0	0
T146	0	1	0	0
T151	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T167	0	2	0	0
T168	0	1	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T13,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T11,T12,T27
1	1	Covered	T13,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T44,T80,T81
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T45,T65,T170
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T17
1	-	Covered	T45,T65,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T62,T92,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T44,T80,T81
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T65,T170
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	145	0	0
CntIncr_A	7120944	25443	0	0
CntNoWrap_A	7120944	6421701	0	0
DetectStDropOut_A	7120944	5	0	0
DetectedOut_A	7120944	5369	0	0
DetectedPulseOut_A	7120944	64	0	0
DisabledIdleSt_A	7120944	6291062	0	0
DisabledNoDetection_A	7120944	6293563	0	0
EnterDebounceSt_A	7120944	77	0	0
EnterDetectSt_A	7120944	69	0	0
EnterStableSt_A	7120944	64	0	0
PulseIsPulse_A	7120944	64	0	0
StayInStableSt	7120944	5271	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	2927	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	145	0	0
T13	554	2	0	0
T14	1082	0	0	0
T15	16806	2	0	0
T16	14020	0	0	0
T17	0	2	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T55	425	0	0	0
T62	0	1	0	0
T65	0	10	0	0
T126	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	25443	0	0
T13	554	100	0	0
T14	1082	0	0	0
T15	16806	3340	0	0
T16	14020	0	0	0
T17	0	23	0	0
T18	0	67	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	17871	0	0
T44	0	26	0	0
T45	0	58	0	0
T55	425	0	0	0
T62	0	70	0	0
T65	0	284	0	0
T126	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421701	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	151	0	0
T14	1082	681	0	0
T15	16806	7856	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5	0	0
T37	1149	0	0	0
T41	26032	0	0	0
T44	501	1	0	0
T52	17805	0	0	0
T80	590	1	0	0
T81	0	1	0	0
T98	3569	0	0	0
T135	446	0	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	406	0	0	0
T174	577	0	0	0
T175	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5369	0	0
T13	554	45	0	0
T14	1082	0	0	0
T15	16806	190	0	0
T16	14020	0	0	0
T17	0	145	0	0
T18	0	49	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	41	0	0
T45	0	102	0	0
T55	425	0	0	0
T65	0	427	0	0
T126	0	39	0	0
T170	0	154	0	0
T176	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	64	0	0
T13	554	1	0	0
T14	1082	0	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	5	0	0
T126	0	1	0	0
T170	0	2	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6291062	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	4	0	0
T14	1082	681	0	0
T15	16806	4259	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6293563	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	4	0	0
T14	1082	682	0	0
T15	16806	4282	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	77	0	0
T13	554	1	0	0
T14	1082	0	0	0
T15	16806	2	0	0
T16	14020	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T65	0	5	0	0
T126	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	69	0	0
T13	554	1	0	0
T14	1082	0	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	5	0	0
T126	0	1	0	0
T170	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	64	0	0
T13	554	1	0	0
T14	1082	0	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	5	0	0
T126	0	1	0	0
T170	0	2	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	64	0	0
T13	554	1	0	0
T14	1082	0	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	0	1	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	5	0	0
T126	0	1	0	0
T170	0	2	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5271	0	0
T13	554	43	0	0
T14	1082	0	0	0
T15	16806	188	0	0
T16	14020	0	0	0
T17	0	143	0	0
T18	0	47	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	39	0	0
T45	0	101	0	0
T55	425	0	0	0
T65	0	420	0	0
T126	0	37	0	0
T170	0	151	0	0
T176	0	93	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	2927	0	0
T11	931	2	0	0
T12	632	1	0	0
T13	554	1	0	0
T14	1082	1	0	0
T15	16806	41	0	0
T17	0	1	0	0
T27	523	5	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	4	0	0
T31	8808	0	0	0
T55	0	1	0	0
T57	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	29	0	0
T37	1149	0	0	0
T41	26032	0	0	0
T44	501	0	0	0
T45	952	1	0	0
T52	17805	0	0	0
T65	0	3	0	0
T86	0	2	0	0
T98	3569	0	0	0
T135	446	0	0	0
T146	0	2	0	0
T167	0	1	0	0
T168	0	3	0	0
T169	0	2	0	0
T170	0	1	0	0
T173	406	0	0	0
T174	577	0	0	0
T175	524	0	0	0
T176	0	1	0	0
T177	0	1	0	0