Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T17,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T11,T17,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T17,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T17,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T45
0	1	Covered	T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T45
0	1	Covered	T11,T17,T45
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T17,T45
1	-	Covered	T11,T17,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T17,T45
0	1	Covered	T11,T17,T45
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T17,T45
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T17,T45
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T17,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T126,T178,T179
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T17,T45
DetectSt	-	-	-	-	1	-	-	Covered	T87
DetectSt	-	-	-	-	0	1	-	Covered	T11,T17,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T17,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T17,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	96	0	0
CntIncr_A	7120944	41457	0	0
CntNoWrap_A	7120944	6421750	0	0
DetectStDropOut_A	7120944	1	0	0
DetectedOut_A	7120944	3631	0	0
DetectedPulseOut_A	7120944	45	0	0
DisabledIdleSt_A	7120944	6192586	0	0
DisabledNoDetection_A	7120944	6195084	0	0
EnterDebounceSt_A	7120944	50	0	0
EnterDetectSt_A	7120944	46	0	0
EnterStableSt_A	7120944	45	0	0
PulseIsPulse_A	7120944	45	0	0
StayInStableSt	7120944	3563	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	96	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	4	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	4	0	0
T62	0	2	0	0
T86	0	4	0	0
T87	0	4	0	0
T88	0	2	0	0
T126	0	1	0	0
T140	0	4	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	41457	0	0
T11	931	54	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	46	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	116	0	0
T62	0	70	0	0
T86	0	28891	0	0
T87	0	66	0	0
T88	0	47	0	0
T126	0	34	0	0
T140	0	70	0	0
T157	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421750	0	0
T11	931	528	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1	0	0
T87	20185	1	0	0
T92	496	0	0	0
T180	754	0	0	0
T181	504	0	0	0
T182	489	0	0	0
T183	407	0	0	0
T184	10764	0	0	0
T185	1330	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3631	0	0
T11	931	194	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	79	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	142	0	0
T62	0	41	0	0
T86	0	89	0	0
T87	0	98	0	0
T88	0	40	0	0
T140	0	85	0	0
T151	0	181	0	0
T157	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	45	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T140	0	2	0	0
T151	0	2	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6192586	0	0
T11	931	3	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6195084	0	0
T11	931	3	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	50	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T126	0	1	0	0
T140	0	2	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T140	0	2	0	0
T151	0	2	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	45	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T140	0	2	0	0
T151	0	2	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	45	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	2	0	0
T62	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T88	0	1	0	0
T140	0	2	0	0
T151	0	2	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3563	0	0
T11	931	193	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	76	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	139	0	0
T62	0	39	0	0
T81	0	118	0	0
T86	0	85	0	0
T87	0	96	0	0
T88	0	39	0	0
T140	0	83	0	0
T151	0	178	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	21	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	1	0	0
T88	0	1	0	0
T140	0	2	0	0
T151	0	1	0	0
T157	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T39,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T18,T39,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T18,T39,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T39,T44
1	0	Covered	T11,T13,T27
1	1	Covered	T18,T39,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T39,T44
0	1	Covered	T80,T188,T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T39,T44
0	1	Covered	T18,T39,T62
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T39,T44
1	-	Covered	T18,T39,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T39,T44
0	1	Covered	T18,T39,T44
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T39,T44
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T39,T44
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T39,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T190
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T39,T44
DetectSt	-	-	-	-	1	-	-	Covered	T80,T188,T189
DetectSt	-	-	-	-	0	1	-	Covered	T18,T39,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T39,T62
StableSt	-	-	-	-	-	-	0	Covered	T18,T39,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	144	0	0
CntIncr_A	7120944	20347	0	0
CntNoWrap_A	7120944	6421702	0	0
DetectStDropOut_A	7120944	4	0	0
DetectedOut_A	7120944	13790	0	0
DetectedPulseOut_A	7120944	67	0	0
DisabledIdleSt_A	7120944	6346624	0	0
DisabledNoDetection_A	7120944	6349126	0	0
EnterDebounceSt_A	7120944	73	0	0
EnterDetectSt_A	7120944	71	0	0
EnterStableSt_A	7120944	67	0	0
PulseIsPulse_A	7120944	67	0	0
StayInStableSt	7120944	13692	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	3355	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	144	0	0
T18	30837	4	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	4	0	0
T43	106976	0	0	0
T44	0	2	0	0
T62	0	4	0	0
T65	0	4	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	2	0	0
T126	0	6	0	0
T155	0	2	0	0
T160	0	2	0	0
T191	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	20347	0	0
T18	30837	138	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	38	0	0
T43	106976	0	0	0
T44	0	26	0	0
T62	0	76	0	0
T65	0	172	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	33	0	0
T126	0	101	0	0
T155	0	44	0	0
T160	0	27	0	0
T191	0	6522	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421702	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	4	0	0
T80	590	1	0	0
T188	3646	1	0	0
T189	0	1	0	0
T192	0	1	0	0
T193	17590	0	0	0
T194	639	0	0	0
T195	1927	0	0	0
T196	1237	0	0	0
T197	427	0	0	0
T198	10514	0	0	0
T199	867	0	0	0
T200	14560	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	13790	0	0
T18	30837	82	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	108	0	0
T43	106976	0	0	0
T44	0	66	0	0
T62	0	97	0	0
T65	0	105	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	43	0	0
T126	0	180	0	0
T155	0	43	0	0
T160	0	178	0	0
T191	0	151	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	67	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	2	0	0
T43	106976	0	0	0
T44	0	1	0	0
T62	0	2	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	1	0	0
T126	0	3	0	0
T155	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6346624	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6349126	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	73	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	2	0	0
T43	106976	0	0	0
T44	0	1	0	0
T62	0	2	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	1	0	0
T126	0	3	0	0
T155	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	71	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	2	0	0
T43	106976	0	0	0
T44	0	1	0	0
T62	0	2	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	1	0	0
T126	0	3	0	0
T155	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	67	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	2	0	0
T43	106976	0	0	0
T44	0	1	0	0
T62	0	2	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	1	0	0
T126	0	3	0	0
T155	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	67	0	0
T18	30837	2	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	2	0	0
T43	106976	0	0	0
T44	0	1	0	0
T62	0	2	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	1	0	0
T126	0	3	0	0
T155	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	13692	0	0
T18	30837	79	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	105	0	0
T43	106976	0	0	0
T44	0	64	0	0
T62	0	94	0	0
T65	0	102	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T92	0	41	0	0
T126	0	175	0	0
T155	0	41	0	0
T160	0	177	0	0
T191	0	148	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3355	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	57	0	0
T17	0	2	0	0
T27	523	6	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	4	0	0
T31	8808	0	0	0
T55	0	4	0	0
T57	0	2	0	0
T58	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	35	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T39	0	1	0	0
T43	106976	0	0	0
T62	0	1	0	0
T65	0	1	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T86	0	1	0	0
T126	0	1	0	0
T146	0	1	0	0
T151	0	2	0	0
T160	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T13,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T13,T27
1	1	Covered	T11,T13,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T14,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T13,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T14,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T11,T27,T28
1	1	Covered	T13,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T18
0	1	Covered	T18,T51,T62
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T18
1	-	Covered	T18,T51,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T14,T18
0	1	Covered	T13,T14,T15
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T18
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T62,T88,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T201
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T51,T62
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	162	0	0
CntIncr_A	7120944	108421	0	0
CntNoWrap_A	7120944	6421684	0	0
DetectStDropOut_A	7120944	1	0	0
DetectedOut_A	7120944	96279	0	0
DetectedPulseOut_A	7120944	76	0	0
DisabledIdleSt_A	7120944	6116754	0	0
DisabledNoDetection_A	7120944	6119241	0	0
EnterDebounceSt_A	7120944	86	0	0
EnterDetectSt_A	7120944	77	0	0
EnterStableSt_A	7120944	76	0	0
PulseIsPulse_A	7120944	76	0	0
StayInStableSt	7120944	96160	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	162	0	0
T13	554	2	0	0
T14	1082	2	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	2	0	0
T51	0	2	0	0
T55	425	0	0	0
T62	0	5	0	0
T65	0	6	0	0
T126	0	2	0	0
T160	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	108421	0	0
T13	554	100	0	0
T14	1082	75	0	0
T15	16806	3302	0	0
T16	14020	0	0	0
T18	0	69	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	77	0	0
T43	0	17871	0	0
T51	0	28	0	0
T55	425	0	0	0
T62	0	146	0	0
T65	0	185	0	0
T126	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421684	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	151	0	0
T14	1082	679	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1	0	0
T158	24704	0	0	0
T161	433	0	0	0
T162	708	0	0	0
T163	38833	0	0	0
T164	494	0	0	0
T201	103983	1	0	0
T202	11655	0	0	0
T203	423	0	0	0
T204	502	0	0	0
T205	496	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	96279	0	0
T13	554	45	0	0
T14	1082	466	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	102	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	294	0	0
T43	0	88696	0	0
T51	0	80	0	0
T55	425	0	0	0
T62	0	77	0	0
T65	0	511	0	0
T126	0	39	0	0
T160	0	126	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	76	0	0
T13	554	1	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	2	0	0
T65	0	3	0	0
T126	0	1	0	0
T160	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6116754	0	0
T11	931	530	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	4550	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6119241	0	0
T11	931	531	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	4574	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	86	0	0
T13	554	1	0	0
T14	1082	1	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	3	0	0
T65	0	3	0	0
T126	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	77	0	0
T13	554	1	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	2	0	0
T65	0	3	0	0
T126	0	1	0	0
T160	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	76	0	0
T13	554	1	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	2	0	0
T65	0	3	0	0
T126	0	1	0	0
T160	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	76	0	0
T13	554	1	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	2	0	0
T65	0	3	0	0
T126	0	1	0	0
T160	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	96160	0	0
T13	554	43	0	0
T14	1082	464	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T18	0	101	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	292	0	0
T43	0	88694	0	0
T51	0	79	0	0
T55	425	0	0	0
T62	0	74	0	0
T65	0	507	0	0
T126	0	37	0	0
T160	0	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	32	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T20	1345	0	0	0
T43	106976	0	0	0
T51	0	1	0	0
T62	0	1	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T69	803	0	0	0
T70	423	0	0	0
T71	55660	0	0	0
T86	0	4	0	0
T87	0	1	0	0
T140	0	1	0	0
T146	0	2	0	0
T160	0	1	0	0
T206	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T13,T27
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T18,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T11,T18,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T18,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T15
1	0	Covered	T27,T28,T30
1	1	Covered	T11,T18,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T18,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T18,T44
0	1	Covered	T11,T160,T191
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T18,T44
1	-	Covered	T11,T160,T191

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T18,T44
0	1	Covered	T11,T18,T44
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T18,T44
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T18,T44
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T18,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T168,T207
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T18,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T18,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T160,T191
StableSt	-	-	-	-	-	-	0	Covered	T11,T18,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	95	0	0
CntIncr_A	7120944	54913	0	0
CntNoWrap_A	7120944	6421751	0	0
DetectStDropOut_A	7120944	0	0	0
DetectedOut_A	7120944	3408	0	0
DetectedPulseOut_A	7120944	46	0	0
DisabledIdleSt_A	7120944	6252229	0	0
DisabledNoDetection_A	7120944	6254720	0	0
EnterDebounceSt_A	7120944	49	0	0
EnterDetectSt_A	7120944	46	0	0
EnterStableSt_A	7120944	46	0	0
PulseIsPulse_A	7120944	46	0	0
StayInStableSt	7120944	3339	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	6953	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	95	0	0
T11	931	4	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	2	0	0
T62	0	2	0	0
T87	0	2	0	0
T140	0	4	0	0
T160	0	2	0	0
T191	0	2	0	0
T208	0	4	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	54913	0	0
T11	931	108	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	69	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	26	0	0
T62	0	70	0	0
T87	0	33	0	0
T140	0	70	0	0
T160	0	27	0	0
T191	0	75	0	0
T208	0	76	0	0
T209	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421751	0	0
T11	931	526	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3408	0	0
T11	931	178	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	41	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	39	0	0
T62	0	41	0	0
T87	0	282	0	0
T140	0	79	0	0
T160	0	73	0	0
T191	0	212	0	0
T208	0	88	0	0
T209	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T62	0	1	0	0
T87	0	1	0	0
T140	0	2	0	0
T160	0	1	0	0
T191	0	1	0	0
T208	0	2	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6252229	0	0
T11	931	3	0	0
T12	632	231	0	0
T13	554	4	0	0
T14	1082	681	0	0
T15	16806	4550	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6254720	0	0
T11	931	3	0	0
T12	632	232	0	0
T13	554	4	0	0
T14	1082	682	0	0
T15	16806	4574	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T62	0	1	0	0
T87	0	1	0	0
T140	0	2	0	0
T160	0	1	0	0
T191	0	1	0	0
T208	0	2	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T62	0	1	0	0
T87	0	1	0	0
T140	0	2	0	0
T160	0	1	0	0
T191	0	1	0	0
T208	0	2	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T62	0	1	0	0
T87	0	1	0	0
T140	0	2	0	0
T160	0	1	0	0
T191	0	1	0	0
T208	0	2	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	46	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T62	0	1	0	0
T87	0	1	0	0
T140	0	2	0	0
T160	0	1	0	0
T191	0	1	0	0
T208	0	2	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3339	0	0
T11	931	175	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	39	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	37	0	0
T62	0	39	0	0
T87	0	280	0	0
T140	0	76	0	0
T160	0	72	0	0
T191	0	211	0	0
T208	0	85	0	0
T209	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6953	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	44	0	0
T16	0	9	0	0
T27	523	5	0	0
T28	510	1	0	0
T29	468	0	0	0
T30	523	5	0	0
T31	8808	21	0	0
T46	0	28	0	0
T55	0	2	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	22	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T86	0	2	0	0
T140	0	1	0	0
T146	0	2	0	0
T160	0	1	0	0
T167	0	2	0	0
T191	0	1	0	0
T208	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T27
1	1	Covered	T11,T12,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T17,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T17
1	0	Covered	T11,T12,T27
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T39,T171,T189
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T14,T18,T43
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T18
1	-	Covered	T14,T18,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T18
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T18,T92
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	1	-	-	Covered	T39,T171,T189
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T18,T43
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	188	0	0
CntIncr_A	7120944	44223	0	0
CntNoWrap_A	7120944	6421658	0	0
DetectStDropOut_A	7120944	3	0	0
DetectedOut_A	7120944	90237	0	0
DetectedPulseOut_A	7120944	84	0	0
DisabledIdleSt_A	7120944	6183626	0	0
DisabledNoDetection_A	7120944	6186111	0	0
EnterDebounceSt_A	7120944	102	0	0
EnterDetectSt_A	7120944	87	0	0
EnterStableSt_A	7120944	84	0	0
PulseIsPulse_A	7120944	84	0	0
StayInStableSt	7120944	90117	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	47	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	188	0	0
T14	1082	2	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	3	0	0
T18	0	5	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	6	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	4767	0	0	0
T51	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	2	0	0
T126	0	4	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	44223	0	0
T14	1082	75	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	46	0	0
T18	0	205	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	231	0	0
T43	0	17871	0	0
T44	0	26	0	0
T46	4767	0	0	0
T51	0	28	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	38	0	0
T126	0	67	0	0
T155	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421658	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	679	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3	0	0
T39	45220	1	0	0
T40	15925	0	0	0
T42	25175	0	0	0
T44	501	0	0	0
T45	952	0	0	0
T52	17805	0	0	0
T171	0	1	0	0
T189	0	1	0	0
T212	434	0	0	0
T213	437	0	0	0
T214	424	0	0	0
T215	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	90237	0	0
T14	1082	40	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	39	0	0
T18	0	103	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	88	0	0
T43	0	70782	0	0
T44	0	1	0	0
T46	4767	0	0	0
T51	0	47	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	38	0	0
T126	0	145	0	0
T155	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	84	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	2	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T51	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	1	0	0
T126	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6183626	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	3	0	0
T15	16806	7567	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6186111	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	3	0	0
T15	16806	7591	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	102	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	2	0	0
T18	0	3	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T51	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	1	0	0
T126	0	2	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	87	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	2	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T51	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	1	0	0
T126	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	84	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	2	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T51	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	1	0	0
T126	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	84	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	2	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T51	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	1	0	0
T126	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	90117	0	0
T14	1082	39	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	37	0	0
T18	0	100	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	85	0	0
T43	0	70781	0	0
T46	4767	0	0	0
T51	0	45	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	36	0	0
T126	0	142	0	0
T155	0	41	0	0
T157	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	47	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	2	0	0
T126	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T17,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T14,T17,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T14,T17,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T11,T27,T29
1	1	Covered	T14,T17,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T17,T18
0	1	Covered	T17,T18,T39
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T17,T18
1	-	Covered	T17,T18,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T17,T18
0	1	Covered	T14,T17,T18
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T17,T18
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T17,T18
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T17,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T186,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T14,T17,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T18,T39
StableSt	-	-	-	-	-	-	0	Covered	T14,T17,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	124	0	0
CntIncr_A	7120944	25950	0	0
CntNoWrap_A	7120944	6421722	0	0
DetectStDropOut_A	7120944	0	0	0
DetectedOut_A	7120944	6594	0	0
DetectedPulseOut_A	7120944	60	0	0
DisabledIdleSt_A	7120944	6203001	0	0
DisabledNoDetection_A	7120944	6205492	0	0
EnterDebounceSt_A	7120944	64	0	0
EnterDetectSt_A	7120944	60	0	0
EnterStableSt_A	7120944	60	0	0
PulseIsPulse_A	7120944	60	0	0
StayInStableSt	7120944	6504	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	6613	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	124	0	0
T14	1082	2	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	2	0	0
T18	0	2	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	6	0	0
T43	0	2	0	0
T44	0	2	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	6	0	0
T157	0	2	0	0
T160	0	2	0	0
T191	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	25950	0	0
T14	1082	75	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	23	0	0
T18	0	69	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	173	0	0
T43	0	17871	0	0
T44	0	26	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	185	0	0
T157	0	76	0	0
T160	0	27	0	0
T191	0	150	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421722	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	679	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6594	0	0
T14	1082	349	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	83	0	0
T18	0	43	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	161	0	0
T43	0	41	0	0
T44	0	38	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	159	0	0
T157	0	116	0	0
T160	0	154	0	0
T191	0	158	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	60	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	3	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6203001	0	0
T11	931	530	0	0
T12	632	3	0	0
T13	554	153	0	0
T14	1082	3	0	0
T15	16806	4550	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6205492	0	0
T11	931	531	0	0
T12	632	3	0	0
T13	554	154	0	0
T14	1082	3	0	0
T15	16806	4574	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	64	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	3	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	60	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	3	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	60	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	3	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	60	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	3	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6504	0	0
T14	1082	347	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	82	0	0
T18	0	42	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	157	0	0
T43	0	39	0	0
T44	0	36	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	155	0	0
T157	0	114	0	0
T160	0	152	0	0
T191	0	156	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6613	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	45	0	0
T16	0	12	0	0
T27	523	6	0	0
T28	510	0	0	0
T29	468	1	0	0
T30	523	4	0	0
T31	8808	26	0	0
T46	0	27	0	0
T55	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	29	0	0
T17	601	1	0	0
T18	30837	1	0	0
T19	1313	0	0	0
T39	0	2	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T65	0	2	0	0
T66	731	0	0	0
T67	449	0	0	0
T68	521	0	0	0
T86	0	1	0	0
T102	526	0	0	0
T151	0	1	0	0
T170	0	1	0	0
T191	0	2	0	0
T210	0	1	0	0
T211	0	2	0	0