Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T13,T14

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T12,T13,T14

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T14,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Covered	T11,T27,T29
1	1	Covered	T12,T13,T14

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T158
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T14,T15,T17
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T14,T15
1	-	Covered	T14,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T13,T14
0	1	Covered	T12,T13,T14
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T15
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T13,T14
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T14,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T168,T216
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T13,T14
DetectSt	-	-	-	-	1	-	-	Covered	T158
DetectSt	-	-	-	-	0	1	-	Covered	T12,T14,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T12,T14,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	153	0	0
CntIncr_A	7120944	4028	0	0
CntNoWrap_A	7120944	6421693	0	0
DetectStDropOut_A	7120944	1	0	0
DetectedOut_A	7120944	5906	0	0
DetectedPulseOut_A	7120944	73	0	0
DisabledIdleSt_A	7120944	6402242	0	0
DisabledNoDetection_A	7120944	6404737	0	0
EnterDebounceSt_A	7120944	79	0	0
EnterDetectSt_A	7120944	74	0	0
EnterStableSt_A	7120944	73	0	0
PulseIsPulse_A	7120944	73	0	0
StayInStableSt	7120944	5803	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	153	0	0
T12	632	2	0	0
T13	554	1	0	0
T14	1082	4	0	0
T15	16806	2	0	0
T17	0	4	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	2	0	0
T55	425	0	0	0
T62	0	2	0	0
T126	0	4	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	4028	0	0
T12	632	76	0	0
T13	554	100	0	0
T14	1082	150	0	0
T15	16806	38	0	0
T17	0	46	0	0
T18	0	69	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	26	0	0
T55	425	0	0	0
T62	0	70	0	0
T126	0	68	0	0
T155	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421693	0	0
T11	931	530	0	0
T12	632	229	0	0
T13	554	152	0	0
T14	1082	677	0	0
T15	16806	7856	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1	0	0
T158	24704	1	0	0
T161	433	0	0	0
T162	708	0	0	0
T163	38833	0	0	0
T164	494	0	0	0
T165	14883	0	0	0
T166	422	0	0	0
T217	504	0	0	0
T218	1213	0	0	0
T219	735	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5906	0	0
T12	632	147	0	0
T13	554	0	0	0
T14	1082	139	0	0
T15	16806	113	0	0
T17	0	102	0	0
T18	0	44	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	39	0	0
T55	425	0	0	0
T62	0	61	0	0
T65	0	176	0	0
T126	0	84	0	0
T155	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	73	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T65	0	2	0	0
T126	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6402242	0	0
T11	931	530	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	7567	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6404737	0	0
T11	931	531	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	7591	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	79	0	0
T12	632	1	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T126	0	2	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	74	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T65	0	2	0	0
T126	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	73	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T65	0	2	0	0
T126	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	73	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T17	0	2	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T65	0	2	0	0
T126	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5803	0	0
T12	632	145	0	0
T13	554	0	0	0
T14	1082	137	0	0
T15	16806	112	0	0
T17	0	99	0	0
T18	0	43	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T44	0	37	0	0
T55	425	0	0	0
T62	0	59	0	0
T65	0	173	0	0
T126	0	81	0	0
T155	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	42	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	601	1	0	0
T18	0	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T126	0	1	0	0
T160	0	1	0	0
T170	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T13,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T13,T14,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T11,T27,T29
1	1	Covered	T13,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T14,T15
0	1	Covered	T14,T65,T87
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T14,T15
1	-	Covered	T14,T65,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T14,T15
0	1	Covered	T13,T14,T15
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T15
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T14,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T168,T220
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T14,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T65,T87
StableSt	-	-	-	-	-	-	0	Covered	T13,T14,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	112	0	0
CntIncr_A	7120944	9303	0	0
CntNoWrap_A	7120944	6421734	0	0
DetectStDropOut_A	7120944	0	0	0
DetectedOut_A	7120944	3448	0	0
DetectedPulseOut_A	7120944	53	0	0
DisabledIdleSt_A	7120944	6380748	0	0
DisabledNoDetection_A	7120944	6383240	0	0
EnterDebounceSt_A	7120944	59	0	0
EnterDetectSt_A	7120944	53	0	0
EnterStableSt_A	7120944	53	0	0
PulseIsPulse_A	7120944	53	0	0
StayInStableSt	7120944	3365	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	6725	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	112	0	0
T13	554	2	0	0
T14	1082	4	0	0
T15	16806	2	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	2	0	0
T55	425	0	0	0
T65	0	3	0	0
T86	0	4	0	0
T87	0	2	0	0
T140	0	2	0	0
T170	0	2	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	9303	0	0
T13	554	100	0	0
T14	1082	150	0	0
T15	16806	38	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	58	0	0
T55	425	0	0	0
T65	0	99	0	0
T86	0	40	0	0
T87	0	33	0	0
T140	0	35	0	0
T170	0	59	0	0
T191	0	6447	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421734	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	151	0	0
T14	1082	677	0	0
T15	16806	7856	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3448	0	0
T13	554	39	0	0
T14	1082	98	0	0
T15	16806	38	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	46	0	0
T55	425	0	0	0
T65	0	1	0	0
T86	0	110	0	0
T87	0	75	0	0
T140	0	54	0	0
T170	0	102	0	0
T191	0	109	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T140	0	1	0	0
T170	0	1	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6380748	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	4259	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6383240	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	4282	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	59	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	2	0	0
T86	0	2	0	0
T87	0	1	0	0
T140	0	1	0	0
T170	0	1	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T140	0	1	0	0
T170	0	1	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T140	0	1	0	0
T170	0	1	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T87	0	1	0	0
T140	0	1	0	0
T170	0	1	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3365	0	0
T13	554	37	0	0
T14	1082	95	0	0
T15	16806	36	0	0
T16	14020	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T45	0	44	0	0
T55	425	0	0	0
T86	0	107	0	0
T87	0	74	0	0
T88	0	86	0	0
T140	0	52	0	0
T170	0	100	0	0
T191	0	107	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6725	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	1	0	0
T14	1082	2	0	0
T15	16806	49	0	0
T16	0	17	0	0
T27	523	4	0	0
T28	510	0	0	0
T29	468	1	0	0
T30	523	3	0	0
T31	8808	22	0	0
T55	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	22	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T146	0	1	0	0
T168	0	2	0	0
T177	0	1	0	0
T211	0	1	0	0
T221	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T27
1	1	Covered	T11,T12,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T14,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T12,T14,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T14,T15

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T15
1	0	Covered	T11,T27,T29
1	1	Covered	T12,T14,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T65,T222,T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T15
0	1	Covered	T14,T43,T39
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T14,T15
1	-	Covered	T14,T43,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T14,T15
0	1	Covered	T12,T14,T15
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T14,T15
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T14,T15
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T14,T15
DebounceSt	-	0	1	0	-	-	-	Covered	T126,T157,T160
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T14,T15
DetectSt	-	-	-	-	1	-	-	Covered	T65,T222,T201
DetectSt	-	-	-	-	0	1	-	Covered	T12,T14,T15
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T43,T39
StableSt	-	-	-	-	-	-	0	Covered	T12,T14,T15
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	175	0	0
CntIncr_A	7120944	86762	0	0
CntNoWrap_A	7120944	6421671	0	0
DetectStDropOut_A	7120944	3	0	0
DetectedOut_A	7120944	33781	0	0
DetectedPulseOut_A	7120944	78	0	0
DisabledIdleSt_A	7120944	6152093	0	0
DisabledNoDetection_A	7120944	6154582	0	0
EnterDebounceSt_A	7120944	94	0	0
EnterDetectSt_A	7120944	81	0	0
EnterStableSt_A	7120944	78	0	0
PulseIsPulse_A	7120944	78	0	0
StayInStableSt	7120944	33668	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	175	0	0
T12	632	2	0	0
T13	554	0	0	0
T14	1082	4	0	0
T15	16806	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T51	0	2	0	0
T55	425	0	0	0
T62	0	2	0	0
T126	0	1	0	0
T155	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	86762	0	0
T12	632	76	0	0
T13	554	0	0	0
T14	1082	150	0	0
T15	16806	38	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	19	0	0
T43	0	17871	0	0
T44	0	26	0	0
T51	0	28	0	0
T55	425	0	0	0
T62	0	38	0	0
T126	0	34	0	0
T155	0	44	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421671	0	0
T11	931	530	0	0
T12	632	229	0	0
T13	554	153	0	0
T14	1082	677	0	0
T15	16806	7856	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3	0	0
T65	26851	1	0	0
T105	4267	0	0	0
T201	0	1	0	0
T222	25128	1	0	0
T223	489	0	0	0
T224	503	0	0	0
T225	521	0	0	0
T226	424	0	0	0
T227	501	0	0	0
T228	8419	0	0	0
T229	9248	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	33781	0	0
T12	632	45	0	0
T13	554	0	0	0
T14	1082	100	0	0
T15	16806	248	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	72	0	0
T43	0	17834	0	0
T44	0	65	0	0
T51	0	46	0	0
T55	425	0	0	0
T62	0	138	0	0
T155	0	122	0	0
T157	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	78	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6152093	0	0
T11	931	530	0	0
T12	632	3	0	0
T13	554	153	0	0
T14	1082	3	0	0
T15	16806	7567	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6154582	0	0
T11	931	531	0	0
T12	632	3	0	0
T13	554	154	0	0
T14	1082	3	0	0
T15	16806	7591	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	94	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T126	0	1	0	0
T155	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	81	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	78	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	78	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T51	0	1	0	0
T55	425	0	0	0
T62	0	1	0	0
T155	0	1	0	0
T157	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	33668	0	0
T12	632	43	0	0
T13	554	0	0	0
T14	1082	97	0	0
T15	16806	246	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	71	0	0
T43	0	17833	0	0
T44	0	63	0	0
T51	0	44	0	0
T55	425	0	0	0
T62	0	137	0	0
T155	0	120	0	0
T157	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	42	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T46	4767	0	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T62	0	1	0	0
T65	0	1	0	0
T86	0	1	0	0
T140	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T11,T14,T18

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T14,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T27,T29,T30
1	1	Covered	T11,T14,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T18
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T14,T18
0	1	Covered	T11,T14,T65
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T14,T18
1	-	Covered	T11,T14,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T14,T18
0	1	Covered	T11,T14,T18
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T18
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T14,T18
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T14,T18
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T14,T18
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T14,T18
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T14,T65
StableSt	-	-	-	-	-	-	0	Covered	T11,T14,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	99	0	0
CntIncr_A	7120944	20558	0	0
CntNoWrap_A	7120944	6421747	0	0
DetectStDropOut_A	7120944	0	0	0
DetectedOut_A	7120944	57195	0	0
DetectedPulseOut_A	7120944	49	0	0
DisabledIdleSt_A	7120944	6216833	0	0
DisabledNoDetection_A	7120944	6219326	0	0
EnterDebounceSt_A	7120944	50	0	0
EnterDetectSt_A	7120944	49	0	0
EnterStableSt_A	7120944	49	0	0
PulseIsPulse_A	7120944	49	0	0
StayInStableSt	7120944	57119	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	6642	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	99	0	0
T11	931	4	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	0	0	0
T18	0	4	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	4	0	0
T43	0	2	0	0
T45	0	2	0	0
T62	0	2	0	0
T65	0	2	0	0
T126	0	2	0	0
T160	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	20558	0	0
T11	931	108	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	75	0	0
T15	16806	0	0	0
T18	0	136	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	96	0	0
T43	0	17871	0	0
T45	0	58	0	0
T62	0	38	0	0
T65	0	86	0	0
T126	0	34	0	0
T160	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421747	0	0
T11	931	526	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	679	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	57195	0	0
T11	931	229	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	346	0	0
T15	16806	0	0	0
T18	0	149	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	285	0	0
T43	0	52989	0	0
T45	0	303	0	0
T62	0	37	0	0
T65	0	104	0	0
T126	0	39	0	0
T160	0	124	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T126	0	1	0	0
T160	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6216833	0	0
T11	931	3	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	4259	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6219326	0	0
T11	931	3	0	0
T12	632	3	0	0
T13	554	4	0	0
T14	1082	3	0	0
T15	16806	4282	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	50	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T126	0	1	0	0
T160	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T126	0	1	0	0
T160	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T126	0	1	0	0
T160	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0
T65	0	1	0	0
T126	0	1	0	0
T160	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	57119	0	0
T11	931	226	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	345	0	0
T15	16806	0	0	0
T18	0	145	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	281	0	0
T43	0	52987	0	0
T45	0	301	0	0
T62	0	35	0	0
T65	0	103	0	0
T126	0	37	0	0
T160	0	121	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6642	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	40	0	0
T16	0	11	0	0
T27	523	6	0	0
T28	510	0	0	0
T29	468	1	0	0
T30	523	4	0	0
T31	8808	30	0	0
T46	0	35	0	0
T55	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	21	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	1	0	0
T15	16806	0	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	2	0	0
T140	0	1	0	0
T151	0	3	0	0
T160	0	1	0	0
T186	0	1	0	0
T208	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T12,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T27
1	1	Covered	T11,T12,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T18,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T12,T18,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T12,T18,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T15,T18
1	0	Covered	T11,T27,T28
1	1	Covered	T12,T18,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T18,T43
0	1	Covered	T86,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T18,T43
0	1	Covered	T12,T18,T43
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T18,T43
1	-	Covered	T12,T18,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T18,T43
0	1	Covered	T12,T18,T43
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T18,T43
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T18,T43
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T18,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T126,T92,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T18,T43
DetectSt	-	-	-	-	1	-	-	Covered	T86,T88
DetectSt	-	-	-	-	0	1	-	Covered	T12,T18,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T18,T43
StableSt	-	-	-	-	-	-	0	Covered	T12,T18,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	146	0	0
CntIncr_A	7120944	21932	0	0
CntNoWrap_A	7120944	6421700	0	0
DetectStDropOut_A	7120944	2	0	0
DetectedOut_A	7120944	22953	0	0
DetectedPulseOut_A	7120944	65	0	0
DisabledIdleSt_A	7120944	6140753	0	0
DisabledNoDetection_A	7120944	6143249	0	0
EnterDebounceSt_A	7120944	79	0	0
EnterDetectSt_A	7120944	67	0	0
EnterStableSt_A	7120944	65	0	0
PulseIsPulse_A	7120944	65	0	0
StayInStableSt	7120944	22860	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	146	0	0
T12	632	2	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T55	425	0	0	0
T65	0	4	0	0
T92	0	1	0	0
T126	0	1	0	0
T222	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	21932	0	0
T12	632	76	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	67	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	19	0	0
T43	0	17871	0	0
T44	0	26	0	0
T45	0	58	0	0
T55	425	0	0	0
T65	0	26	0	0
T92	0	33	0	0
T126	0	34	0	0
T222	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421700	0	0
T11	931	530	0	0
T12	632	229	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	2	0	0
T86	79812	1	0	0
T88	26911	1	0	0
T143	691	0	0	0
T144	502	0	0	0
T145	410	0	0	0
T146	975	0	0	0
T147	410	0	0	0
T148	531	0	0	0
T230	12247	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	22953	0	0
T12	632	25	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	5	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	159	0	0
T43	0	17835	0	0
T44	0	1	0	0
T45	0	141	0	0
T55	425	0	0	0
T65	0	88	0	0
T176	0	39	0	0
T209	0	133	0	0
T222	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	65	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	2	0	0
T176	0	1	0	0
T209	0	1	0	0
T222	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6140753	0	0
T11	931	530	0	0
T12	632	3	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	4550	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6143249	0	0
T11	931	531	0	0
T12	632	3	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	4574	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	79	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	2	0	0
T92	0	1	0	0
T126	0	1	0	0
T222	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	67	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	2	0	0
T176	0	1	0	0
T209	0	1	0	0
T222	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	65	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	2	0	0
T176	0	1	0	0
T209	0	1	0	0
T222	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	65	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T55	425	0	0	0
T65	0	2	0	0
T176	0	1	0	0
T209	0	1	0	0
T222	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	22860	0	0
T12	632	24	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	4	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	157	0	0
T43	0	17834	0	0
T45	0	139	0	0
T55	425	0	0	0
T65	0	85	0	0
T140	0	115	0	0
T176	0	38	0	0
T209	0	131	0	0
T222	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	36	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T18	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T55	425	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T140	0	3	0	0
T146	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T11,T12,T27
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T27
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T17,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T11,T17,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T11,T17,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T13,T17
1	0	Covered	T12,T27,T14
1	1	Covered	T11,T17,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T17,T43
0	1	Covered	T65,T208,T87
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T17,T43
1	-	Covered	T65,T208,T87

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T17,T43
0	1	Covered	T11,T17,T43
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T17,T43
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T17,T43
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T77
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T17,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T87,T231
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T17,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T17,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T65,T208,T87
StableSt	-	-	-	-	-	-	0	Covered	T11,T17,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	101	0	0
CntIncr_A	7120944	29382	0	0
CntNoWrap_A	7120944	6421745	0	0
DetectStDropOut_A	7120944	0	0	0
DetectedOut_A	7120944	63510	0	0
DetectedPulseOut_A	7120944	49	0	0
DisabledIdleSt_A	7120944	6194776	0	0
DisabledNoDetection_A	7120944	6197268	0	0
EnterDebounceSt_A	7120944	53	0	0
EnterDetectSt_A	7120944	49	0	0
EnterStableSt_A	7120944	49	0	0
PulseIsPulse_A	7120944	49	0	0
StayInStableSt	7120944	63441	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7120944	7248	0	0
gen_low_level_sva.LowLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	101	0	0
T11	931	2	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	2	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	2	0	0
T65	0	2	0	0
T86	0	6	0	0
T87	0	3	0	0
T126	0	2	0	0
T140	0	4	0	0
T176	0	2	0	0
T208	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	29382	0	0
T11	931	54	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	23	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	17871	0	0
T65	0	86	0	0
T86	0	216	0	0
T87	0	66	0	0
T126	0	34	0	0
T140	0	180	0	0
T176	0	58	0	0
T208	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6421745	0	0
T11	931	528	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	63510	0	0
T11	931	40	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	81	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	52988	0	0
T65	0	43	0	0
T86	0	123	0	0
T87	0	23	0	0
T126	0	40	0	0
T140	0	84	0	0
T176	0	46	0	0
T208	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T65	0	1	0	0
T86	0	3	0	0
T87	0	1	0	0
T126	0	1	0	0
T140	0	2	0	0
T176	0	1	0	0
T208	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6194776	0	0
T11	931	3	0	0
T12	632	231	0	0
T13	554	4	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6197268	0	0
T11	931	3	0	0
T12	632	232	0	0
T13	554	4	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T65	0	1	0	0
T86	0	3	0	0
T87	0	2	0	0
T126	0	1	0	0
T140	0	2	0	0
T176	0	1	0	0
T208	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T65	0	1	0	0
T86	0	3	0	0
T87	0	1	0	0
T126	0	1	0	0
T140	0	2	0	0
T176	0	1	0	0
T208	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T65	0	1	0	0
T86	0	3	0	0
T87	0	1	0	0
T126	0	1	0	0
T140	0	2	0	0
T176	0	1	0	0
T208	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T11	931	1	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	1	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	1	0	0
T65	0	1	0	0
T86	0	3	0	0
T87	0	1	0	0
T126	0	1	0	0
T140	0	2	0	0
T176	0	1	0	0
T208	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	63441	0	0
T11	931	38	0	0
T12	632	0	0	0
T13	554	0	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T17	0	79	0	0
T27	523	0	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	0	0	0
T31	8808	0	0	0
T43	0	52986	0	0
T65	0	42	0	0
T86	0	119	0	0
T87	0	22	0	0
T126	0	38	0	0
T140	0	81	0	0
T176	0	44	0	0
T208	0	84	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	7248	0	0
T11	931	1	0	0
T12	632	1	0	0
T13	554	0	0	0
T14	1082	2	0	0
T15	16806	57	0	0
T16	0	10	0	0
T27	523	4	0	0
T28	510	0	0	0
T29	468	0	0	0
T30	523	4	0	0
T31	8808	30	0	0
T55	0	1	0	0
T56	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	28	0	0
T65	26851	1	0	0
T86	0	2	0	0
T87	20185	1	0	0
T140	0	1	0	0
T151	0	3	0	0
T167	0	1	0	0
T169	0	1	0	0
T177	0	1	0	0
T208	11849	1	0	0
T211	0	1	0	0
T223	489	0	0	0
T224	503	0	0	0
T225	521	0	0	0
T226	424	0	0	0
T227	501	0	0	0
T228	8419	0	0	0
T232	11225	0	0	0