Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T46,T47
1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T29,T31,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T29,T31,T46

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T29,T31,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T46,T47
1	0	Covered	T31,T38,T41
1	1	Covered	T29,T31,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T46
0	1	Covered	T46,T47,T38
1	0	Covered	T38,T83,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T31,T48
0	1	Covered	T31,T41,T49
1	0	Covered	T84,T198,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T29,T31,T48
1	-	Covered	T31,T41,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T31,T46
0	1	Covered	T29,T31,T46
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T29,T31,T46
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T29,T31,T46
IdleSt	0	-	-	-	-	-	-	Covered	T31,T46,T47
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T31,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T233,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T31,T46
DetectSt	-	-	-	-	1	-	-	Covered	T46,T47,T38
DetectSt	-	-	-	-	0	1	-	Covered	T29,T31,T48
DetectSt	-	-	-	-	0	0	-	Covered	T29,T31,T46
StableSt	-	-	-	-	-	-	1	Covered	T31,T41,T49
StableSt	-	-	-	-	-	-	0	Covered	T29,T31,T48
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	3107	0	0
CntIncr_A	7120944	107829	0	0
CntNoWrap_A	7120944	6418739	0	0
DetectStDropOut_A	7120944	430	0	0
DetectedOut_A	7120944	76243	0	0
DetectedPulseOut_A	7120944	814	0	0
DisabledIdleSt_A	7120944	5946209	0	0
DisabledNoDetection_A	7120944	5948553	0	0
EnterDebounceSt_A	7120944	1569	0	0
EnterDetectSt_A	7120944	1539	0	0
EnterStableSt_A	7120944	814	0	0
PulseIsPulse_A	7120944	814	0	0
StayInStableSt	7120944	75309	0	0
gen_high_event_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	679	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3107	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	2	0	0
T30	523	0	0	0
T31	8808	38	0	0
T38	0	24	0	0
T41	0	50	0	0
T46	4767	70	0	0
T47	0	40	0	0
T48	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T93	0	15	0	0
T103	0	44	0	0
T104	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	107829	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	21	0	0
T30	523	0	0	0
T31	8808	969	0	0
T38	0	711	0	0
T41	0	1425	0	0
T46	4767	1501	0	0
T47	0	881	0	0
T48	0	21	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T93	0	450	0	0
T103	0	1318	0	0
T104	0	1370	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6418739	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	65	0	0
T30	523	122	0	0
T31	8808	8358	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	430	0	0
T17	601	0	0	0
T38	0	4	0	0
T46	4767	35	0	0
T47	4816	20	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T72	496	0	0	0
T78	0	10	0	0
T102	526	0	0	0
T103	0	22	0	0
T104	0	24	0	0
T105	0	16	0	0
T106	0	5	0	0
T107	0	17	0	0
T234	0	10	0	0
T235	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	76243	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	42	0	0
T30	523	0	0	0
T31	8808	359	0	0
T41	0	2318	0	0
T46	4767	0	0	0
T48	0	40	0	0
T49	0	1356	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T82	0	576	0	0
T130	0	2273	0	0
T184	0	930	0	0
T236	0	1770	0	0
T237	0	1559	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	814	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	19	0	0
T41	0	25	0	0
T46	4767	0	0	0
T48	0	1	0	0
T49	0	27	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T82	0	3	0	0
T130	0	26	0	0
T184	0	20	0	0
T236	0	14	0	0
T237	0	30	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5946209	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	4	0	0
T30	523	122	0	0
T31	8808	5134	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5948553	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	4	0	0
T30	523	123	0	0
T31	8808	5134	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1569	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	19	0	0
T38	0	12	0	0
T41	0	25	0	0
T46	4767	35	0	0
T47	0	20	0	0
T48	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T93	0	15	0	0
T103	0	22	0	0
T104	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1539	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	19	0	0
T38	0	12	0	0
T41	0	25	0	0
T46	4767	35	0	0
T47	0	20	0	0
T48	0	1	0	0
T49	0	27	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T103	0	22	0	0
T104	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	814	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	19	0	0
T41	0	25	0	0
T46	4767	0	0	0
T48	0	1	0	0
T49	0	27	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T82	0	3	0	0
T130	0	26	0	0
T184	0	20	0	0
T236	0	14	0	0
T237	0	30	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	814	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	19	0	0
T41	0	25	0	0
T46	4767	0	0	0
T48	0	1	0	0
T49	0	27	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T82	0	3	0	0
T130	0	26	0	0
T184	0	20	0	0
T236	0	14	0	0
T237	0	30	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	75309	0	0
T14	1082	0	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T29	468	40	0	0
T30	523	0	0	0
T31	8808	339	0	0
T41	0	2289	0	0
T46	4767	0	0	0
T48	0	38	0	0
T49	0	1328	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T82	0	572	0	0
T130	0	2245	0	0
T184	0	908	0	0
T236	0	1752	0	0
T237	0	1528	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	679	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	18	0	0
T41	0	21	0	0
T46	4767	0	0	0
T49	0	26	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T82	0	2	0	0
T130	0	24	0	0
T184	0	18	0	0
T229	0	11	0	0
T236	0	10	0	0
T237	0	29	0	0
T238	0	24	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T29,T31,T15
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T29,T31,T15
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T29,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T29,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T15,T16,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T31,T15
1	0	Covered	T31,T15,T16
1	1	Covered	T29,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T18
0	1	Covered	T16,T39,T87
1	0	Covered	T76,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Covered	T15,T18,T19
1	0	Covered	T79,T76,T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T18,T19
1	-	Covered	T15,T18,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T29,T15,T16
0	1	Covered	T29,T15,T16
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T18
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T16,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T15,T16
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T16,T39,T87
DetectSt	-	-	-	-	0	1	-	Covered	T15,T18,T19
DetectSt	-	-	-	-	0	0	-	Covered	T15,T16,T18
StableSt	-	-	-	-	-	-	1	Covered	T15,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T15,T18,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	1030	0	0
CntIncr_A	7120944	54424	0	0
CntNoWrap_A	7120944	6420816	0	0
DetectStDropOut_A	7120944	60	0	0
DetectedOut_A	7120944	16888	0	0
DetectedPulseOut_A	7120944	411	0	0
DisabledIdleSt_A	7120944	5991779	0	0
DisabledNoDetection_A	7120944	5993513	0	0
EnterDebounceSt_A	7120944	557	0	0
EnterDetectSt_A	7120944	475	0	0
EnterStableSt_A	7120944	411	0	0
PulseIsPulse_A	7120944	411	0	0
StayInStableSt	7120944	16431	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	362	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1030	0	0
T14	1082	0	0	0
T15	16806	3	0	0
T16	14020	17	0	0
T18	0	3	0	0
T19	0	2	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	15	0	0
T42	0	6	0	0
T46	4767	0	0	0
T48	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T95	0	2	0	0
T96	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	54424	0	0
T14	1082	0	0	0
T15	16806	65	0	0
T16	14020	1041	0	0
T18	0	109	0	0
T19	0	25	0	0
T29	468	20	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	872	0	0
T42	0	327	0	0
T46	4767	0	0	0
T48	0	20	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T95	0	239	0	0
T96	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6420816	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7855	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	66	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	60	0	0
T16	14020	8	0	0
T17	601	0	0	0
T39	45220	6	0	0
T46	4767	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T87	0	2	0	0
T102	526	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	5	0	0
T111	0	3	0	0
T112	0	2	0	0
T113	0	15	0	0
T114	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	16888	0	0
T15	16806	3	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	3	0	0
T19	0	3	0	0
T40	0	6	0	0
T41	0	289	0	0
T42	0	207	0	0
T46	4767	0	0	0
T49	0	156	0	0
T52	0	69	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	9	0	0
T125	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	411	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T40	0	1	0	0
T41	0	4	0	0
T42	0	3	0	0
T46	4767	0	0	0
T49	0	3	0	0
T52	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	1	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5991779	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7718	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	26	0	0
T30	523	122	0	0
T31	8808	8038	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5993513	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7740	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	26	0	0
T30	523	123	0	0
T31	8808	8039	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	557	0	0
T14	1082	0	0	0
T15	16806	3	0	0
T16	14020	9	0	0
T18	0	3	0	0
T19	0	1	0	0
T29	468	1	0	0
T30	523	0	0	0
T31	8808	0	0	0
T39	0	9	0	0
T42	0	3	0	0
T46	4767	0	0	0
T48	0	1	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T95	0	1	0	0
T96	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	475	0	0
T15	16806	1	0	0
T16	14020	8	0	0
T17	601	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T39	0	6	0	0
T40	0	1	0	0
T41	0	4	0	0
T42	0	3	0	0
T46	4767	0	0	0
T52	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	411	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T40	0	1	0	0
T41	0	4	0	0
T42	0	3	0	0
T46	4767	0	0	0
T49	0	3	0	0
T52	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	1	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	411	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T40	0	1	0	0
T41	0	4	0	0
T42	0	3	0	0
T46	4767	0	0	0
T49	0	3	0	0
T52	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	1	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	16431	0	0
T15	16806	2	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	2	0	0
T19	0	2	0	0
T40	0	5	0	0
T41	0	285	0	0
T42	0	204	0	0
T46	4767	0	0	0
T49	0	153	0	0
T52	0	67	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	8	0	0
T125	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	362	0	0
T15	16806	1	0	0
T16	14020	0	0	0
T17	601	0	0	0
T18	0	1	0	0
T19	0	1	0	0
T40	0	1	0	0
T41	0	4	0	0
T42	0	3	0	0
T46	4767	0	0	0
T49	0	3	0	0
T52	0	2	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	1	0	0
T125	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T46,T47
1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T46,T47
1	0	Covered	T31,T38,T41
1	1	Covered	T31,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T46,T47
0	1	Covered	T46,T47,T103
1	0	Covered	T82,T184,T238

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T38,T41
0	1	Covered	T31,T38,T41
1	0	Covered	T85,T239

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T38,T41
1	-	Covered	T31,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T46,T47
0	1	Covered	T31,T46,T47
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T46,T47
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T31,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T31,T46,T47
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T233,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T46,T47
DetectSt	-	-	-	-	1	-	-	Covered	T46,T47,T103
DetectSt	-	-	-	-	0	1	-	Covered	T31,T38,T41
DetectSt	-	-	-	-	0	0	-	Covered	T31,T46,T47
StableSt	-	-	-	-	-	-	1	Covered	T31,T38,T41
StableSt	-	-	-	-	-	-	0	Covered	T31,T38,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	3162	0	0
CntIncr_A	7120944	112903	0	0
CntNoWrap_A	7120944	6418684	0	0
DetectStDropOut_A	7120944	490	0	0
DetectedOut_A	7120944	66942	0	0
DetectedPulseOut_A	7120944	795	0	0
DisabledIdleSt_A	7120944	5953330	0	0
DisabledNoDetection_A	7120944	5955701	0	0
EnterDebounceSt_A	7120944	1611	0	0
EnterDetectSt_A	7120944	1552	0	0
EnterStableSt_A	7120944	795	0	0
PulseIsPulse_A	7120944	795	0	0
StayInStableSt	7120944	66052	0	0
gen_high_event_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	692	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3162	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	44	0	0
T38	0	58	0	0
T41	0	28	0	0
T46	4767	30	0	0
T47	0	56	0	0
T49	0	18	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	28	0	0
T103	0	48	0	0
T104	0	50	0	0
T130	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	112903	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	1166	0	0
T38	0	1450	0	0
T41	0	714	0	0
T46	4767	640	0	0
T47	0	1237	0	0
T49	0	648	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	840	0	0
T103	0	1436	0	0
T104	0	1428	0	0
T130	0	679	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6418684	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8352	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	490	0	0
T17	601	0	0	0
T46	4767	15	0	0
T47	4816	28	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T72	496	0	0	0
T82	0	11	0	0
T102	526	0	0	0
T103	0	24	0	0
T104	0	25	0	0
T105	0	12	0	0
T106	0	10	0	0
T107	0	14	0	0
T234	0	14	0	0
T235	506	0	0	0
T238	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	66942	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	1386	0	0
T38	0	1848	0	0
T41	0	927	0	0
T46	4767	0	0	0
T49	0	314	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	71	0	0
T83	0	3557	0	0
T130	0	218	0	0
T229	0	14	0	0
T236	0	3386	0	0
T237	0	1742	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	795	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	29	0	0
T41	0	14	0	0
T46	4767	0	0	0
T49	0	9	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	11	0	0
T83	0	12	0	0
T130	0	7	0	0
T229	0	1	0	0
T236	0	22	0	0
T237	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5953330	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	4081	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5955701	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	4081	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1611	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	29	0	0
T41	0	14	0	0
T46	4767	15	0	0
T47	0	28	0	0
T49	0	9	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	28	0	0
T103	0	24	0	0
T104	0	25	0	0
T130	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1552	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	29	0	0
T41	0	14	0	0
T46	4767	15	0	0
T47	0	28	0	0
T49	0	9	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T82	0	13	0	0
T103	0	24	0	0
T104	0	25	0	0
T130	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	795	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	29	0	0
T41	0	14	0	0
T46	4767	0	0	0
T49	0	9	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	11	0	0
T83	0	12	0	0
T130	0	7	0	0
T229	0	1	0	0
T236	0	22	0	0
T237	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	795	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	22	0	0
T38	0	29	0	0
T41	0	14	0	0
T46	4767	0	0	0
T49	0	9	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	11	0	0
T83	0	12	0	0
T130	0	7	0	0
T229	0	1	0	0
T236	0	22	0	0
T237	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	66052	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	1363	0	0
T38	0	1818	0	0
T41	0	911	0	0
T46	4767	0	0	0
T49	0	304	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	60	0	0
T83	0	3543	0	0
T130	0	211	0	0
T229	0	13	0	0
T236	0	3358	0	0
T237	0	1714	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	692	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	21	0	0
T38	0	28	0	0
T41	0	12	0	0
T46	4767	0	0	0
T49	0	8	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	11	0	0
T83	0	10	0	0
T130	0	7	0	0
T229	0	1	0	0
T236	0	16	0	0
T237	0	26	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T16,T46
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T16,T46
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T16,T18

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T31,T16,T18

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T16,T18

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T16,T18
1	0	Covered	T31,T15,T16
1	1	Covered	T31,T16,T18

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T16,T18
0	1	Covered	T240,T153,T151
1	0	Covered	T76,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T16,T18
0	1	Covered	T16,T18,T38
1	0	Covered	T76,T77

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T16,T18
1	-	Covered	T16,T18,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T16,T18
0	1	Covered	T31,T16,T18
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T16,T18
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T16,T18
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T16,T18
DebounceSt	-	0	1	0	-	-	-	Covered	T16,T18,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T16,T18
DetectSt	-	-	-	-	1	-	-	Covered	T240,T153,T151
DetectSt	-	-	-	-	0	1	-	Covered	T31,T16,T18
DetectSt	-	-	-	-	0	0	-	Covered	T31,T16,T18
StableSt	-	-	-	-	-	-	1	Covered	T16,T18,T38
StableSt	-	-	-	-	-	-	0	Covered	T31,T16,T18
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	880	0	0
CntIncr_A	7120944	55298	0	0
CntNoWrap_A	7120944	6420966	0	0
DetectStDropOut_A	7120944	49	0	0
DetectedOut_A	7120944	13650	0	0
DetectedPulseOut_A	7120944	363	0	0
DisabledIdleSt_A	7120944	6009295	0	0
DisabledNoDetection_A	7120944	6011125	0	0
EnterDebounceSt_A	7120944	464	0	0
EnterDetectSt_A	7120944	417	0	0
EnterStableSt_A	7120944	363	0	0
PulseIsPulse_A	7120944	363	0	0
StayInStableSt	7120944	13241	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	315	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	880	0	0
T15	16806	0	0	0
T16	14020	7	0	0
T17	601	0	0	0
T18	0	5	0	0
T31	8808	2	0	0
T38	0	2	0	0
T39	0	8	0	0
T40	0	21	0	0
T41	0	2	0	0
T42	0	2	0	0
T46	4767	0	0	0
T52	0	8	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T125	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	55298	0	0
T15	16806	0	0	0
T16	14020	379	0	0
T17	601	0	0	0
T18	0	199	0	0
T31	8808	70	0	0
T38	0	45	0	0
T39	0	496	0	0
T40	0	1783	0	0
T41	0	60	0	0
T42	0	158	0	0
T46	4767	0	0	0
T52	0	792	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T125	0	190	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6420966	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8394	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	49	0	0
T62	5493	0	0	0
T63	1603	0	0	0
T81	0	3	0	0
T94	559	0	0	0
T100	737	0	0	0
T111	0	5	0	0
T113	0	2	0	0
T151	0	3	0	0
T153	11725	1	0	0
T240	50187	8	0	0
T241	0	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	0	8	0	0
T245	686	0	0	0
T246	522	0	0	0
T247	502	0	0	0
T248	492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	13650	0	0
T15	16806	0	0	0
T16	14020	61	0	0
T17	601	0	0	0
T18	0	130	0	0
T31	8808	42	0	0
T38	0	88	0	0
T39	0	17	0	0
T40	0	315	0	0
T41	0	60	0	0
T46	4767	0	0	0
T52	0	23	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T74	0	298	0	0
T125	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	363	0	0
T15	16806	0	0	0
T16	14020	3	0	0
T17	601	0	0	0
T18	0	2	0	0
T31	8808	1	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	10	0	0
T41	0	1	0	0
T46	4767	0	0	0
T52	0	4	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T74	0	5	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6009295	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	7011	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6011125	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	7012	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	464	0	0
T15	16806	0	0	0
T16	14020	4	0	0
T17	601	0	0	0
T18	0	3	0	0
T31	8808	1	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	11	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	4767	0	0	0
T52	0	4	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T125	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	417	0	0
T15	16806	0	0	0
T16	14020	3	0	0
T17	601	0	0	0
T18	0	2	0	0
T31	8808	1	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	10	0	0
T41	0	1	0	0
T46	4767	0	0	0
T52	0	4	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T74	0	5	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	363	0	0
T15	16806	0	0	0
T16	14020	3	0	0
T17	601	0	0	0
T18	0	2	0	0
T31	8808	1	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	10	0	0
T41	0	1	0	0
T46	4767	0	0	0
T52	0	4	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T74	0	5	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	363	0	0
T15	16806	0	0	0
T16	14020	3	0	0
T17	601	0	0	0
T18	0	2	0	0
T31	8808	1	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	10	0	0
T41	0	1	0	0
T46	4767	0	0	0
T52	0	4	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T74	0	5	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	13241	0	0
T15	16806	0	0	0
T16	14020	58	0	0
T17	601	0	0	0
T18	0	128	0	0
T31	8808	40	0	0
T38	0	87	0	0
T39	0	13	0	0
T40	0	305	0	0
T41	0	59	0	0
T46	4767	0	0	0
T52	0	19	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T74	0	293	0	0
T125	0	74	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	315	0	0
T16	14020	3	0	0
T17	601	0	0	0
T18	30837	2	0	0
T38	0	1	0	0
T39	0	4	0	0
T40	0	10	0	0
T41	0	1	0	0
T46	4767	0	0	0
T52	0	4	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T74	0	5	0	0
T102	526	0	0	0
T125	0	1	0	0
T154	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T46,T47
1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T31,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T46,T47
1	0	Covered	T31,T38,T41
1	1	Covered	T31,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T46,T47
0	1	Covered	T46,T47,T103
1	0	Covered	T38,T236,T84

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T41,T49
0	1	Covered	T31,T41,T49
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T41,T49
1	-	Covered	T31,T41,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T31,T46,T47
0	1	Covered	T31,T46,T47
0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T46,T47
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T31,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T31,T46,T47
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T93,T233,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T46,T47
DetectSt	-	-	-	-	1	-	-	Covered	T46,T47,T38
DetectSt	-	-	-	-	0	1	-	Covered	T31,T41,T49
DetectSt	-	-	-	-	0	0	-	Covered	T31,T46,T47
StableSt	-	-	-	-	-	-	1	Covered	T31,T41,T49
StableSt	-	-	-	-	-	-	0	Covered	T31,T41,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	3117	0	0
CntIncr_A	7120944	105179	0	0
CntNoWrap_A	7120944	6418729	0	0
DetectStDropOut_A	7120944	418	0	0
DetectedOut_A	7120944	92944	0	0
DetectedPulseOut_A	7120944	962	0	0
DisabledIdleSt_A	7120944	5935238	0	0
DisabledNoDetection_A	7120944	5937580	0	0
EnterDebounceSt_A	7120944	1578	0	0
EnterDetectSt_A	7120944	1541	0	0
EnterStableSt_A	7120944	962	0	0
PulseIsPulse_A	7120944	962	0	0
StayInStableSt	7120944	91859	0	0
gen_high_event_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	838	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	3117	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	14	0	0
T38	0	32	0	0
T41	0	12	0	0
T46	4767	30	0	0
T47	0	60	0	0
T49	0	44	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	14	0	0
T103	0	22	0	0
T104	0	16	0	0
T130	0	58	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	105179	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	308	0	0
T38	0	953	0	0
T41	0	300	0	0
T46	4767	642	0	0
T47	0	1322	0	0
T49	0	1540	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	420	0	0
T103	0	652	0	0
T104	0	451	0	0
T130	0	2088	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6418729	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8382	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	418	0	0
T17	601	0	0	0
T46	4767	15	0	0
T47	4816	30	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T72	496	0	0	0
T84	0	5	0	0
T102	526	0	0	0
T103	0	11	0	0
T104	0	8	0	0
T105	0	29	0	0
T106	0	21	0	0
T107	0	26	0	0
T235	506	0	0	0
T236	0	14	0	0
T249	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	92944	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	92	0	0
T41	0	422	0	0
T46	4767	0	0	0
T49	0	1489	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	1640	0	0
T83	0	2732	0	0
T130	0	1786	0	0
T184	0	542	0	0
T229	0	2583	0	0
T237	0	774	0	0
T250	0	1285	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	962	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	7	0	0
T41	0	6	0	0
T46	4767	0	0	0
T49	0	22	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	16	0	0
T83	0	12	0	0
T130	0	29	0	0
T184	0	5	0	0
T229	0	26	0	0
T237	0	23	0	0
T250	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5935238	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	5411	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5937580	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	5412	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1578	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	7	0	0
T38	0	16	0	0
T41	0	6	0	0
T46	4767	15	0	0
T47	0	30	0	0
T49	0	22	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T93	0	14	0	0
T103	0	11	0	0
T104	0	8	0	0
T130	0	29	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	1541	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	7	0	0
T38	0	16	0	0
T41	0	6	0	0
T46	4767	15	0	0
T47	0	30	0	0
T49	0	22	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T83	0	12	0	0
T103	0	11	0	0
T104	0	8	0	0
T130	0	29	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	962	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	7	0	0
T41	0	6	0	0
T46	4767	0	0	0
T49	0	22	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	16	0	0
T83	0	12	0	0
T130	0	29	0	0
T184	0	5	0	0
T229	0	26	0	0
T237	0	23	0	0
T250	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	962	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	7	0	0
T41	0	6	0	0
T46	4767	0	0	0
T49	0	22	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	16	0	0
T83	0	12	0	0
T130	0	29	0	0
T184	0	5	0	0
T229	0	26	0	0
T237	0	23	0	0
T250	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	91859	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	85	0	0
T41	0	415	0	0
T46	4767	0	0	0
T49	0	1466	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	1624	0	0
T83	0	2717	0	0
T130	0	1757	0	0
T184	0	537	0	0
T229	0	2557	0	0
T237	0	750	0	0
T250	0	1267	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	838	0	0
T15	16806	0	0	0
T16	14020	0	0	0
T17	601	0	0	0
T31	8808	7	0	0
T41	0	5	0	0
T46	4767	0	0	0
T49	0	21	0	0
T55	425	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T78	0	16	0	0
T83	0	9	0	0
T130	0	29	0	0
T184	0	5	0	0
T229	0	26	0	0
T237	0	22	0	0
T250	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T31,T16,T46
1	Covered	T11,T12,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T31,T16,T46
1	0	Covered	T11,T12,T13
1	1	Covered	T11,T12,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T16,T18,T95

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T11,T12,T13	VC_COV_UNR
1	Covered	T16,T18,T95

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T11,T12,T13
1	Covered	T16,T18,T95

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T16,T18
1	0	Covered	T31,T15,T16
1	1	Covered	T16,T18,T95

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T18,T95
0	1	Covered	T16,T18,T251
1	0	Covered	T76,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T95,T39,T42
0	1	Covered	T95,T39,T42
1	0	Covered	T78,T252

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T95,T39,T42
1	-	Covered	T95,T39,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T16,T18,T95
0	1	Covered	T16,T18,T95
0	0	Excluded	T11,T12,T13	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T16,T18,T95
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T18,T95
IdleSt	0	-	-	-	-	-	-	Covered	T11,T12,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76,T77
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T18,T95
DebounceSt	-	0	1	0	-	-	-	Covered	T95,T42,T40
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T18,T95
DetectSt	-	-	-	-	1	-	-	Covered	T16,T18,T251
DetectSt	-	-	-	-	0	1	-	Covered	T95,T39,T42
DetectSt	-	-	-	-	0	0	-	Covered	T16,T18,T95
StableSt	-	-	-	-	-	-	1	Covered	T95,T39,T42
StableSt	-	-	-	-	-	-	0	Covered	T95,T39,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7120944	950	0	0
CntIncr_A	7120944	53449	0	0
CntNoWrap_A	7120944	6420896	0	0
DetectStDropOut_A	7120944	75	0	0
DetectedOut_A	7120944	17852	0	0
DetectedPulseOut_A	7120944	374	0	0
DisabledIdleSt_A	7120944	5982306	0	0
DisabledNoDetection_A	7120944	5984118	0	0
EnterDebounceSt_A	7120944	497	0	0
EnterDetectSt_A	7120944	453	0	0
EnterStableSt_A	7120944	374	0	0
PulseIsPulse_A	7120944	374	0	0
StayInStableSt	7120944	17435	0	0
gen_high_level_sva.HighLevelEvent_A	7120944	6424404	0	0
gen_not_sticky_sva.StableStDropOut_A	7120944	326	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	950	0	0
T16	14020	2	0	0
T17	601	0	0	0
T18	30837	2	0	0
T39	0	30	0	0
T40	0	21	0	0
T41	0	2	0	0
T42	0	19	0	0
T46	4767	0	0	0
T49	0	3	0	0
T52	0	8	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	7	0	0
T102	526	0	0	0
T136	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	53449	0	0
T16	14020	120	0	0
T17	601	0	0	0
T18	30837	136	0	0
T39	0	1215	0	0
T40	0	1643	0	0
T41	0	69	0	0
T42	0	889	0	0
T46	4767	0	0	0
T49	0	119	0	0
T52	0	524	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	597	0	0
T102	526	0	0	0
T136	0	357	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6420896	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8396	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	75	0	0
T16	14020	1	0	0
T17	601	0	0	0
T18	30837	1	0	0
T46	4767	0	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T65	0	1	0	0
T102	526	0	0	0
T108	0	1	0	0
T153	0	1	0	0
T163	0	1	0	0
T222	0	1	0	0
T242	0	9	0	0
T251	0	3	0	0
T253	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	17852	0	0
T39	0	720	0	0
T40	0	455	0	0
T41	0	53	0	0
T42	0	804	0	0
T48	466	0	0	0
T49	0	76	0	0
T51	624	0	0	0
T52	0	292	0	0
T74	0	68	0	0
T95	14733	231	0	0
T96	454	0	0	0
T97	683	0	0	0
T127	423	0	0	0
T128	844	0	0	0
T129	439	0	0	0
T131	1060	0	0	0
T136	0	13	0	0
T154	0	77	0	0
T254	509	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	374	0	0
T39	0	15	0	0
T40	0	10	0	0
T41	0	1	0	0
T42	0	9	0	0
T48	466	0	0	0
T49	0	1	0	0
T51	624	0	0	0
T52	0	4	0	0
T74	0	7	0	0
T95	14733	3	0	0
T96	454	0	0	0
T97	683	0	0	0
T127	423	0	0	0
T128	844	0	0	0
T129	439	0	0	0
T131	1060	0	0	0
T136	0	1	0	0
T154	0	2	0	0
T254	509	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5982306	0	0
T11	931	530	0	0
T12	632	231	0	0
T13	554	153	0	0
T14	1082	681	0	0
T15	16806	7858	0	0
T27	523	122	0	0
T28	510	109	0	0
T29	468	67	0	0
T30	523	122	0	0
T31	8808	8304	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	5984118	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8306	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	497	0	0
T16	14020	1	0	0
T17	601	0	0	0
T18	30837	1	0	0
T39	0	15	0	0
T40	0	11	0	0
T41	0	1	0	0
T42	0	10	0	0
T46	4767	0	0	0
T49	0	2	0	0
T52	0	4	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	4	0	0
T102	526	0	0	0
T136	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	453	0	0
T16	14020	1	0	0
T17	601	0	0	0
T18	30837	1	0	0
T39	0	15	0	0
T40	0	10	0	0
T41	0	1	0	0
T42	0	9	0	0
T46	4767	0	0	0
T49	0	1	0	0
T52	0	4	0	0
T56	1210	0	0	0
T57	421	0	0	0
T58	490	0	0	0
T59	407	0	0	0
T60	1113	0	0	0
T95	0	3	0	0
T102	526	0	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	374	0	0
T39	0	15	0	0
T40	0	10	0	0
T41	0	1	0	0
T42	0	9	0	0
T48	466	0	0	0
T49	0	1	0	0
T51	624	0	0	0
T52	0	4	0	0
T74	0	7	0	0
T95	14733	3	0	0
T96	454	0	0	0
T97	683	0	0	0
T127	423	0	0	0
T128	844	0	0	0
T129	439	0	0	0
T131	1060	0	0	0
T136	0	1	0	0
T154	0	2	0	0
T254	509	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	374	0	0
T39	0	15	0	0
T40	0	10	0	0
T41	0	1	0	0
T42	0	9	0	0
T48	466	0	0	0
T49	0	1	0	0
T51	624	0	0	0
T52	0	4	0	0
T74	0	7	0	0
T95	14733	3	0	0
T96	454	0	0	0
T97	683	0	0	0
T127	423	0	0	0
T128	844	0	0	0
T129	439	0	0	0
T131	1060	0	0	0
T136	0	1	0	0
T154	0	2	0	0
T254	509	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	17435	0	0
T39	0	705	0	0
T40	0	445	0	0
T41	0	52	0	0
T42	0	795	0	0
T48	466	0	0	0
T49	0	75	0	0
T51	624	0	0	0
T52	0	288	0	0
T74	0	61	0	0
T95	14733	228	0	0
T96	454	0	0	0
T97	683	0	0	0
T127	423	0	0	0
T128	844	0	0	0
T129	439	0	0	0
T131	1060	0	0	0
T136	0	12	0	0
T154	0	75	0	0
T254	509	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	6424404	0	0
T11	931	531	0	0
T12	632	232	0	0
T13	554	154	0	0
T14	1082	682	0	0
T15	16806	7883	0	0
T27	523	123	0	0
T28	510	110	0	0
T29	468	68	0	0
T30	523	123	0	0
T31	8808	8398	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7120944	326	0	0
T39	0	15	0	0
T40	0	10	0	0
T41	0	1	0	0
T42	0	9	0	0
T48	466	0	0	0
T49	0	1	0	0
T51	624	0	0	0
T52	0	4	0	0
T74	0	7	0	0
T95	14733	3	0	0
T96	454	0	0	0
T97	683	0	0	0
T127	423	0	0	0
T128	844	0	0	0
T129	439	0	0	0
T131	1060	0	0	0
T136	0	1	0	0
T154	0	2	0	0
T254	509	0	0	0